PKGBUILDs/alarm/uboot-olinuxino/0007-mxs-spl_mem_init-Remove-erroneous-DDR-setting.patch

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2013-05-07 00:10:45 +00:00
From ce10ca38bc54e6e8c6063de18a690f1e065339d6 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Fri, 3 May 2013 04:37:11 +0000
Subject: [PATCH 07/15] mxs: spl_mem_init: Remove erroneous DDR setting
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.
Remove this erroneous setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 300da0a..df25535 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -279,10 +279,6 @@ static void mx23_mem_init(void)
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
- ;
}
#endif
--
1.8.2.2