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32 lines
1 KiB
Diff
32 lines
1 KiB
Diff
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From e61fac261f081b5b68c304c3a7ce849cc08f3f79 Mon Sep 17 00:00:00 2001
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From: Fabio Estevam <fabio.estevam@freescale.com>
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Date: Fri, 3 May 2013 04:37:13 +0000
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Subject: [PATCH 09/15] mxs: spl_mem_init: Change EMI port priority
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FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
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as 0x2, which means:
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PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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---
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arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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index 5eacd36..41fb803 100644
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--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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@@ -287,7 +287,7 @@ static void mx23_mem_init(void)
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early_delay(20000);
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/* Adjust EMI port priority. */
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- clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
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+ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
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early_delay(20000);
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setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
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--
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1.8.2.2
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