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core/linux-espressobin to 4.13.1-1

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This commit is contained in:
Kevin Mihelich 2017-09-13 00:05:47 +00:00
parent c45b8dc0c4
commit 2a2391d3ea
19 changed files with 675 additions and 581 deletions
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10
core/linux-espressobin/0001-ARM64-dts-marvell-armada37xx-Fix-GIC-maintenance-int.patch
View file

@ -1,7 +1,7 @@
From b5470764c194b8930cf0fb65f48e2f2cea6246c5 Mon Sep 17 00:00:00 2001
From 31a3b2d526aded19e5b8e577b95eed1ef534edd8 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:34 +0100
Subject: [PATCH 01/11] ARM64: dts: marvell: armada37xx: Fix GIC maintenance
Subject: [PATCH 01/13] ARM64: dts: marvell: armada37xx: Fix GIC maintenance
interrupt
The GIC-500 integrated in the Armada-37xx SoCs is compliant with
@ -17,10 +17,10 @@ Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index bc179efb10ef..592e95e5f633 100644
index dbcc3d4e2ed5..506aee2e796b 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -312,6 +312,7 @@
@@ -323,6 +323,7 @@
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
<0x1d40000 0x40000>; /* GICR */
@ -29,5 +29,5 @@ index bc179efb10ef..592e95e5f633 100644
};
--
2.13.3
2.14.1

10
core/linux-espressobin/0002-ARM64-dts-marvell-armada37xx-Enable-memory-mapped-GI.patch
View file

@ -1,7 +1,7 @@
From a6e0e494f7213d914963b2aea8e3ff0e9a0e978a Mon Sep 17 00:00:00 2001
From 51039c207512ec118aeec2e18a22f8dafac5c66e Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:35 +0100
Subject: [PATCH 02/11] ARM64: dts: marvell: armada37xx: Enable memory-mapped
Subject: [PATCH 02/13] ARM64: dts: marvell: armada37xx: Enable memory-mapped
GIC CPU interface
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
@ -18,10 +18,10 @@ Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 592e95e5f633..fd26d31d2846 100644
index 506aee2e796b..2dfc09501f9f 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -311,7 +311,10 @@
@@ -322,7 +322,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
@ -34,5 +34,5 @@ index 592e95e5f633..fd26d31d2846 100644
};
};
--
2.13.3
2.14.1

8
core/linux-espressobin/0003-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch
View file

@ -1,7 +1,7 @@
From b61fe18e003c4a37b91092cf4abaee9592bb5a87 Mon Sep 17 00:00:00 2001
From 74c6836db73c9361c34dcc9dfd363f5b447d1b30 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:36 +0100
Subject: [PATCH 03/11] ARM64: dts: marvell: armada37xx: Wire PMUv3
Subject: [PATCH 03/13] ARM64: dts: marvell: armada37xx: Wire PMUv3
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.
@ -15,7 +15,7 @@ Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index fd26d31d2846..f4deb8cd11c6 100644
index 2dfc09501f9f..d6a060d9f083 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -81,6 +81,11 @@
@ -31,5 +31,5 @@ index fd26d31d2846..f4deb8cd11c6 100644
compatible = "simple-bus";
#address-cells = <2>;
--
2.13.3
2.14.1

6
core/linux-espressobin/0004-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch
View file

@ -1,7 +1,7 @@
From d71549275ca1e2bee8e7914501526b625e9f8a53 Mon Sep 17 00:00:00 2001
From bc0a98af7bd04356528338d287a734622d6ce7d1 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:37 +0100
Subject: [PATCH 04/11] ARM64: dts: marvell: armada37xx: Enable USB2 on
Subject: [PATCH 04/13] ARM64: dts: marvell: armada37xx: Enable USB2 on
espressobin
The Espressobin SBC has a USB2 interface available on J8. Let's
@ -29,5 +29,5 @@ index e3a136ed77b0..b1af3f988b29 100644
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
--
2.13.3
2.14.1

6
core/linux-espressobin/0006-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch → core/linux-espressobin/0005-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch
View file

@ -1,7 +1,7 @@
From 1d0dd1ab378af298bf4040edb8ee58d340f48518 Mon Sep 17 00:00:00 2001
From 737f6a0e38813727892484840406ad51c48e0687 Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Fri, 21 Jul 2017 01:50:36 +0200
Subject: [PATCH 06/11] ARM64: dts: marvell: armada-37xx: Enable uSD on
Subject: [PATCH 05/13] ARM64: dts: marvell: armada-37xx: Enable uSD on
ESPRESSObin
The ESPRESSObin board exposes one of the SDHCI interfaces
@ -67,5 +67,5 @@ index b1af3f988b29..2ce52ba74f73 100644
&uart0 {
status = "okay";
--
2.13.3
2.14.1

72
core/linux-espressobin/0005-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch
View file

@ -1,72 +0,0 @@
From aff7d41d285c04f5990247660c860e30029f72b2 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Tue, 23 May 2017 16:11:40 +0300
Subject: [PATCH 05/11] arm64: dts: marvell: Enable second SDHCI controller in
Armada 37xx
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second
one.
Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces.
The second interface is using pluggable module that can either
have an SD connector or eMMC on it.
This patch adds support for SD module in the device DT.
[ gregory.clement@free-electrons.com:
- Add more detail in commit log
- Sort the dt node in address order
- Document the SD slot in the dts ]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +++++++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index a89855f57091..6a0abd7a5349 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,15 @@
status = "okay";
};
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+ wp-inverted;
+ cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ status = "okay";
+};
+
&spi0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index f4deb8cd11c6..a78195b4ef7a 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -293,6 +293,17 @@
};
};
+ sdhci1: sdhci@d0000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
--
2.13.3

8
core/linux-espressobin/0007-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch → core/linux-espressobin/0006-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
View file

@ -1,7 +1,7 @@
From 8440f9edeb29c10cc0ec29c55c07d4e5e5b67c5b Mon Sep 17 00:00:00 2001
From 70883393eeeec4e74164996eee427d3d4b506b77 Mon Sep 17 00:00:00 2001
From: Kevin Mihelich <kevin@archlinuxarm.org>
Date: Tue, 4 Jul 2017 19:25:28 -0600
Subject: [PATCH 07/11] arm64: dts: marvell: armada37xx: Add eth0 alias
Subject: [PATCH 06/13] arm64: dts: marvell: armada37xx: Add eth0 alias
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
---
@ -9,7 +9,7 @@ Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index a78195b4ef7a..14248957b2dd 100644
index d6a060d9f083..d977c760e587 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -54,6 +54,7 @@
@ -21,5 +21,5 @@ index a78195b4ef7a..14248957b2dd 100644
};
--
2.13.3
2.14.1

51
core/linux-espressobin/0007-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch Normal file
View file

@ -0,0 +1,51 @@
From f1e6e40e9a67f39dc559ff49ee7e017cd3165e13 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:42 +0200
Subject: [PATCH 07/13] PCI: aardvark: fix logic in PCI configuration
read/write functions
The PCI configuration space read/write functions were special casing
the situation where PCI_SLOT(devfn) != 0, and returned
PCIBIOS_DEVICE_NOT_FOUND in this case.
However, will this is what is intended for the root bus, it is not
intended for the child busses, as it prevents discovering devices with
PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only
if we're on the root bus.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 5fb9b620ac78..582d75f864e3 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -441,7 +441,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
u32 reg;
int ret;
- if (PCI_SLOT(devfn) != 0) {
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0)) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -495,7 +495,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int offset;
int ret;
- if (PCI_SLOT(devfn) != 0)
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0))
return PCIBIOS_DEVICE_NOT_FOUND;
if (where % size)
--
2.14.1

38
core/linux-espressobin/0008-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch Normal file
View file

@ -0,0 +1,38 @@
From 05e816c4b086bfba96abccf6a3dd8527213bd75d Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:43 +0200
Subject: [PATCH 08/13] PCI: aardvark: set PIO_ADDR_LS correctly in
advk_pcie_rd_conf()
When setting the PIO_ADDR_LS register during a configuration read, we
were properly passing the device number, function number and register
number, but not the bus number, causing issues when reading the
configuration of PCIe devices.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 582d75f864e3..68ff10e17c74 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -460,7 +460,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
--
2.14.1

35
core/linux-espressobin/0008-fix-pci-aardvark-disable-LOS-state-by-default.patch
View file

@ -1,35 +0,0 @@
From c1d0aadc4440c07d2e940c83c1b6e5d9d694a3a5 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Wed, 29 Mar 2017 15:17:03 +0800
Subject: [PATCH 08/11] fix: pci: aardvark: disable LOS state by default
Some PCIe devices do not support LOS, there will be time out issue
if the RC forces the LOS state.
This patch disables the LOS state by default.
Change-Id: I88a6a5cf58ea5f2df234c99050ce041987cdabc6
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38119
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 37d0bcd31f8a..072bc70e900c 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
--
2.13.3

54
core/linux-espressobin/0010-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch → core/linux-espressobin/0009-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch
View file

@ -1,37 +1,55 @@
From dda187271721fbc30329d56fd68034c54e304a44 Mon Sep 17 00:00:00 2001
From 867894fceeaf74327d334f71a14318d4ec847399 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:52:30 +0800
Subject: [PATCH 10/11] pci: aardvard: set host and device to the same MAX
Date: Fri, 8 Sep 2017 11:53:44 +0200
Subject: [PATCH 09/13] PCI: aardvark: set host and device to the same MAX
payload size
Since the Aardvard does not implement PCIe root bus, the Linux PCIe
framework will not align the MAX payload size between host and device
for it.
This patch sets host and device to the same MAX payload size in Aardvard
PCIe driver.
Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
subsystem will not align the MAX payload size between the host and the
device. This patch ensures that the host and device have the same MAX
payload size, fixing a number of problems with various PCIe devices.
Change-Id: I3979397b3af98911c067f7ad384922aa3f05497f
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37927
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 56 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 10154dcf219b..0407c8cb89fb 100644
index 68ff10e17c74..e361c673732f 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -32,6 +32,7 @@
@@ -30,8 +30,10 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
@@ -886,6 +887,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
@@ -298,7 +300,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
@@ -880,6 +883,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
return err;
}
@ -90,7 +108,7 @@ index 10154dcf219b..0407c8cb89fb 100644
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -948,6 +1001,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
@@ -951,6 +1006,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
@ -101,5 +119,5 @@ index 10154dcf219b..0407c8cb89fb 100644
return 0;
}
--
2.13.3
2.14.1

104
core/linux-espressobin/0009-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch
View file

@ -1,104 +0,0 @@
From 364d845b2fd8c083f32a95377f5b3cd3f0cf2323 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Mon, 27 Mar 2017 18:28:25 +0800
Subject: [PATCH 09/11] fix: pci: aardvark: use isr1 interrupt in legacy irq
mode
The Aardvark has two interrupts sets, first set is bit[23:16] of
PCIe ISR 0 register(RD0074840h), second set is bit[11:8] of PCIe
ISR 1 register(RD0074848h). Only one set should be used, while
another set should be masked.
The second set is more advanced, the Legacy INT_X status bit is
asserted once Assert_INTX message is received, and de-asserted after
Deassert_INTX message is received, which provides alternate way
besides of the assert/deassert interrupt pairs in PCIe ISR 0 register.
Change-Id: Idef2eb474a094754195a031ad580caa8a88f046d
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38024
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 072bc70e900c..10154dcf219b 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -103,7 +103,8 @@
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
#define PCIE_ISR1_FLUSH BIT(5)
-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
@@ -612,9 +613,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static void advk_pcie_irq_unmask(struct irq_data *d)
@@ -623,9 +624,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static int advk_pcie_irq_map(struct irq_domain *h,
@@ -769,14 +770,20 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
static void advk_pcie_handle_int(struct advk_pcie *pcie)
{
u32 val, mask, status;
+ u32 val2, mask2, status2;
int i, virq;
val = advk_readl(pcie, PCIE_ISR0_REG);
mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
- if (!status) {
+ val2 = advk_readl(pcie, PCIE_ISR1_REG);
+ mask2 = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ status2 = val2 & ((~mask2) & PCIE_ISR1_ALL_MASK);
+
+ if (!status && !status2) {
advk_writel(pcie, val, PCIE_ISR0_REG);
+ advk_writel(pcie, val2, PCIE_ISR1_REG);
return;
}
@@ -786,11 +793,11 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
/* Process legacy interrupts */
for (i = 0; i < LEGACY_IRQ_NUM; i++) {
- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+ if (!(status2 & PCIE_ISR1_INTX_ASSERT(i)))
continue;
- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+ PCIE_ISR1_REG);
virq = irq_find_mapping(pcie->irq_domain, i);
generic_handle_irq(virq);
--
2.13.3

127
core/linux-espressobin/0010-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-l.patch Normal file
View file

@ -0,0 +1,127 @@
From 8059cc047ea434de114cf1ddebc12843ad7acef7 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:45 +0200
Subject: [PATCH 10/13] PCI: aardvark: use isr1 instead of isr0 interrupt in
legacy irq mode
The Aardvark has two interrupts sets:
- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)
- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)
Only one set should be used, while another set should be masked.
The second set, ISR1, is more advanced, the Legacy INT_X status bit is
asserted once Assert_INTX message is received, and de-asserted after
Deassert_INTX message is received. Therefore, it matches what the
driver is currently doing in the ->irq_mask() and ->irq_unmask()
functions. The ISR0 requires additional work to deassert the
interrupt, which the driver doesn't do currently.
This commit resolves a number of issues with legacy interrupts.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index e361c673732f..4a563d8526ae 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -105,7 +105,8 @@
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
#define PCIE_ISR1_FLUSH BIT(5)
-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
@@ -616,9 +617,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static void advk_pcie_irq_unmask(struct irq_data *d)
@@ -627,9 +628,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static int advk_pcie_irq_map(struct irq_domain *h,
@@ -772,29 +773,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
static void advk_pcie_handle_int(struct advk_pcie *pcie)
{
- u32 val, mask, status;
+ u32 isr0_val, isr0_mask, isr0_status;
+ u32 isr1_val, isr1_mask, isr1_status;
int i, virq;
- val = advk_readl(pcie, PCIE_ISR0_REG);
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
+ isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
+ isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
+ isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
- if (!status) {
- advk_writel(pcie, val, PCIE_ISR0_REG);
+ isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
+ isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
+
+ if (!isr0_status && !isr1_status) {
+ advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
+ advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
return;
}
/* Process MSI interrupts */
- if (status & PCIE_ISR0_MSI_INT_PENDING)
+ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
advk_pcie_handle_msi(pcie);
/* Process legacy interrupts */
for (i = 0; i < LEGACY_IRQ_NUM; i++) {
- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+ if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
continue;
- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+ PCIE_ISR1_REG);
virq = irq_find_mapping(pcie->irq_domain, i);
generic_handle_irq(virq);
--
2.14.1

41
core/linux-espressobin/0011-PCI-aardvark-disable-LOS-state-by-default.patch Normal file
View file

@ -0,0 +1,41 @@
From a433673c37b7306dbf1d268b95243ee42aa273db Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:46 +0200
Subject: [PATCH 11/13] PCI: aardvark: disable LOS state by default
Some PCIe devices do not support LOS, and will cause timeouts if the
root complex forces the LOS state. This patch disables the LOS state
by default.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 4a563d8526ae..461517a87eca 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -369,8 +369,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
--
2.14.1

44
core/linux-espressobin/0011-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch
View file

@ -1,44 +0,0 @@
From 100881d53b53c3c6691a3f3b4ddfc88d738c753b Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:41:55 +0800
Subject: [PATCH 11/11] fix: pcie: aardvark: correct the default MAX payload
size
The previous PCIe MAX payload field is set to 7 which is undefined
value according to functional specification.
The default PICe host controller MAX payload size should be
set to 512 bytes according to specification.
Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37926
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 0407c8cb89fb..cac1558b8d3b 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -30,6 +30,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_MPS_UNIT_BYTE 128
@@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
--
2.13.3

49
core/linux-espressobin/0012-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch Normal file
View file

@ -0,0 +1,49 @@
From 7ba663f19c23e67d01a433486e302462ba30dc1a Mon Sep 17 00:00:00 2001
From: Evan Wang <xswang@marvell.com>
Date: Fri, 8 Sep 2017 11:53:47 +0200
Subject: [PATCH 12/13] PCI: aardvark: fix PCIe max read request size setting
There is an obvious typo issue in the definition of the PCIe maximum
read request size: a bit shift is directly used as a value, while it
should be used to shift the correct value.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 461517a87eca..6d6a2ae35481 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -33,6 +33,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
@@ -304,7 +305,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
/* Program PCIe Control 2 to disable strict ordering */
--
2.14.1

39
core/linux-espressobin/0013-PCI-aardvark-define-IRQ-related-hooks-in-pci_host_br.patch Normal file
View file

@ -0,0 +1,39 @@
From 0873f17aef726c64c5abb5ccdb35280a2239fc73 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Fri, 8 Sep 2017 11:53:48 +0200
Subject: [PATCH 13/13] PCI: aardvark: define IRQ related hooks in
pci_host_bridge
Commit 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from
pcibios_alloc_irq()") was assuming all PCI host controller drivers had
been converted to use ->map_irq(), but that wasn't the case:
pci-aardvark had not been converted. Due to this, it broke the support
for legacy PCI interrupts when using the pci-aardvark driver (used on
Marvell Armada 3720 platforms).
In order to fix this, we make sure the ->map_irq and ->swizzle_irq
fields of pci_host_bridge are properly filled in.
Fixes: 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v4.13+
---
drivers/pci/host/pci-aardvark.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 6d6a2ae35481..f682650bf037 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -999,6 +999,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pcie;
bridge->busnr = 0;
bridge->ops = &advk_pcie_ops;
+ bridge->map_irq = of_irq_parse_and_map_pci;
+ bridge->swizzle_irq = pci_common_swizzle;
ret = pci_scan_root_bus_bridge(bridge);
if (ret < 0) {
--
2.14.1

70
core/linux-espressobin/PKGBUILD
View file

@ -4,10 +4,10 @@
buildarch=8
pkgbase=linux-espressobin
_srcname=linux-4.12
_srcname=linux-4.13
_kernelname=${pkgbase#linux}
_desc="Globalscale ESPRESSOBin"
pkgver=4.12.12
pkgver=4.13.1
pkgrel=1
arch=('aarch64')
url="http://www.kernel.org/"
@ -20,29 +20,33 @@ source=("http://www.kernel.org/pub/linux/kernel/v4.x/${_srcname}.tar.xz"
'0002-ARM64-dts-marvell-armada37xx-Enable-memory-mapped-GI.patch'
'0003-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch'
'0004-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch'
'0005-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch'
'0006-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch'
'0007-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch'
'0008-fix-pci-aardvark-disable-LOS-state-by-default.patch'
'0009-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch'
'0010-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch'
'0011-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch'
'0005-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch'
'0006-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch'
'0007-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch'
'0008-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch'
'0009-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch'
'0010-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-l.patch'
'0011-PCI-aardvark-disable-LOS-state-by-default.patch'
'0012-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch'
'0013-PCI-aardvark-define-IRQ-related-hooks-in-pci_host_br.patch'
'config'
'linux.preset')
md5sums=('fc454157e2d024d401a60905d6481c6b'
'16e01eec97767ffbc0c79e4784c7c99e'
'a5fa5fb4a2c9f81893f64519419d64a0'
'8d6c8a277c5486398aa35b043e4b719d'
'cf2e62ac9c823d5bbbea550e3ec905fa'
'bf107ceb9bf8decef68f8f04c41feef1'
'14edcb80e72bfdd52780d73fa9ee620e'
'0b35c2f91eca2e6b44e856f891fb87f7'
'c6ed17ff51f5fc91a89145232758698f'
'1730d83da11980a67faac86e65011cad'
'a2b48909d123cc289c76b4675ef2d734'
'f9c043188dce7c686ebaad09d693a9eb'
'5dfa7ccc106660a5b45d36dab5352c96'
'c95edc27fef32524f2a02bc8748c635d'
md5sums=('ab1a2abc6f37b752dd2595338bec4e78'
'e2824a53597a9af0bfb2c533386842f0'
'58d3c4d2dda70d6bf5a241b8c6363c7e'
'4bce2be25214c81f1bf1e46e6a4c7d70'
'903386a648fe7c1fd54f5c0384ce0db3'
'125ada93f7b77dc1062310acae35f8a5'
'f7051fe596af5844ec9c321f985d05b3'
'd7854dc2004728203ffb21b9b07979ca'
'ec9be172d832feaf53514ac712a634a9'
'd971ded67792286617f0143f577ab0f8'
'b4d9ab7e846ef77562cfed6baa36ab4c'
'a275b90e133c3d045af1858d9f44faf8'
'88b158d5e0f650c08b37bd2dd394b8ad'
'98e275e9c5e48dd1e337bddf48934f85'
'20f31fa87e111c8ec1b0335c6d059466'
'0bca6f08768f5757e62d5ee56f1a7c6b'
'd8d30aa4a9d4c2b8d4ea53faf46ccf80')
prepare() {
@ -56,13 +60,15 @@ prepare() {
git apply ../0002-ARM64-dts-marvell-armada37xx-Enable-memory-mapped-GI.patch
git apply ../0003-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch
git apply ../0004-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch
git apply ../0005-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch
git apply ../0006-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch
git apply ../0007-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
git apply ../0008-fix-pci-aardvark-disable-LOS-state-by-default.patch
git apply ../0009-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch
git apply ../0010-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch
git apply ../0011-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch
git apply ../0005-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch
git apply ../0006-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
git apply ../0007-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch
git apply ../0008-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch
git apply ../0009-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch
git apply ../0010-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-l.patch
git apply ../0011-PCI-aardvark-disable-LOS-state-by-default.patch
git apply ../0012-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch
git apply ../0013-PCI-aardvark-define-IRQ-related-hooks-in-pci_host_br.patch
cat "${srcdir}/config" > ./.config
@ -203,10 +209,6 @@ _package-headers() {
cp arch/${KARCH}/kernel/asm-offsets.s "${pkgdir}/usr/lib/modules/${_kernver}/build/arch/${KARCH}/kernel/"
# add docbook makefile
install -D -m644 Documentation/DocBook/Makefile \
"${pkgdir}/usr/lib/modules/${_kernver}/build/Documentation/DocBook/Makefile"
# add dm headers
mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/md"
cp drivers/md/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/md"

484
core/linux-espressobin/config
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