extra/llvm to 3.9.1-2

2025-03-09 00:17:31 +00:00 · 2016-12-31 15:17:30 +00:00 · 2016-12-31 15:17:30 +00:00 · 3bad2f72b4
commit 3bad2f72b4
parent 813498d470
2 changed files with 146 additions and 1 deletions
--- a/extra/llvm/AMDGPU-Fix-an-interaction-between-WQM-and-polygon-stippling.patch
+++ b/extra/llvm/AMDGPU-Fix-an-interaction-between-WQM-and-polygon-stippling.patch
@ -0,0 +1,140 @@
+From 25e2616626caafb896517e18cd8aa724fba2b200 Mon Sep 17 00:00:00 2001
+From: Tom Stellard <thomas.stellard@amd.com>
+Date: Tue, 29 Nov 2016 03:41:28 +0000
+Subject: [PATCH] Merging r280589:
+
+------------------------------------------------------------------------
+r280589 | nhaehnle | 2016-09-03 05:26:32 -0700 (Sat, 03 Sep 2016) | 19 lines
+
+AMDGPU: Fix an interaction between WQM and polygon stippling
+
+Summary:
+This fixes a rare bug in polygon stippling with non-monolithic pixel shaders.
+
+The underlying problem is as follows: the prolog part contains the polygon
+stippling sequence, i.e. a kill. The main part then enables WQM based on the
+_reduced_ exec mask, effectively undoing most of the polygon stippling.
+
+Since we cannot know whether polygon stippling will be used, the main part
+of a non-monolithic shader must always return to exact mode to fix this
+problem.
+
+Reviewers: arsenm, tstellarAMD, mareko
+
+Subscribers: arsenm, llvm-commits, kzhuravl
+
+Differential Revision: https://reviews.llvm.org/D23131
+
+------------------------------------------------------------------------
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@288105 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Target/AMDGPU/SIInstructions.td   |  1 +
+ lib/Target/AMDGPU/SIWholeQuadMode.cpp |  7 -----
+ test/CodeGen/AMDGPU/wqm.ll            | 49 ++++++++++++++++++++++++++++++++---
+ 3 files changed, 46 insertions(+), 11 deletions(-)
+
+diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
+index 18b7d5d..dde5f2f 100644
+--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
+@@ -2029,6 +2029,7 @@ def SI_RETURN : PseudoInstSI <
+   let hasSideEffects = 1;
+   let SALU = 1;
+   let hasNoSchedulingInfo = 1;
+  let DisableWQM = 1;
+ }
+ 
+ let Uses = [EXEC], Defs = [EXEC, VCC, M0],
+diff --git a/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+index b200c15..1534d58 100644
+--- a/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+@@ -219,13 +219,6 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
+       markInstruction(MI, Flags, Worklist);
+       GlobalFlags |= Flags;
+     }
+-
+-    if (WQMOutputs && MBB.succ_empty()) {
+-      // This is a prolog shader. Make sure we go back to exact mode at the end.
+-      Blocks[&MBB].OutNeeds = StateExact;
+-      Worklist.push_back(&MBB);
+-      GlobalFlags |= StateExact;
+-    }
+   }
+ 
+   return GlobalFlags;
+diff --git a/test/CodeGen/AMDGPU/wqm.ll b/test/CodeGen/AMDGPU/wqm.ll
+index 809a7ba..41e4264 100644
+--- a/test/CodeGen/AMDGPU/wqm.ll
+++ b/test/CodeGen/AMDGPU/wqm.ll
+@@ -17,17 +17,18 @@ main_body:
+ ;CHECK-LABEL: {{^}}test2:
+ ;CHECK-NEXT: ; %main_body
+ ;CHECK-NEXT: s_wqm_b64 exec, exec
+-;CHECK: image_sample
+ ;CHECK-NOT: exec
+-;CHECK: _load_dword v0,
+-define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
+define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
+ main_body:
+   %c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+   %c.2 = bitcast <4 x float> %c.1 to <4 x i32>
+   %c.3 = extractelement <4 x i32> %c.2, i32 0
+   %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
+   %data = load float, float addrspace(1)* %gep
+-  ret float %data
+
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %data, float undef, float undef, float undef)
+
+  ret void
+ }
+ 
+ ; ... but disabled for stores (and, in this simple case, not re-enabled).
+@@ -414,6 +415,46 @@ entry:
+   ret void
+ }
+ 
+; Must return to exact at the end of a non-void returning shader,
+; otherwise the EXEC mask exported by the epilog will be wrong. This is true
+; even if the shader has no kills, because a kill could have happened in a
+; previous shader fragment.
+;
+; CHECK-LABEL: {{^}}test_nonvoid_return:
+; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
+; CHECK: s_wqm_b64 exec, exec
+;
+; CHECK: s_and_b64 exec, exec, [[LIVE]]
+; CHECK-NOT: exec
+define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind {
+  %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %tex.i = bitcast <4 x float> %tex to <4 x i32>
+  %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  ret <4 x float> %dtex
+}
+
+; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable:
+; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
+; CHECK: s_wqm_b64 exec, exec
+;
+; CHECK: s_and_b64 exec, exec, [[LIVE]]
+; CHECK-NOT: exec
+define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind {
+entry:
+  %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  %tex.i = bitcast <4 x float> %tex to <4 x i32>
+  %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+
+  %cc = icmp sgt i32 %c, 0
+  br i1 %cc, label %if, label %else
+
+if:
+  store volatile <4 x float> %dtex, <4 x float>* undef
+  unreachable
+
+else:
+  ret <4 x float> %dtex
+}
+ 
+ declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
+ declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
--- a/extra/llvm/PKGBUILD
+++ b/extra/llvm/PKGBUILD
@ -17,7 +17,7 @@ highmem=1

 pkgname=('llvm' 'llvm-libs' 'llvm-ocaml' 'lldb' 'clang' 'clang-tools-extra')
 pkgver=3.9.1
-pkgrel=1
+pkgrel=2
 _ocaml_ver=4.04.0
 arch=('i686' 'x86_64')
 url="http://llvm.org/"
@ -32,6 +32,7 @@ source=(http://llvm.org/releases/$pkgver/llvm-$pkgver.src.tar.xz{,.sig}
        http://llvm.org/releases/$pkgver/clang-tools-extra-$pkgver.src.tar.xz{,.sig}
        http://llvm.org/releases/$pkgver/compiler-rt-$pkgver.src.tar.xz{,.sig}
        http://llvm.org/releases/$pkgver/lldb-$pkgver.src.tar.xz{,.sig}
+        AMDGPU-Fix-an-interaction-between-WQM-and-polygon-stippling.patch
        msan-prevent-initialization-failure-with-newer-glibc.patch
        llvm-Config-llvm-config.h)
 sha256sums=('1fd90354b9cf19232e8f168faf2220e79be555df3aa743242700879e8fd329ee'
@ -44,6 +45,7 @@ sha256sums=('1fd90354b9cf19232e8f168faf2220e79be555df3aa743242700879e8fd329ee'
            'SKIP'
            '7e3311b2a1f80f4d3426e09f9459d079cab4d698258667e50a46dccbaaa460fc'
            'SKIP'
+            'adadc41090ab0eb33fe4449a0ea3f02b15d03f186262dd89576848a2c66d0ce6'
            '8e4f194c2283b91644a7fff43bc4e58c36b5507f2a4d90b72f275c0bd7511c20'
            '597dc5968c695bbdbb0eac9e8eb5117fcd2773bc91edf5ec103ecffffab8bc48')
 validpgpkeys=('B6C8F98282B944E3B0D5C2530FC3042E345AD05D'
@ -62,6 +64,9 @@ prepare() {

  mv "$srcdir/lldb-$pkgver.src" tools/lldb

+  # https://bugs.freedesktop.org/show_bug.cgi?id=99078
+  patch -Rp1 -i ../AMDGPU-Fix-an-interaction-between-WQM-and-polygon-stippling.patch
+
  # https://reviews.llvm.org/D24736
  patch -Np0 -d projects/compiler-rt <../msan-prevent-initialization-failure-with-newer-glibc.patch