mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2025-01-17 23:34:07 +00:00
core/linux-espressobin to 4.12.1-1
This commit is contained in:
Kevin Mihelich
parent
a55285c75e
commit
6f22ce88e9
13 changed files with 326 additions and 25 deletions
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@ -1,7 +1,7 @@
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From 88b3509f36a458b882b895ecf9eb50e922ddb2e1 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:33 +0100
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Subject: [PATCH 1/8] ARM64: dts: marvell: armada37xx: Fix timer interrupt
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Subject: [PATCH 01/12] ARM64: dts: marvell: armada37xx: Fix timer interrupt
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specifiers
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Contrary to popular belief, PPIs connected to a GICv3 to not have
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@ -1,7 +1,7 @@
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From e9fa04548195495c53ed7d13a7f6028f60b24fde Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:34 +0100
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Subject: [PATCH 2/8] ARM64: dts: marvell: armada37xx: Fix GIC maintenance
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Subject: [PATCH 02/12] ARM64: dts: marvell: armada37xx: Fix GIC maintenance
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interrupt
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The GIC-500 integrated in the Armada-37xx SoCs is compliant with
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@ -1,8 +1,8 @@
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From 4d36e9fbcde62f6312d0f3c573aa0bb9ee48c478 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:35 +0100
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Subject: [PATCH 3/8] ARM64: dts: marvell: armada37xx: Enable memory-mapped GIC
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CPU interface
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Subject: [PATCH 03/12] ARM64: dts: marvell: armada37xx: Enable memory-mapped
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GIC CPU interface
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The Cortex-A53s that power the Armada-37xx SoCs are equipped with
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a GIC CPU interface that gets enabled when coupled with a GICv3
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@ -1,7 +1,7 @@
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From 55f2b7a0efc914173368405d1399f31a4ca76566 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:36 +0100
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Subject: [PATCH 4/8] ARM64: dts: marvell: armada37xx: Wire PMUv3
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Subject: [PATCH 04/12] ARM64: dts: marvell: armada37xx: Wire PMUv3
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The Cortex-A53s that power the Armada-37xx SoCs are equipped with
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a PMUv3, just like most ARMv8 cores.
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@ -1,7 +1,7 @@
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From 8024835ce8bd95e953658bd3c83eadc3eaf4dec6 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:37 +0100
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Subject: [PATCH 5/8] ARM64: dts: marvell: armada37xx: Enable USB2 on
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Subject: [PATCH 05/12] ARM64: dts: marvell: armada37xx: Enable USB2 on
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espressobin
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The Espressobin SBC has a USB2 interface available on J8. Let's
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@ -1,7 +1,7 @@
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From 85348a90e9b2bc41164e51184bad445bdc4b777d Mon Sep 17 00:00:00 2001
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From: Konstantin Porotchkin <kostap@marvell.com>
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Date: Tue, 23 May 2017 16:11:40 +0300
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Subject: [PATCH 6/8] arm64: dts: marvell: Enable second SDHCI controller in
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Subject: [PATCH 06/12] arm64: dts: marvell: Enable second SDHCI controller in
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Armada 37xx
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The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second
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@ -1,8 +1,8 @@
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From 191c274b6024a3b3055200e909d6ad68872fa976 Mon Sep 17 00:00:00 2001
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From: Sean Nyekjaer <sean@nyekjaer.dk>
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Date: Sun, 25 Jun 2017 21:20:05 +0200
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Subject: [PATCH 7/8] arm64: dts: marvell: Add microsd card definition for the
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ESPRESSObin
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Subject: [PATCH 07/12] arm64: dts: marvell: Add microsd card definition for
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the ESPRESSObin
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This defines and enables the microsd card on the
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Marvell ESPRESSObin board.
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@ -1,7 +1,7 @@
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From 10cb26081c87817aa037eb4151e42237d000da68 Mon Sep 17 00:00:00 2001
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From d07fa043fcdf4b15c70e90a7701ad8dc0a9a1158 Mon Sep 17 00:00:00 2001
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From: Kevin Mihelich <kevin@archlinuxarm.org>
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Date: Tue, 4 Jul 2017 19:25:28 -0600
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Subject: [PATCH 8/8] arm64: marvell: armada37xx: Add eth0 alias
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Subject: [PATCH 08/12] arm64: dts: marvell: armada37xx: Add eth0 alias
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Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
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---
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@ -0,0 +1,35 @@
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From 3c4ad04a042ca8022cbb8511742ea297536b78fd Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Wed, 29 Mar 2017 15:17:03 +0800
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Subject: [PATCH 09/12] fix: pci: aardvark: disable LOS state by default
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Some PCIe devices do not support LOS, there will be time out issue
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if the RC forces the LOS state.
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This patch disables the LOS state by default.
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Change-Id: I88a6a5cf58ea5f2df234c99050ce041987cdabc6
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/38119
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 37d0bcd31f8a..072bc70e900c 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_pcie_wait_for_link(pcie);
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- reg = PCIE_CORE_LINK_L0S_ENTRY |
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- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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--
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2.13.2
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@ -0,0 +1,104 @@
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From 9fe10853807dd1bd370ca2bf8baf76c4cfe242a9 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Mon, 27 Mar 2017 18:28:25 +0800
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Subject: [PATCH 10/12] fix: pci: aardvark: use isr1 interrupt in legacy irq
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mode
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The Aardvark has two interrupts sets, first set is bit[23:16] of
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PCIe ISR 0 register(RD0074840h), second set is bit[11:8] of PCIe
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ISR 1 register(RD0074848h). Only one set should be used, while
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another set should be masked.
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The second set is more advanced, the Legacy INT_X status bit is
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asserted once Assert_INTX message is received, and de-asserted after
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Deassert_INTX message is received, which provides alternate way
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besides of the assert/deassert interrupt pairs in PCIe ISR 0 register.
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Change-Id: Idef2eb474a094754195a031ad580caa8a88f046d
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/38024
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 29 ++++++++++++++++++-----------
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1 file changed, 18 insertions(+), 11 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 072bc70e900c..10154dcf219b 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -103,7 +103,8 @@
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#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
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#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
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#define PCIE_ISR1_FLUSH BIT(5)
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-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
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+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
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+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
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#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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@@ -612,9 +613,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static void advk_pcie_irq_unmask(struct irq_data *d)
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@@ -623,9 +624,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static int advk_pcie_irq_map(struct irq_domain *h,
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@@ -769,14 +770,20 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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static void advk_pcie_handle_int(struct advk_pcie *pcie)
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{
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u32 val, mask, status;
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+ u32 val2, mask2, status2;
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int i, virq;
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val = advk_readl(pcie, PCIE_ISR0_REG);
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mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
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- if (!status) {
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+ val2 = advk_readl(pcie, PCIE_ISR1_REG);
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+ mask2 = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ status2 = val2 & ((~mask2) & PCIE_ISR1_ALL_MASK);
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+
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+ if (!status && !status2) {
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advk_writel(pcie, val, PCIE_ISR0_REG);
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+ advk_writel(pcie, val2, PCIE_ISR1_REG);
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return;
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}
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@@ -786,11 +793,11 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
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/* Process legacy interrupts */
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for (i = 0; i < LEGACY_IRQ_NUM; i++) {
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- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
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+ if (!(status2 & PCIE_ISR1_INTX_ASSERT(i)))
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continue;
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- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
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- PCIE_ISR0_REG);
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+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
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+ PCIE_ISR1_REG);
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virq = irq_find_mapping(pcie->irq_domain, i);
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generic_handle_irq(virq);
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--
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2.13.2
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@ -0,0 +1,105 @@
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From 4455b4e78d3696f842d7b27ff6e4c1c15adffbf3 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
|
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Date: Fri, 24 Mar 2017 20:52:30 +0800
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Subject: [PATCH 11/12] pci: aardvard: set host and device to the same MAX
|
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payload size
|
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|
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Since the Aardvard does not implement PCIe root bus, the Linux PCIe
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framework will not align the MAX payload size between host and device
|
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for it.
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This patch sets host and device to the same MAX payload size in Aardvard
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PCIe driver.
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Change-Id: I3979397b3af98911c067f7ad384922aa3f05497f
|
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Signed-off-by: Victor Gu <xigu@marvell.com>
|
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Reviewed-on: http://vgitil04.il.marvell.com:8080/37927
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 56 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 56 insertions(+)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 10154dcf219b..0407c8cb89fb 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -32,6 +32,7 @@
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -886,6 +887,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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return err;
|
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}
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|
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
|
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
|
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+
|
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+ return 0;
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+}
|
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+
|
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
|
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+{
|
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+ int mps;
|
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+
|
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+ if (!dev)
|
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+ return 0;
|
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+
|
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+ if (!pci_is_pcie(dev))
|
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+ return 0;
|
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+
|
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
|
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+ pcie_set_mps(dev, mps);
|
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+
|
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+ return 0;
|
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+}
|
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+
|
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
|
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+{
|
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
|
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+ u32 reg;
|
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+
|
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
|
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+
|
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+ /* Configure RC MAX payload size */
|
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
|
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
|
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
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+
|
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+ /* Configure device MAX payload size */
|
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
|
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
|
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+}
|
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+
|
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static int advk_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
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@@ -948,6 +1001,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
|
||||
list_for_each_entry(child, &bus->children, node)
|
||||
pcie_bus_configure_settings(child);
|
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|
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+ /* Configure the MAX pay load size */
|
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+ advk_pcie_configure_mps(bus, pcie);
|
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+
|
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pci_bus_add_devices(bus);
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return 0;
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}
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--
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2.13.2
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|
|
@ -0,0 +1,44 @@
|
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From ebd87e2955e49f5197aff99702606866e8729a1d Mon Sep 17 00:00:00 2001
|
||||
From: Victor Gu <xigu@marvell.com>
|
||||
Date: Fri, 24 Mar 2017 20:41:55 +0800
|
||||
Subject: [PATCH 12/12] fix: pcie: aardvark: correct the default MAX payload
|
||||
size
|
||||
|
||||
The previous PCIe MAX payload field is set to 7 which is undefined
|
||||
value according to functional specification.
|
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The default PICe host controller MAX payload size should be
|
||||
set to 512 bytes according to specification.
|
||||
|
||||
Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9
|
||||
Signed-off-by: Victor Gu <xigu@marvell.com>
|
||||
Reviewed-on: http://vgitil04.il.marvell.com:8080/37926
|
||||
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
|
||||
Reviewed-by: Evan Wang <xswang@marvell.com>
|
||||
---
|
||||
drivers/pci/host/pci-aardvark.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
|
||||
index 0407c8cb89fb..cac1558b8d3b 100644
|
||||
--- a/drivers/pci/host/pci-aardvark.c
|
||||
+++ b/drivers/pci/host/pci-aardvark.c
|
||||
@@ -30,6 +30,7 @@
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
|
||||
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
||||
#define PCIE_CORE_MPS_UNIT_BYTE 128
|
||||
@@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
||||
|
||||
/* Set PCIe Device Control and Status 1 PF0 register */
|
||||
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
|
||||
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||||
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||||
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
||||
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
|
||||
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
||||
--
|
||||
2.13.2
|
||||
|
||||
|
|
@ -7,15 +7,15 @@ pkgbase=linux-espressobin
|
|||
_srcname=linux-4.12
|
||||
_kernelname=${pkgbase#linux}
|
||||
_desc="Globalscale ESPRESSOBin"
|
||||
pkgver=4.12.0
|
||||
pkgrel=2
|
||||
pkgver=4.12.1
|
||||
pkgrel=1
|
||||
arch=('aarch64')
|
||||
url="http://www.kernel.org/"
|
||||
license=('GPL2')
|
||||
makedepends=('xmlto' 'docbook-xsl' 'kmod' 'inetutils' 'bc' 'git')
|
||||
options=('!strip')
|
||||
source=("http://www.kernel.org/pub/linux/kernel/v4.x/${_srcname}.tar.xz"
|
||||
#"http://www.kernel.org/pub/linux/kernel/v4.x/patch-${pkgver}.xz"
|
||||
"http://www.kernel.org/pub/linux/kernel/v4.x/patch-${pkgver}.xz"
|
||||
'0001-ARM64-dts-marvell-armada37xx-Fix-timer-interrupt-spe.patch'
|
||||
'0002-ARM64-dts-marvell-armada37xx-Fix-GIC-maintenance-int.patch'
|
||||
'0003-ARM64-dts-marvell-armada37xx-Enable-memory-mapped-GI.patch'
|
||||
|
|
@ -23,18 +23,27 @@ source=("http://www.kernel.org/pub/linux/kernel/v4.x/${_srcname}.tar.xz"
|
|||
'0005-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch'
|
||||
'0006-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch'
|
||||
'0007-arm64-dts-marvell-Add-microsd-card-definition-for-th.patch'
|
||||
'0008-arm64-marvell-armada37xx-Add-eth0-alias.patch'
|
||||
'0008-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch'
|
||||
'0009-fix-pci-aardvark-disable-LOS-state-by-default.patch'
|
||||
'0010-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch'
|
||||
'0011-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch'
|
||||
'0012-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch'
|
||||
'config'
|
||||
'linux.preset')
|
||||
md5sums=('fc454157e2d024d401a60905d6481c6b'
|
||||
'7b2bb6f5cfd91f1e0b98693b4c2be795'
|
||||
'ad38796bd014a3a2f371cb705629391a'
|
||||
'71e1896b02c2c36372b23c41f74bf3cc'
|
||||
'3537c6f3729f2cb7e528eec15bec849b'
|
||||
'b007cd30ca2261e9f7f7a14fadb5e999'
|
||||
'19b64449ee336a42255411a0025fd5d1'
|
||||
'a14447adca3b29fb28a30de451e39488'
|
||||
'80a477685ba907e83b3b0c10a36bc5f0'
|
||||
'fab3dcd3b5a99d959bde7cde2e5cedb8'
|
||||
'b2a7116c7b3908fe1603c796f83fb56c'
|
||||
'2f43eba428830c7a7bf4a520f7077535'
|
||||
'9d0f72905f1f1320f52d6f65dd668d0b'
|
||||
'b50d466feecea898a74c3867319fb90e'
|
||||
'd79d1f0f7d9a7c35137229e70a30c0d7'
|
||||
'3e60cf410ae3bb37c01d2eb04501d174'
|
||||
'57dace766b81b0680ac43f37765d7018'
|
||||
'd659197cb859a9976123b73dc796db9f'
|
||||
'b24d333e00622a48ea68058b6157d276'
|
||||
'4f340086bdc4fab53ac271f821a62176'
|
||||
'f3f6c6fe3645783486aac43e4d7c00ec'
|
||||
'd540534a40050f4dfea2bd658b89e038'
|
||||
'aafe13461c5fed44285f685025ec610f'
|
||||
'd8d30aa4a9d4c2b8d4ea53faf46ccf80')
|
||||
|
||||
|
|
@ -42,7 +51,7 @@ prepare() {
|
|||
cd "${srcdir}/${_srcname}"
|
||||
|
||||
# add upstream patch
|
||||
#git apply --whitespace=nowarn ../patch-${pkgver}
|
||||
git apply --whitespace=nowarn ../patch-${pkgver}
|
||||
|
||||
# ALARM patches
|
||||
git apply ../0001-ARM64-dts-marvell-armada37xx-Fix-timer-interrupt-spe.patch
|
||||
|
|
@ -52,7 +61,11 @@ prepare() {
|
|||
git apply ../0005-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch
|
||||
git apply ../0006-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch
|
||||
git apply ../0007-arm64-dts-marvell-Add-microsd-card-definition-for-th.patch
|
||||
git apply ../0008-arm64-marvell-armada37xx-Add-eth0-alias.patch
|
||||
git apply ../0008-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
|
||||
git apply ../0009-fix-pci-aardvark-disable-LOS-state-by-default.patch
|
||||
git apply ../0010-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch
|
||||
git apply ../0011-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch
|
||||
git apply ../0012-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch
|
||||
|
||||
cat "${srcdir}/config" > ./.config
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue