mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2024-11-18 22:54:00 +00:00
core/linux-armv7-rc to 4.18.rc7-1
This commit is contained in:
parent
307b0670f7
commit
771632dbd0
2 changed files with 9 additions and 10 deletions
|
@ -4,7 +4,7 @@
|
|||
buildarch=4
|
||||
|
||||
_rcver=4.18
|
||||
_rcrel=6
|
||||
_rcrel=7
|
||||
_rcnrel=armv7-x2
|
||||
|
||||
pkgbase=linux-armv7-rc
|
||||
|
@ -40,8 +40,8 @@ source=("https://git.kernel.org/torvalds/t/${_srcname}.tar.gz"
|
|||
'kernel_data_key.vbprivk'
|
||||
'linux.preset'
|
||||
'99-linux.hook')
|
||||
md5sums=('d3bdc7d12034b03e4487ba07e5edb562'
|
||||
'1f67dc8fc8b90c69f86d5289d908cec2'
|
||||
md5sums=('c71dbb50b1d2006379d0167a132f9d2f'
|
||||
'd66c1f8dcf21ed3935eeb59d50304167'
|
||||
'fb218c1825366e722be83dd705d02822'
|
||||
'bfeb8670a65fc8c14a7076ec623e9898'
|
||||
'1651316b545214bb346af28f3925ccd0'
|
||||
|
@ -56,7 +56,7 @@ md5sums=('d3bdc7d12034b03e4487ba07e5edb562'
|
|||
'eb51f5bbcf5b38956a0ba931d7898f07'
|
||||
'cd9f373ec6e45e99610c9892a8e38100'
|
||||
'8b896e19eac2b3bff797c48e737a166b'
|
||||
'6bb2378dbfc0aa0514d200024dffac00'
|
||||
'0cd85c86fe652667791d282f8af22096'
|
||||
'4f2379ed84258050edb858ee8d281678'
|
||||
'61c5ff73c136ed07a7aadbf58db3d96a'
|
||||
'584777ae88bce2c5659960151b64c7d8'
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 4.18.0-rc6-1 Kernel Configuration
|
||||
# Linux/arm 4.18.0-rc7-1 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
@ -6367,7 +6367,6 @@ CONFIG_USB_CHIPIDEA_OF=y
|
|||
CONFIG_USB_CHIPIDEA_PCI=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
# CONFIG_USB_CHIPIDEA_ULPI is not set
|
||||
CONFIG_USB_ISP1760=y
|
||||
CONFIG_USB_ISP1760_HCD=y
|
||||
CONFIG_USB_ISP1761_UDC=y
|
||||
|
@ -7970,12 +7969,12 @@ CONFIG_FPGA_MGR_SOCFPGA=m
|
|||
CONFIG_FPGA_MGR_SOCFPGA_A10=m
|
||||
CONFIG_ALTERA_PR_IP_CORE=m
|
||||
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
|
||||
# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
|
||||
# CONFIG_FPGA_MGR_ALTERA_CVP is not set
|
||||
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
|
||||
CONFIG_FPGA_MGR_ALTERA_CVP=m
|
||||
CONFIG_FPGA_MGR_ZYNQ_FPGA=m
|
||||
CONFIG_FPGA_MGR_XILINX_SPI=m
|
||||
CONFIG_FPGA_MGR_ICE40_SPI=m
|
||||
# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
|
||||
CONFIG_FPGA_MGR_MACHXO2_SPI=m
|
||||
CONFIG_FPGA_BRIDGE=m
|
||||
CONFIG_SOCFPGA_FPGA_BRIDGE=m
|
||||
CONFIG_ALTERA_FREEZE_BRIDGE=m
|
||||
|
@ -8278,7 +8277,7 @@ CONFIG_CIFS_FSCACHE=y
|
|||
# CONFIG_9P_FS is not set
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
|
|
Loading…
Reference in a new issue