core/gcc: update

core/gcc/0001-ARMv5-disable-LDRD-STRD.patch

@@ -1,4 +1,4 @@
-From 5268e8d175437f0bc18487d78d5f083b45ff17f3 Mon Sep 17 00:00:00 2001
+From 09eb4fbd5d0e51490da810a1ee0c6ed73c1c8688 Mon Sep 17 00:00:00 2001
 From: Kevin Mihelich <kevin@archlinuxarm.org>
 Date: Wed, 7 Jan 2015 18:43:57 -0700
 Subject: [PATCH] ARMv5: disable LDRD/STRD
@@ -8,18 +8,18 @@ Subject: [PATCH] ARMv5: disable LDRD/STRD
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
-index ad123dd..87697f7 100644
+index 4866e1e4b7d..a4bd43a364f 100644
 --- a/gcc/config/arm/arm.h
 +++ b/gcc/config/arm/arm.h
-@@ -166,7 +166,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+@@ -167,7 +167,7 @@ emission of floating point pcs attributes.  */
  /* Thumb-1 only.  */
  #define TARGET_THUMB1_ONLY		(TARGET_THUMB1 && !arm_arch_notm)
  
--#define TARGET_LDRD			(arm_arch5e && ARM_DOUBLEWORD_ALIGN \
+-#define TARGET_LDRD			(arm_arch5te && ARM_DOUBLEWORD_ALIGN \
 +#define TARGET_LDRD			(arm_arch6 && ARM_DOUBLEWORD_ALIGN \
                                           && !TARGET_THUMB1)
  
  #define TARGET_CRC32			(arm_arch_crc)
 -- 
-2.7.2
+2.22.0
 

core/gcc/PKGBUILD

@@ -48,7 +48,7 @@ sha256sums=('ea6ef08f121239da5695f76c9b33637a118dcf63e24164422231917fa61fb206'
             'c86372c207d174c0918d4aedf1cb79f7fc093649eb1ad8d9450dccc46849d308'
             '3862757491160700ac2fb723096f6f636f30320cccc6efd9537149ed348b57d1'
             '9699d7105375754f0dcf6abff87d09b270565bfc6578a13641770f3fc62d678a'
-            '31e24baa9eee826d7d77dbcf8f1a6a44c92f771e52d21677acb8d76fac7ae204')
+            'ac6663528a1cbea30ed9627ef41ef13f25b3cd49c31e22b45b04aa911e6f562f')
 
 _svnrev=264010
 _svnurl=svn://gcc.gnu.org/svn/gcc/branches/gcc-${_majorver}-branch