From 8ab379fa9f63f35b41b30ac6d5a35ec97f9ff8f8 Mon Sep 17 00:00:00 2001 From: Kevin Mihelich Date: Mon, 12 Oct 2015 00:25:36 +0000 Subject: [PATCH] added core/linux-armv8-rc --- ...d-xgbe-a0-Add-support-for-XGBE-on-A0.patch | 10391 ++++++++++++++++ ...hy-a0-Add-support-for-XGBE-PHY-on-A0.patch | 1870 +++ .../0003-arm64-acpi-drop-expert-patch.patch | 25 + ...atform-driver-use-64-bit-or-32-bit-D.patch | 44 + core/linux-armv8-rc/PKGBUILD | 266 + core/linux-armv8-rc/config | 6038 +++++++++ core/linux-armv8-rc/linux-armv8-rc.install | 31 + core/linux-armv8-rc/linux.preset | 14 + 8 files changed, 18679 insertions(+) create mode 100644 core/linux-armv8-rc/0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch create mode 100644 core/linux-armv8-rc/0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch create mode 100644 core/linux-armv8-rc/0003-arm64-acpi-drop-expert-patch.patch create mode 100644 core/linux-armv8-rc/0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch create mode 100644 core/linux-armv8-rc/PKGBUILD create mode 100644 core/linux-armv8-rc/config create mode 100644 core/linux-armv8-rc/linux-armv8-rc.install create mode 100644 core/linux-armv8-rc/linux.preset diff --git a/core/linux-armv8-rc/0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch b/core/linux-armv8-rc/0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch new file mode 100644 index 000000000..012331fd3 --- /dev/null +++ b/core/linux-armv8-rc/0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch @@ -0,0 +1,10391 @@ +From 6c25652c1f1b59476d6a548a1d1d811f49615b52 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky +Date: Thu, 28 May 2015 16:38:57 -0400 +Subject: [PATCH 1/4] amd-xgbe-a0: Add support for XGBE on A0 + +Add XGBE driver support for A0 hardware. + +Signed-off-by: Tom Lendacky +[fixup timespec -> timespec64] +[use device_dma_is_coherent] +Signed-off-by: Mark Salter +--- + drivers/net/ethernet/amd/Makefile | 1 + + drivers/net/ethernet/amd/xgbe-a0/Makefile | 8 + + drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h | 1142 +++++++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c | 269 +++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c | 373 +++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c | 636 +++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c | 2930 +++++++++++++++++++++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c | 2218 +++++++++++++++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c | 616 +++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c | 618 +++++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c | 312 +++ + drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c | 278 +++ + drivers/net/ethernet/amd/xgbe-a0/xgbe.h | 868 +++++++ + 13 files changed, 10269 insertions(+) + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/Makefile + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c + create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe.h + +diff --git a/drivers/net/ethernet/amd/Makefile b/drivers/net/ethernet/amd/Makefile +index a38a2dc..bf0cf2f 100644 +--- a/drivers/net/ethernet/amd/Makefile ++++ b/drivers/net/ethernet/amd/Makefile +@@ -18,3 +18,4 @@ obj-$(CONFIG_PCNET32) += pcnet32.o + obj-$(CONFIG_SUN3LANCE) += sun3lance.o + obj-$(CONFIG_SUNLANCE) += sunlance.o + obj-$(CONFIG_AMD_XGBE) += xgbe/ ++obj-$(CONFIG_AMD_XGBE) += xgbe-a0/ +diff --git a/drivers/net/ethernet/amd/xgbe-a0/Makefile b/drivers/net/ethernet/amd/xgbe-a0/Makefile +new file mode 100644 +index 0000000..561116f +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/Makefile +@@ -0,0 +1,8 @@ ++obj-$(CONFIG_AMD_XGBE) += amd-xgbe-a0.o ++ ++amd-xgbe-a0-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \ ++ xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \ ++ xgbe-ptp.o ++ ++amd-xgbe-a0-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o ++amd-xgbe-a0-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h +new file mode 100644 +index 0000000..75b08c6 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h +@@ -0,0 +1,1142 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef __XGBE_COMMON_H__ ++#define __XGBE_COMMON_H__ ++ ++/* DMA register offsets */ ++#define DMA_MR 0x3000 ++#define DMA_SBMR 0x3004 ++#define DMA_ISR 0x3008 ++#define DMA_AXIARCR 0x3010 ++#define DMA_AXIAWCR 0x3018 ++#define DMA_DSR0 0x3020 ++#define DMA_DSR1 0x3024 ++ ++/* DMA register entry bit positions and sizes */ ++#define DMA_AXIARCR_DRC_INDEX 0 ++#define DMA_AXIARCR_DRC_WIDTH 4 ++#define DMA_AXIARCR_DRD_INDEX 4 ++#define DMA_AXIARCR_DRD_WIDTH 2 ++#define DMA_AXIARCR_TEC_INDEX 8 ++#define DMA_AXIARCR_TEC_WIDTH 4 ++#define DMA_AXIARCR_TED_INDEX 12 ++#define DMA_AXIARCR_TED_WIDTH 2 ++#define DMA_AXIARCR_THC_INDEX 16 ++#define DMA_AXIARCR_THC_WIDTH 4 ++#define DMA_AXIARCR_THD_INDEX 20 ++#define DMA_AXIARCR_THD_WIDTH 2 ++#define DMA_AXIAWCR_DWC_INDEX 0 ++#define DMA_AXIAWCR_DWC_WIDTH 4 ++#define DMA_AXIAWCR_DWD_INDEX 4 ++#define DMA_AXIAWCR_DWD_WIDTH 2 ++#define DMA_AXIAWCR_RPC_INDEX 8 ++#define DMA_AXIAWCR_RPC_WIDTH 4 ++#define DMA_AXIAWCR_RPD_INDEX 12 ++#define DMA_AXIAWCR_RPD_WIDTH 2 ++#define DMA_AXIAWCR_RHC_INDEX 16 ++#define DMA_AXIAWCR_RHC_WIDTH 4 ++#define DMA_AXIAWCR_RHD_INDEX 20 ++#define DMA_AXIAWCR_RHD_WIDTH 2 ++#define DMA_AXIAWCR_TDC_INDEX 24 ++#define DMA_AXIAWCR_TDC_WIDTH 4 ++#define DMA_AXIAWCR_TDD_INDEX 28 ++#define DMA_AXIAWCR_TDD_WIDTH 2 ++#define DMA_ISR_MACIS_INDEX 17 ++#define DMA_ISR_MACIS_WIDTH 1 ++#define DMA_ISR_MTLIS_INDEX 16 ++#define DMA_ISR_MTLIS_WIDTH 1 ++#define DMA_MR_SWR_INDEX 0 ++#define DMA_MR_SWR_WIDTH 1 ++#define DMA_SBMR_EAME_INDEX 11 ++#define DMA_SBMR_EAME_WIDTH 1 ++#define DMA_SBMR_BLEN_256_INDEX 7 ++#define DMA_SBMR_BLEN_256_WIDTH 1 ++#define DMA_SBMR_UNDEF_INDEX 0 ++#define DMA_SBMR_UNDEF_WIDTH 1 ++ ++/* DMA register values */ ++#define DMA_DSR_RPS_WIDTH 4 ++#define DMA_DSR_TPS_WIDTH 4 ++#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) ++#define DMA_DSR0_RPS_START 8 ++#define DMA_DSR0_TPS_START 12 ++#define DMA_DSRX_FIRST_QUEUE 3 ++#define DMA_DSRX_INC 4 ++#define DMA_DSRX_QPR 4 ++#define DMA_DSRX_RPS_START 0 ++#define DMA_DSRX_TPS_START 4 ++#define DMA_TPS_STOPPED 0x00 ++#define DMA_TPS_SUSPENDED 0x06 ++ ++/* DMA channel register offsets ++ * Multiple channels can be active. The first channel has registers ++ * that begin at 0x3100. Each subsequent channel has registers that ++ * are accessed using an offset of 0x80 from the previous channel. ++ */ ++#define DMA_CH_BASE 0x3100 ++#define DMA_CH_INC 0x80 ++ ++#define DMA_CH_CR 0x00 ++#define DMA_CH_TCR 0x04 ++#define DMA_CH_RCR 0x08 ++#define DMA_CH_TDLR_HI 0x10 ++#define DMA_CH_TDLR_LO 0x14 ++#define DMA_CH_RDLR_HI 0x18 ++#define DMA_CH_RDLR_LO 0x1c ++#define DMA_CH_TDTR_LO 0x24 ++#define DMA_CH_RDTR_LO 0x2c ++#define DMA_CH_TDRLR 0x30 ++#define DMA_CH_RDRLR 0x34 ++#define DMA_CH_IER 0x38 ++#define DMA_CH_RIWT 0x3c ++#define DMA_CH_CATDR_LO 0x44 ++#define DMA_CH_CARDR_LO 0x4c ++#define DMA_CH_CATBR_HI 0x50 ++#define DMA_CH_CATBR_LO 0x54 ++#define DMA_CH_CARBR_HI 0x58 ++#define DMA_CH_CARBR_LO 0x5c ++#define DMA_CH_SR 0x60 ++ ++/* DMA channel register entry bit positions and sizes */ ++#define DMA_CH_CR_PBLX8_INDEX 16 ++#define DMA_CH_CR_PBLX8_WIDTH 1 ++#define DMA_CH_CR_SPH_INDEX 24 ++#define DMA_CH_CR_SPH_WIDTH 1 ++#define DMA_CH_IER_AIE_INDEX 15 ++#define DMA_CH_IER_AIE_WIDTH 1 ++#define DMA_CH_IER_FBEE_INDEX 12 ++#define DMA_CH_IER_FBEE_WIDTH 1 ++#define DMA_CH_IER_NIE_INDEX 16 ++#define DMA_CH_IER_NIE_WIDTH 1 ++#define DMA_CH_IER_RBUE_INDEX 7 ++#define DMA_CH_IER_RBUE_WIDTH 1 ++#define DMA_CH_IER_RIE_INDEX 6 ++#define DMA_CH_IER_RIE_WIDTH 1 ++#define DMA_CH_IER_RSE_INDEX 8 ++#define DMA_CH_IER_RSE_WIDTH 1 ++#define DMA_CH_IER_TBUE_INDEX 2 ++#define DMA_CH_IER_TBUE_WIDTH 1 ++#define DMA_CH_IER_TIE_INDEX 0 ++#define DMA_CH_IER_TIE_WIDTH 1 ++#define DMA_CH_IER_TXSE_INDEX 1 ++#define DMA_CH_IER_TXSE_WIDTH 1 ++#define DMA_CH_RCR_PBL_INDEX 16 ++#define DMA_CH_RCR_PBL_WIDTH 6 ++#define DMA_CH_RCR_RBSZ_INDEX 1 ++#define DMA_CH_RCR_RBSZ_WIDTH 14 ++#define DMA_CH_RCR_SR_INDEX 0 ++#define DMA_CH_RCR_SR_WIDTH 1 ++#define DMA_CH_RIWT_RWT_INDEX 0 ++#define DMA_CH_RIWT_RWT_WIDTH 8 ++#define DMA_CH_SR_FBE_INDEX 12 ++#define DMA_CH_SR_FBE_WIDTH 1 ++#define DMA_CH_SR_RBU_INDEX 7 ++#define DMA_CH_SR_RBU_WIDTH 1 ++#define DMA_CH_SR_RI_INDEX 6 ++#define DMA_CH_SR_RI_WIDTH 1 ++#define DMA_CH_SR_RPS_INDEX 8 ++#define DMA_CH_SR_RPS_WIDTH 1 ++#define DMA_CH_SR_TBU_INDEX 2 ++#define DMA_CH_SR_TBU_WIDTH 1 ++#define DMA_CH_SR_TI_INDEX 0 ++#define DMA_CH_SR_TI_WIDTH 1 ++#define DMA_CH_SR_TPS_INDEX 1 ++#define DMA_CH_SR_TPS_WIDTH 1 ++#define DMA_CH_TCR_OSP_INDEX 4 ++#define DMA_CH_TCR_OSP_WIDTH 1 ++#define DMA_CH_TCR_PBL_INDEX 16 ++#define DMA_CH_TCR_PBL_WIDTH 6 ++#define DMA_CH_TCR_ST_INDEX 0 ++#define DMA_CH_TCR_ST_WIDTH 1 ++#define DMA_CH_TCR_TSE_INDEX 12 ++#define DMA_CH_TCR_TSE_WIDTH 1 ++ ++/* DMA channel register values */ ++#define DMA_OSP_DISABLE 0x00 ++#define DMA_OSP_ENABLE 0x01 ++#define DMA_PBL_1 1 ++#define DMA_PBL_2 2 ++#define DMA_PBL_4 4 ++#define DMA_PBL_8 8 ++#define DMA_PBL_16 16 ++#define DMA_PBL_32 32 ++#define DMA_PBL_64 64 /* 8 x 8 */ ++#define DMA_PBL_128 128 /* 8 x 16 */ ++#define DMA_PBL_256 256 /* 8 x 32 */ ++#define DMA_PBL_X8_DISABLE 0x00 ++#define DMA_PBL_X8_ENABLE 0x01 ++ ++/* MAC register offsets */ ++#define MAC_TCR 0x0000 ++#define MAC_RCR 0x0004 ++#define MAC_PFR 0x0008 ++#define MAC_WTR 0x000c ++#define MAC_HTR0 0x0010 ++#define MAC_VLANTR 0x0050 ++#define MAC_VLANHTR 0x0058 ++#define MAC_VLANIR 0x0060 ++#define MAC_IVLANIR 0x0064 ++#define MAC_RETMR 0x006c ++#define MAC_Q0TFCR 0x0070 ++#define MAC_RFCR 0x0090 ++#define MAC_RQC0R 0x00a0 ++#define MAC_RQC1R 0x00a4 ++#define MAC_RQC2R 0x00a8 ++#define MAC_RQC3R 0x00ac ++#define MAC_ISR 0x00b0 ++#define MAC_IER 0x00b4 ++#define MAC_RTSR 0x00b8 ++#define MAC_PMTCSR 0x00c0 ++#define MAC_RWKPFR 0x00c4 ++#define MAC_LPICSR 0x00d0 ++#define MAC_LPITCR 0x00d4 ++#define MAC_VR 0x0110 ++#define MAC_DR 0x0114 ++#define MAC_HWF0R 0x011c ++#define MAC_HWF1R 0x0120 ++#define MAC_HWF2R 0x0124 ++#define MAC_GPIOCR 0x0278 ++#define MAC_GPIOSR 0x027c ++#define MAC_MACA0HR 0x0300 ++#define MAC_MACA0LR 0x0304 ++#define MAC_MACA1HR 0x0308 ++#define MAC_MACA1LR 0x030c ++#define MAC_RSSCR 0x0c80 ++#define MAC_RSSAR 0x0c88 ++#define MAC_RSSDR 0x0c8c ++#define MAC_TSCR 0x0d00 ++#define MAC_SSIR 0x0d04 ++#define MAC_STSR 0x0d08 ++#define MAC_STNR 0x0d0c ++#define MAC_STSUR 0x0d10 ++#define MAC_STNUR 0x0d14 ++#define MAC_TSAR 0x0d18 ++#define MAC_TSSR 0x0d20 ++#define MAC_TXSNR 0x0d30 ++#define MAC_TXSSR 0x0d34 ++ ++#define MAC_QTFCR_INC 4 ++#define MAC_MACA_INC 4 ++#define MAC_HTR_INC 4 ++ ++#define MAC_RQC2_INC 4 ++#define MAC_RQC2_Q_PER_REG 4 ++ ++/* MAC register entry bit positions and sizes */ ++#define MAC_HWF0R_ADDMACADRSEL_INDEX 18 ++#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 ++#define MAC_HWF0R_ARPOFFSEL_INDEX 9 ++#define MAC_HWF0R_ARPOFFSEL_WIDTH 1 ++#define MAC_HWF0R_EEESEL_INDEX 13 ++#define MAC_HWF0R_EEESEL_WIDTH 1 ++#define MAC_HWF0R_GMIISEL_INDEX 1 ++#define MAC_HWF0R_GMIISEL_WIDTH 1 ++#define MAC_HWF0R_MGKSEL_INDEX 7 ++#define MAC_HWF0R_MGKSEL_WIDTH 1 ++#define MAC_HWF0R_MMCSEL_INDEX 8 ++#define MAC_HWF0R_MMCSEL_WIDTH 1 ++#define MAC_HWF0R_RWKSEL_INDEX 6 ++#define MAC_HWF0R_RWKSEL_WIDTH 1 ++#define MAC_HWF0R_RXCOESEL_INDEX 16 ++#define MAC_HWF0R_RXCOESEL_WIDTH 1 ++#define MAC_HWF0R_SAVLANINS_INDEX 27 ++#define MAC_HWF0R_SAVLANINS_WIDTH 1 ++#define MAC_HWF0R_SMASEL_INDEX 5 ++#define MAC_HWF0R_SMASEL_WIDTH 1 ++#define MAC_HWF0R_TSSEL_INDEX 12 ++#define MAC_HWF0R_TSSEL_WIDTH 1 ++#define MAC_HWF0R_TSSTSSEL_INDEX 25 ++#define MAC_HWF0R_TSSTSSEL_WIDTH 2 ++#define MAC_HWF0R_TXCOESEL_INDEX 14 ++#define MAC_HWF0R_TXCOESEL_WIDTH 1 ++#define MAC_HWF0R_VLHASH_INDEX 4 ++#define MAC_HWF0R_VLHASH_WIDTH 1 ++#define MAC_HWF1R_ADVTHWORD_INDEX 13 ++#define MAC_HWF1R_ADVTHWORD_WIDTH 1 ++#define MAC_HWF1R_DBGMEMA_INDEX 19 ++#define MAC_HWF1R_DBGMEMA_WIDTH 1 ++#define MAC_HWF1R_DCBEN_INDEX 16 ++#define MAC_HWF1R_DCBEN_WIDTH 1 ++#define MAC_HWF1R_HASHTBLSZ_INDEX 24 ++#define MAC_HWF1R_HASHTBLSZ_WIDTH 3 ++#define MAC_HWF1R_L3L4FNUM_INDEX 27 ++#define MAC_HWF1R_L3L4FNUM_WIDTH 4 ++#define MAC_HWF1R_NUMTC_INDEX 21 ++#define MAC_HWF1R_NUMTC_WIDTH 3 ++#define MAC_HWF1R_RSSEN_INDEX 20 ++#define MAC_HWF1R_RSSEN_WIDTH 1 ++#define MAC_HWF1R_RXFIFOSIZE_INDEX 0 ++#define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 ++#define MAC_HWF1R_SPHEN_INDEX 17 ++#define MAC_HWF1R_SPHEN_WIDTH 1 ++#define MAC_HWF1R_TSOEN_INDEX 18 ++#define MAC_HWF1R_TSOEN_WIDTH 1 ++#define MAC_HWF1R_TXFIFOSIZE_INDEX 6 ++#define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 ++#define MAC_HWF2R_AUXSNAPNUM_INDEX 28 ++#define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 ++#define MAC_HWF2R_PPSOUTNUM_INDEX 24 ++#define MAC_HWF2R_PPSOUTNUM_WIDTH 3 ++#define MAC_HWF2R_RXCHCNT_INDEX 12 ++#define MAC_HWF2R_RXCHCNT_WIDTH 4 ++#define MAC_HWF2R_RXQCNT_INDEX 0 ++#define MAC_HWF2R_RXQCNT_WIDTH 4 ++#define MAC_HWF2R_TXCHCNT_INDEX 18 ++#define MAC_HWF2R_TXCHCNT_WIDTH 4 ++#define MAC_HWF2R_TXQCNT_INDEX 6 ++#define MAC_HWF2R_TXQCNT_WIDTH 4 ++#define MAC_IER_TSIE_INDEX 12 ++#define MAC_IER_TSIE_WIDTH 1 ++#define MAC_ISR_MMCRXIS_INDEX 9 ++#define MAC_ISR_MMCRXIS_WIDTH 1 ++#define MAC_ISR_MMCTXIS_INDEX 10 ++#define MAC_ISR_MMCTXIS_WIDTH 1 ++#define MAC_ISR_PMTIS_INDEX 4 ++#define MAC_ISR_PMTIS_WIDTH 1 ++#define MAC_ISR_TSIS_INDEX 12 ++#define MAC_ISR_TSIS_WIDTH 1 ++#define MAC_MACA1HR_AE_INDEX 31 ++#define MAC_MACA1HR_AE_WIDTH 1 ++#define MAC_PFR_HMC_INDEX 2 ++#define MAC_PFR_HMC_WIDTH 1 ++#define MAC_PFR_HPF_INDEX 10 ++#define MAC_PFR_HPF_WIDTH 1 ++#define MAC_PFR_HUC_INDEX 1 ++#define MAC_PFR_HUC_WIDTH 1 ++#define MAC_PFR_PM_INDEX 4 ++#define MAC_PFR_PM_WIDTH 1 ++#define MAC_PFR_PR_INDEX 0 ++#define MAC_PFR_PR_WIDTH 1 ++#define MAC_PFR_VTFE_INDEX 16 ++#define MAC_PFR_VTFE_WIDTH 1 ++#define MAC_PMTCSR_MGKPKTEN_INDEX 1 ++#define MAC_PMTCSR_MGKPKTEN_WIDTH 1 ++#define MAC_PMTCSR_PWRDWN_INDEX 0 ++#define MAC_PMTCSR_PWRDWN_WIDTH 1 ++#define MAC_PMTCSR_RWKFILTRST_INDEX 31 ++#define MAC_PMTCSR_RWKFILTRST_WIDTH 1 ++#define MAC_PMTCSR_RWKPKTEN_INDEX 2 ++#define MAC_PMTCSR_RWKPKTEN_WIDTH 1 ++#define MAC_Q0TFCR_PT_INDEX 16 ++#define MAC_Q0TFCR_PT_WIDTH 16 ++#define MAC_Q0TFCR_TFE_INDEX 1 ++#define MAC_Q0TFCR_TFE_WIDTH 1 ++#define MAC_RCR_ACS_INDEX 1 ++#define MAC_RCR_ACS_WIDTH 1 ++#define MAC_RCR_CST_INDEX 2 ++#define MAC_RCR_CST_WIDTH 1 ++#define MAC_RCR_DCRCC_INDEX 3 ++#define MAC_RCR_DCRCC_WIDTH 1 ++#define MAC_RCR_HDSMS_INDEX 12 ++#define MAC_RCR_HDSMS_WIDTH 3 ++#define MAC_RCR_IPC_INDEX 9 ++#define MAC_RCR_IPC_WIDTH 1 ++#define MAC_RCR_JE_INDEX 8 ++#define MAC_RCR_JE_WIDTH 1 ++#define MAC_RCR_LM_INDEX 10 ++#define MAC_RCR_LM_WIDTH 1 ++#define MAC_RCR_RE_INDEX 0 ++#define MAC_RCR_RE_WIDTH 1 ++#define MAC_RFCR_PFCE_INDEX 8 ++#define MAC_RFCR_PFCE_WIDTH 1 ++#define MAC_RFCR_RFE_INDEX 0 ++#define MAC_RFCR_RFE_WIDTH 1 ++#define MAC_RFCR_UP_INDEX 1 ++#define MAC_RFCR_UP_WIDTH 1 ++#define MAC_RQC0R_RXQ0EN_INDEX 0 ++#define MAC_RQC0R_RXQ0EN_WIDTH 2 ++#define MAC_RSSAR_ADDRT_INDEX 2 ++#define MAC_RSSAR_ADDRT_WIDTH 1 ++#define MAC_RSSAR_CT_INDEX 1 ++#define MAC_RSSAR_CT_WIDTH 1 ++#define MAC_RSSAR_OB_INDEX 0 ++#define MAC_RSSAR_OB_WIDTH 1 ++#define MAC_RSSAR_RSSIA_INDEX 8 ++#define MAC_RSSAR_RSSIA_WIDTH 8 ++#define MAC_RSSCR_IP2TE_INDEX 1 ++#define MAC_RSSCR_IP2TE_WIDTH 1 ++#define MAC_RSSCR_RSSE_INDEX 0 ++#define MAC_RSSCR_RSSE_WIDTH 1 ++#define MAC_RSSCR_TCP4TE_INDEX 2 ++#define MAC_RSSCR_TCP4TE_WIDTH 1 ++#define MAC_RSSCR_UDP4TE_INDEX 3 ++#define MAC_RSSCR_UDP4TE_WIDTH 1 ++#define MAC_RSSDR_DMCH_INDEX 0 ++#define MAC_RSSDR_DMCH_WIDTH 4 ++#define MAC_SSIR_SNSINC_INDEX 8 ++#define MAC_SSIR_SNSINC_WIDTH 8 ++#define MAC_SSIR_SSINC_INDEX 16 ++#define MAC_SSIR_SSINC_WIDTH 8 ++#define MAC_TCR_SS_INDEX 29 ++#define MAC_TCR_SS_WIDTH 2 ++#define MAC_TCR_TE_INDEX 0 ++#define MAC_TCR_TE_WIDTH 1 ++#define MAC_TSCR_AV8021ASMEN_INDEX 28 ++#define MAC_TSCR_AV8021ASMEN_WIDTH 1 ++#define MAC_TSCR_SNAPTYPSEL_INDEX 16 ++#define MAC_TSCR_SNAPTYPSEL_WIDTH 2 ++#define MAC_TSCR_TSADDREG_INDEX 5 ++#define MAC_TSCR_TSADDREG_WIDTH 1 ++#define MAC_TSCR_TSCFUPDT_INDEX 1 ++#define MAC_TSCR_TSCFUPDT_WIDTH 1 ++#define MAC_TSCR_TSCTRLSSR_INDEX 9 ++#define MAC_TSCR_TSCTRLSSR_WIDTH 1 ++#define MAC_TSCR_TSENA_INDEX 0 ++#define MAC_TSCR_TSENA_WIDTH 1 ++#define MAC_TSCR_TSENALL_INDEX 8 ++#define MAC_TSCR_TSENALL_WIDTH 1 ++#define MAC_TSCR_TSEVNTENA_INDEX 14 ++#define MAC_TSCR_TSEVNTENA_WIDTH 1 ++#define MAC_TSCR_TSINIT_INDEX 2 ++#define MAC_TSCR_TSINIT_WIDTH 1 ++#define MAC_TSCR_TSIPENA_INDEX 11 ++#define MAC_TSCR_TSIPENA_WIDTH 1 ++#define MAC_TSCR_TSIPV4ENA_INDEX 13 ++#define MAC_TSCR_TSIPV4ENA_WIDTH 1 ++#define MAC_TSCR_TSIPV6ENA_INDEX 12 ++#define MAC_TSCR_TSIPV6ENA_WIDTH 1 ++#define MAC_TSCR_TSMSTRENA_INDEX 15 ++#define MAC_TSCR_TSMSTRENA_WIDTH 1 ++#define MAC_TSCR_TSVER2ENA_INDEX 10 ++#define MAC_TSCR_TSVER2ENA_WIDTH 1 ++#define MAC_TSCR_TXTSSTSM_INDEX 24 ++#define MAC_TSCR_TXTSSTSM_WIDTH 1 ++#define MAC_TSSR_TXTSC_INDEX 15 ++#define MAC_TSSR_TXTSC_WIDTH 1 ++#define MAC_TXSNR_TXTSSTSMIS_INDEX 31 ++#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 ++#define MAC_VLANHTR_VLHT_INDEX 0 ++#define MAC_VLANHTR_VLHT_WIDTH 16 ++#define MAC_VLANIR_VLTI_INDEX 20 ++#define MAC_VLANIR_VLTI_WIDTH 1 ++#define MAC_VLANIR_CSVL_INDEX 19 ++#define MAC_VLANIR_CSVL_WIDTH 1 ++#define MAC_VLANTR_DOVLTC_INDEX 20 ++#define MAC_VLANTR_DOVLTC_WIDTH 1 ++#define MAC_VLANTR_ERSVLM_INDEX 19 ++#define MAC_VLANTR_ERSVLM_WIDTH 1 ++#define MAC_VLANTR_ESVL_INDEX 18 ++#define MAC_VLANTR_ESVL_WIDTH 1 ++#define MAC_VLANTR_ETV_INDEX 16 ++#define MAC_VLANTR_ETV_WIDTH 1 ++#define MAC_VLANTR_EVLS_INDEX 21 ++#define MAC_VLANTR_EVLS_WIDTH 2 ++#define MAC_VLANTR_EVLRXS_INDEX 24 ++#define MAC_VLANTR_EVLRXS_WIDTH 1 ++#define MAC_VLANTR_VL_INDEX 0 ++#define MAC_VLANTR_VL_WIDTH 16 ++#define MAC_VLANTR_VTHM_INDEX 25 ++#define MAC_VLANTR_VTHM_WIDTH 1 ++#define MAC_VLANTR_VTIM_INDEX 17 ++#define MAC_VLANTR_VTIM_WIDTH 1 ++#define MAC_VR_DEVID_INDEX 8 ++#define MAC_VR_DEVID_WIDTH 8 ++#define MAC_VR_SNPSVER_INDEX 0 ++#define MAC_VR_SNPSVER_WIDTH 8 ++#define MAC_VR_USERVER_INDEX 16 ++#define MAC_VR_USERVER_WIDTH 8 ++ ++/* MMC register offsets */ ++#define MMC_CR 0x0800 ++#define MMC_RISR 0x0804 ++#define MMC_TISR 0x0808 ++#define MMC_RIER 0x080c ++#define MMC_TIER 0x0810 ++#define MMC_TXOCTETCOUNT_GB_LO 0x0814 ++#define MMC_TXOCTETCOUNT_GB_HI 0x0818 ++#define MMC_TXFRAMECOUNT_GB_LO 0x081c ++#define MMC_TXFRAMECOUNT_GB_HI 0x0820 ++#define MMC_TXBROADCASTFRAMES_G_LO 0x0824 ++#define MMC_TXBROADCASTFRAMES_G_HI 0x0828 ++#define MMC_TXMULTICASTFRAMES_G_LO 0x082c ++#define MMC_TXMULTICASTFRAMES_G_HI 0x0830 ++#define MMC_TX64OCTETS_GB_LO 0x0834 ++#define MMC_TX64OCTETS_GB_HI 0x0838 ++#define MMC_TX65TO127OCTETS_GB_LO 0x083c ++#define MMC_TX65TO127OCTETS_GB_HI 0x0840 ++#define MMC_TX128TO255OCTETS_GB_LO 0x0844 ++#define MMC_TX128TO255OCTETS_GB_HI 0x0848 ++#define MMC_TX256TO511OCTETS_GB_LO 0x084c ++#define MMC_TX256TO511OCTETS_GB_HI 0x0850 ++#define MMC_TX512TO1023OCTETS_GB_LO 0x0854 ++#define MMC_TX512TO1023OCTETS_GB_HI 0x0858 ++#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c ++#define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 ++#define MMC_TXUNICASTFRAMES_GB_LO 0x0864 ++#define MMC_TXUNICASTFRAMES_GB_HI 0x0868 ++#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c ++#define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 ++#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 ++#define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 ++#define MMC_TXUNDERFLOWERROR_LO 0x087c ++#define MMC_TXUNDERFLOWERROR_HI 0x0880 ++#define MMC_TXOCTETCOUNT_G_LO 0x0884 ++#define MMC_TXOCTETCOUNT_G_HI 0x0888 ++#define MMC_TXFRAMECOUNT_G_LO 0x088c ++#define MMC_TXFRAMECOUNT_G_HI 0x0890 ++#define MMC_TXPAUSEFRAMES_LO 0x0894 ++#define MMC_TXPAUSEFRAMES_HI 0x0898 ++#define MMC_TXVLANFRAMES_G_LO 0x089c ++#define MMC_TXVLANFRAMES_G_HI 0x08a0 ++#define MMC_RXFRAMECOUNT_GB_LO 0x0900 ++#define MMC_RXFRAMECOUNT_GB_HI 0x0904 ++#define MMC_RXOCTETCOUNT_GB_LO 0x0908 ++#define MMC_RXOCTETCOUNT_GB_HI 0x090c ++#define MMC_RXOCTETCOUNT_G_LO 0x0910 ++#define MMC_RXOCTETCOUNT_G_HI 0x0914 ++#define MMC_RXBROADCASTFRAMES_G_LO 0x0918 ++#define MMC_RXBROADCASTFRAMES_G_HI 0x091c ++#define MMC_RXMULTICASTFRAMES_G_LO 0x0920 ++#define MMC_RXMULTICASTFRAMES_G_HI 0x0924 ++#define MMC_RXCRCERROR_LO 0x0928 ++#define MMC_RXCRCERROR_HI 0x092c ++#define MMC_RXRUNTERROR 0x0930 ++#define MMC_RXJABBERERROR 0x0934 ++#define MMC_RXUNDERSIZE_G 0x0938 ++#define MMC_RXOVERSIZE_G 0x093c ++#define MMC_RX64OCTETS_GB_LO 0x0940 ++#define MMC_RX64OCTETS_GB_HI 0x0944 ++#define MMC_RX65TO127OCTETS_GB_LO 0x0948 ++#define MMC_RX65TO127OCTETS_GB_HI 0x094c ++#define MMC_RX128TO255OCTETS_GB_LO 0x0950 ++#define MMC_RX128TO255OCTETS_GB_HI 0x0954 ++#define MMC_RX256TO511OCTETS_GB_LO 0x0958 ++#define MMC_RX256TO511OCTETS_GB_HI 0x095c ++#define MMC_RX512TO1023OCTETS_GB_LO 0x0960 ++#define MMC_RX512TO1023OCTETS_GB_HI 0x0964 ++#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 ++#define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c ++#define MMC_RXUNICASTFRAMES_G_LO 0x0970 ++#define MMC_RXUNICASTFRAMES_G_HI 0x0974 ++#define MMC_RXLENGTHERROR_LO 0x0978 ++#define MMC_RXLENGTHERROR_HI 0x097c ++#define MMC_RXOUTOFRANGETYPE_LO 0x0980 ++#define MMC_RXOUTOFRANGETYPE_HI 0x0984 ++#define MMC_RXPAUSEFRAMES_LO 0x0988 ++#define MMC_RXPAUSEFRAMES_HI 0x098c ++#define MMC_RXFIFOOVERFLOW_LO 0x0990 ++#define MMC_RXFIFOOVERFLOW_HI 0x0994 ++#define MMC_RXVLANFRAMES_GB_LO 0x0998 ++#define MMC_RXVLANFRAMES_GB_HI 0x099c ++#define MMC_RXWATCHDOGERROR 0x09a0 ++ ++/* MMC register entry bit positions and sizes */ ++#define MMC_CR_CR_INDEX 0 ++#define MMC_CR_CR_WIDTH 1 ++#define MMC_CR_CSR_INDEX 1 ++#define MMC_CR_CSR_WIDTH 1 ++#define MMC_CR_ROR_INDEX 2 ++#define MMC_CR_ROR_WIDTH 1 ++#define MMC_CR_MCF_INDEX 3 ++#define MMC_CR_MCF_WIDTH 1 ++#define MMC_CR_MCT_INDEX 4 ++#define MMC_CR_MCT_WIDTH 2 ++#define MMC_RIER_ALL_INTERRUPTS_INDEX 0 ++#define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 ++#define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 ++#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 ++#define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 ++#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 ++#define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 ++#define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 ++#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 ++#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 ++#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 ++#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 ++#define MMC_RISR_RXCRCERROR_INDEX 5 ++#define MMC_RISR_RXCRCERROR_WIDTH 1 ++#define MMC_RISR_RXRUNTERROR_INDEX 6 ++#define MMC_RISR_RXRUNTERROR_WIDTH 1 ++#define MMC_RISR_RXJABBERERROR_INDEX 7 ++#define MMC_RISR_RXJABBERERROR_WIDTH 1 ++#define MMC_RISR_RXUNDERSIZE_G_INDEX 8 ++#define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 ++#define MMC_RISR_RXOVERSIZE_G_INDEX 9 ++#define MMC_RISR_RXOVERSIZE_G_WIDTH 1 ++#define MMC_RISR_RX64OCTETS_GB_INDEX 10 ++#define MMC_RISR_RX64OCTETS_GB_WIDTH 1 ++#define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 ++#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 ++#define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 ++#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 ++#define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 ++#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 ++#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 ++#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 ++#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 ++#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 ++#define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 ++#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 ++#define MMC_RISR_RXLENGTHERROR_INDEX 17 ++#define MMC_RISR_RXLENGTHERROR_WIDTH 1 ++#define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 ++#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 ++#define MMC_RISR_RXPAUSEFRAMES_INDEX 19 ++#define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 ++#define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 ++#define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 ++#define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 ++#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 ++#define MMC_RISR_RXWATCHDOGERROR_INDEX 22 ++#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 ++#define MMC_TIER_ALL_INTERRUPTS_INDEX 0 ++#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 ++#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 ++#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 ++#define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 ++#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 ++#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 ++#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 ++#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 ++#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 ++#define MMC_TISR_TX64OCTETS_GB_INDEX 4 ++#define MMC_TISR_TX64OCTETS_GB_WIDTH 1 ++#define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 ++#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 ++#define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 ++#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 ++#define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 ++#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 ++#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 ++#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 ++#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 ++#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 ++#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 ++#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 ++#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 ++#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 ++#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 ++#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 ++#define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 ++#define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 ++#define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 ++#define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 ++#define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 ++#define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 ++#define MMC_TISR_TXPAUSEFRAMES_INDEX 16 ++#define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 ++#define MMC_TISR_TXVLANFRAMES_G_INDEX 17 ++#define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 ++ ++/* MTL register offsets */ ++#define MTL_OMR 0x1000 ++#define MTL_FDCR 0x1008 ++#define MTL_FDSR 0x100c ++#define MTL_FDDR 0x1010 ++#define MTL_ISR 0x1020 ++#define MTL_RQDCM0R 0x1030 ++#define MTL_TCPM0R 0x1040 ++#define MTL_TCPM1R 0x1044 ++ ++#define MTL_RQDCM_INC 4 ++#define MTL_RQDCM_Q_PER_REG 4 ++#define MTL_TCPM_INC 4 ++#define MTL_TCPM_TC_PER_REG 4 ++ ++/* MTL register entry bit positions and sizes */ ++#define MTL_OMR_ETSALG_INDEX 5 ++#define MTL_OMR_ETSALG_WIDTH 2 ++#define MTL_OMR_RAA_INDEX 2 ++#define MTL_OMR_RAA_WIDTH 1 ++ ++/* MTL queue register offsets ++ * Multiple queues can be active. The first queue has registers ++ * that begin at 0x1100. Each subsequent queue has registers that ++ * are accessed using an offset of 0x80 from the previous queue. ++ */ ++#define MTL_Q_BASE 0x1100 ++#define MTL_Q_INC 0x80 ++ ++#define MTL_Q_TQOMR 0x00 ++#define MTL_Q_TQUR 0x04 ++#define MTL_Q_TQDR 0x08 ++#define MTL_Q_RQOMR 0x40 ++#define MTL_Q_RQMPOCR 0x44 ++#define MTL_Q_RQDR 0x4c ++#define MTL_Q_IER 0x70 ++#define MTL_Q_ISR 0x74 ++ ++/* MTL queue register entry bit positions and sizes */ ++#define MTL_Q_RQOMR_EHFC_INDEX 7 ++#define MTL_Q_RQOMR_EHFC_WIDTH 1 ++#define MTL_Q_RQOMR_RFA_INDEX 8 ++#define MTL_Q_RQOMR_RFA_WIDTH 3 ++#define MTL_Q_RQOMR_RFD_INDEX 13 ++#define MTL_Q_RQOMR_RFD_WIDTH 3 ++#define MTL_Q_RQOMR_RQS_INDEX 16 ++#define MTL_Q_RQOMR_RQS_WIDTH 9 ++#define MTL_Q_RQOMR_RSF_INDEX 5 ++#define MTL_Q_RQOMR_RSF_WIDTH 1 ++#define MTL_Q_RQOMR_RTC_INDEX 0 ++#define MTL_Q_RQOMR_RTC_WIDTH 2 ++#define MTL_Q_TQOMR_FTQ_INDEX 0 ++#define MTL_Q_TQOMR_FTQ_WIDTH 1 ++#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 ++#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 ++#define MTL_Q_TQOMR_TQS_INDEX 16 ++#define MTL_Q_TQOMR_TQS_WIDTH 10 ++#define MTL_Q_TQOMR_TSF_INDEX 1 ++#define MTL_Q_TQOMR_TSF_WIDTH 1 ++#define MTL_Q_TQOMR_TTC_INDEX 4 ++#define MTL_Q_TQOMR_TTC_WIDTH 3 ++#define MTL_Q_TQOMR_TXQEN_INDEX 2 ++#define MTL_Q_TQOMR_TXQEN_WIDTH 2 ++ ++/* MTL queue register value */ ++#define MTL_RSF_DISABLE 0x00 ++#define MTL_RSF_ENABLE 0x01 ++#define MTL_TSF_DISABLE 0x00 ++#define MTL_TSF_ENABLE 0x01 ++ ++#define MTL_RX_THRESHOLD_64 0x00 ++#define MTL_RX_THRESHOLD_96 0x02 ++#define MTL_RX_THRESHOLD_128 0x03 ++#define MTL_TX_THRESHOLD_32 0x01 ++#define MTL_TX_THRESHOLD_64 0x00 ++#define MTL_TX_THRESHOLD_96 0x02 ++#define MTL_TX_THRESHOLD_128 0x03 ++#define MTL_TX_THRESHOLD_192 0x04 ++#define MTL_TX_THRESHOLD_256 0x05 ++#define MTL_TX_THRESHOLD_384 0x06 ++#define MTL_TX_THRESHOLD_512 0x07 ++ ++#define MTL_ETSALG_WRR 0x00 ++#define MTL_ETSALG_WFQ 0x01 ++#define MTL_ETSALG_DWRR 0x02 ++#define MTL_RAA_SP 0x00 ++#define MTL_RAA_WSP 0x01 ++ ++#define MTL_Q_DISABLED 0x00 ++#define MTL_Q_ENABLED 0x02 ++ ++/* MTL traffic class register offsets ++ * Multiple traffic classes can be active. The first class has registers ++ * that begin at 0x1100. Each subsequent queue has registers that ++ * are accessed using an offset of 0x80 from the previous queue. ++ */ ++#define MTL_TC_BASE MTL_Q_BASE ++#define MTL_TC_INC MTL_Q_INC ++ ++#define MTL_TC_ETSCR 0x10 ++#define MTL_TC_ETSSR 0x14 ++#define MTL_TC_QWR 0x18 ++ ++/* MTL traffic class register entry bit positions and sizes */ ++#define MTL_TC_ETSCR_TSA_INDEX 0 ++#define MTL_TC_ETSCR_TSA_WIDTH 2 ++#define MTL_TC_QWR_QW_INDEX 0 ++#define MTL_TC_QWR_QW_WIDTH 21 ++ ++/* MTL traffic class register value */ ++#define MTL_TSA_SP 0x00 ++#define MTL_TSA_ETS 0x02 ++ ++/* PCS MMD select register offset ++ * The MMD select register is used for accessing PCS registers ++ * when the underlying APB3 interface is using indirect addressing. ++ * Indirect addressing requires accessing registers in two phases, ++ * an address phase and a data phase. The address phases requires ++ * writing an address selection value to the MMD select regiesters. ++ */ ++#define PCS_MMD_SELECT 0xff ++ ++/* Descriptor/Packet entry bit positions and sizes */ ++#define RX_PACKET_ERRORS_CRC_INDEX 2 ++#define RX_PACKET_ERRORS_CRC_WIDTH 1 ++#define RX_PACKET_ERRORS_FRAME_INDEX 3 ++#define RX_PACKET_ERRORS_FRAME_WIDTH 1 ++#define RX_PACKET_ERRORS_LENGTH_INDEX 0 ++#define RX_PACKET_ERRORS_LENGTH_WIDTH 1 ++#define RX_PACKET_ERRORS_OVERRUN_INDEX 1 ++#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 ++ ++#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 ++#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 ++#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2 ++#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 ++#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 ++#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 ++#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 ++#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 ++#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 ++ ++#define RX_NORMAL_DESC0_OVT_INDEX 0 ++#define RX_NORMAL_DESC0_OVT_WIDTH 16 ++#define RX_NORMAL_DESC2_HL_INDEX 0 ++#define RX_NORMAL_DESC2_HL_WIDTH 10 ++#define RX_NORMAL_DESC3_CDA_INDEX 27 ++#define RX_NORMAL_DESC3_CDA_WIDTH 1 ++#define RX_NORMAL_DESC3_CTXT_INDEX 30 ++#define RX_NORMAL_DESC3_CTXT_WIDTH 1 ++#define RX_NORMAL_DESC3_ES_INDEX 15 ++#define RX_NORMAL_DESC3_ES_WIDTH 1 ++#define RX_NORMAL_DESC3_ETLT_INDEX 16 ++#define RX_NORMAL_DESC3_ETLT_WIDTH 4 ++#define RX_NORMAL_DESC3_FD_INDEX 29 ++#define RX_NORMAL_DESC3_FD_WIDTH 1 ++#define RX_NORMAL_DESC3_INTE_INDEX 30 ++#define RX_NORMAL_DESC3_INTE_WIDTH 1 ++#define RX_NORMAL_DESC3_L34T_INDEX 20 ++#define RX_NORMAL_DESC3_L34T_WIDTH 4 ++#define RX_NORMAL_DESC3_LD_INDEX 28 ++#define RX_NORMAL_DESC3_LD_WIDTH 1 ++#define RX_NORMAL_DESC3_OWN_INDEX 31 ++#define RX_NORMAL_DESC3_OWN_WIDTH 1 ++#define RX_NORMAL_DESC3_PL_INDEX 0 ++#define RX_NORMAL_DESC3_PL_WIDTH 14 ++#define RX_NORMAL_DESC3_RSV_INDEX 26 ++#define RX_NORMAL_DESC3_RSV_WIDTH 1 ++ ++#define RX_DESC3_L34T_IPV4_TCP 1 ++#define RX_DESC3_L34T_IPV4_UDP 2 ++#define RX_DESC3_L34T_IPV4_ICMP 3 ++#define RX_DESC3_L34T_IPV6_TCP 9 ++#define RX_DESC3_L34T_IPV6_UDP 10 ++#define RX_DESC3_L34T_IPV6_ICMP 11 ++ ++#define RX_CONTEXT_DESC3_TSA_INDEX 4 ++#define RX_CONTEXT_DESC3_TSA_WIDTH 1 ++#define RX_CONTEXT_DESC3_TSD_INDEX 6 ++#define RX_CONTEXT_DESC3_TSD_WIDTH 1 ++ ++#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 ++#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 ++#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 ++#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 ++#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 ++#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 ++#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 ++#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 ++ ++#define TX_CONTEXT_DESC2_MSS_INDEX 0 ++#define TX_CONTEXT_DESC2_MSS_WIDTH 15 ++#define TX_CONTEXT_DESC3_CTXT_INDEX 30 ++#define TX_CONTEXT_DESC3_CTXT_WIDTH 1 ++#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 ++#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 ++#define TX_CONTEXT_DESC3_VLTV_INDEX 16 ++#define TX_CONTEXT_DESC3_VLTV_WIDTH 1 ++#define TX_CONTEXT_DESC3_VT_INDEX 0 ++#define TX_CONTEXT_DESC3_VT_WIDTH 16 ++ ++#define TX_NORMAL_DESC2_HL_B1L_INDEX 0 ++#define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 ++#define TX_NORMAL_DESC2_IC_INDEX 31 ++#define TX_NORMAL_DESC2_IC_WIDTH 1 ++#define TX_NORMAL_DESC2_TTSE_INDEX 30 ++#define TX_NORMAL_DESC2_TTSE_WIDTH 1 ++#define TX_NORMAL_DESC2_VTIR_INDEX 14 ++#define TX_NORMAL_DESC2_VTIR_WIDTH 2 ++#define TX_NORMAL_DESC3_CIC_INDEX 16 ++#define TX_NORMAL_DESC3_CIC_WIDTH 2 ++#define TX_NORMAL_DESC3_CPC_INDEX 26 ++#define TX_NORMAL_DESC3_CPC_WIDTH 2 ++#define TX_NORMAL_DESC3_CTXT_INDEX 30 ++#define TX_NORMAL_DESC3_CTXT_WIDTH 1 ++#define TX_NORMAL_DESC3_FD_INDEX 29 ++#define TX_NORMAL_DESC3_FD_WIDTH 1 ++#define TX_NORMAL_DESC3_FL_INDEX 0 ++#define TX_NORMAL_DESC3_FL_WIDTH 15 ++#define TX_NORMAL_DESC3_LD_INDEX 28 ++#define TX_NORMAL_DESC3_LD_WIDTH 1 ++#define TX_NORMAL_DESC3_OWN_INDEX 31 ++#define TX_NORMAL_DESC3_OWN_WIDTH 1 ++#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 ++#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 ++#define TX_NORMAL_DESC3_TCPPL_INDEX 0 ++#define TX_NORMAL_DESC3_TCPPL_WIDTH 18 ++#define TX_NORMAL_DESC3_TSE_INDEX 18 ++#define TX_NORMAL_DESC3_TSE_WIDTH 1 ++ ++#define TX_NORMAL_DESC2_VLAN_INSERT 0x2 ++ ++/* MDIO undefined or vendor specific registers */ ++#ifndef MDIO_AN_COMP_STAT ++#define MDIO_AN_COMP_STAT 0x0030 ++#endif ++ ++/* Bit setting and getting macros ++ * The get macro will extract the current bit field value from within ++ * the variable ++ * ++ * The set macro will clear the current bit field value within the ++ * variable and then set the bit field of the variable to the ++ * specified value ++ */ ++#define GET_BITS(_var, _index, _width) \ ++ (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) ++ ++#define SET_BITS(_var, _index, _width, _val) \ ++do { \ ++ (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ ++ (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ ++} while (0) ++ ++#define GET_BITS_LE(_var, _index, _width) \ ++ ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) ++ ++#define SET_BITS_LE(_var, _index, _width, _val) \ ++do { \ ++ (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ ++ (_var) |= cpu_to_le32((((_val) & \ ++ ((0x1 << (_width)) - 1)) << (_index))); \ ++} while (0) ++ ++/* Bit setting and getting macros based on register fields ++ * The get macro uses the bit field definitions formed using the input ++ * names to extract the current bit field value from within the ++ * variable ++ * ++ * The set macro uses the bit field definitions formed using the input ++ * names to set the bit field of the variable to the specified value ++ */ ++#define XGMAC_GET_BITS(_var, _prefix, _field) \ ++ GET_BITS((_var), \ ++ _prefix##_##_field##_INDEX, \ ++ _prefix##_##_field##_WIDTH) ++ ++#define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ ++ SET_BITS((_var), \ ++ _prefix##_##_field##_INDEX, \ ++ _prefix##_##_field##_WIDTH, (_val)) ++ ++#define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ ++ GET_BITS_LE((_var), \ ++ _prefix##_##_field##_INDEX, \ ++ _prefix##_##_field##_WIDTH) ++ ++#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ ++ SET_BITS_LE((_var), \ ++ _prefix##_##_field##_INDEX, \ ++ _prefix##_##_field##_WIDTH, (_val)) ++ ++/* Macros for reading or writing registers ++ * The ioread macros will get bit fields or full values using the ++ * register definitions formed using the input names ++ * ++ * The iowrite macros will set bit fields or full values using the ++ * register definitions formed using the input names ++ */ ++#define XGMAC_IOREAD(_pdata, _reg) \ ++ ioread32((_pdata)->xgmac_regs + _reg) ++ ++#define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ ++ GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH) ++ ++#define XGMAC_IOWRITE(_pdata, _reg, _val) \ ++ iowrite32((_val), (_pdata)->xgmac_regs + _reg) ++ ++#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ ++do { \ ++ u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ ++ SET_BITS(reg_val, \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH, (_val)); \ ++ XGMAC_IOWRITE((_pdata), _reg, reg_val); \ ++} while (0) ++ ++/* Macros for reading or writing MTL queue or traffic class registers ++ * Similar to the standard read and write macros except that the ++ * base register value is calculated by the queue or traffic class number ++ */ ++#define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ ++ ioread32((_pdata)->xgmac_regs + \ ++ MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) ++ ++#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ ++ GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH) ++ ++#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ ++ iowrite32((_val), (_pdata)->xgmac_regs + \ ++ MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) ++ ++#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ ++do { \ ++ u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ ++ SET_BITS(reg_val, \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH, (_val)); \ ++ XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ ++} while (0) ++ ++/* Macros for reading or writing DMA channel registers ++ * Similar to the standard read and write macros except that the ++ * base register value is obtained from the ring ++ */ ++#define XGMAC_DMA_IOREAD(_channel, _reg) \ ++ ioread32((_channel)->dma_regs + _reg) ++ ++#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ ++ GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH) ++ ++#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ ++ iowrite32((_val), (_channel)->dma_regs + _reg) ++ ++#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ ++do { \ ++ u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ ++ SET_BITS(reg_val, \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH, (_val)); \ ++ XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ ++} while (0) ++ ++/* Macros for building, reading or writing register values or bits ++ * within the register values of XPCS registers. ++ */ ++#define XPCS_IOWRITE(_pdata, _off, _val) \ ++ iowrite32(_val, (_pdata)->xpcs_regs + (_off)) ++ ++#define XPCS_IOREAD(_pdata, _off) \ ++ ioread32((_pdata)->xpcs_regs + (_off)) ++ ++/* Macros for building, reading or writing register values or bits ++ * using MDIO. Different from above because of the use of standardized ++ * Linux include values. No shifting is performed with the bit ++ * operations, everything works on mask values. ++ */ ++#define XMDIO_READ(_pdata, _mmd, _reg) \ ++ ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ ++ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) ++ ++#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ ++ (XMDIO_READ((_pdata), _mmd, _reg) & _mask) ++ ++#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ ++ ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ ++ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) ++ ++#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ ++do { \ ++ u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ ++ mmd_val &= ~_mask; \ ++ mmd_val |= (_val); \ ++ XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ ++} while (0) ++ ++#endif +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c +new file mode 100644 +index 0000000..343301c +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c +@@ -0,0 +1,269 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static int xgbe_dcb_ieee_getets(struct net_device *netdev, ++ struct ieee_ets *ets) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ /* Set number of supported traffic classes */ ++ ets->ets_cap = pdata->hw_feat.tc_cnt; ++ ++ if (pdata->ets) { ++ ets->cbs = pdata->ets->cbs; ++ memcpy(ets->tc_tx_bw, pdata->ets->tc_tx_bw, ++ sizeof(ets->tc_tx_bw)); ++ memcpy(ets->tc_tsa, pdata->ets->tc_tsa, ++ sizeof(ets->tc_tsa)); ++ memcpy(ets->prio_tc, pdata->ets->prio_tc, ++ sizeof(ets->prio_tc)); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_dcb_ieee_setets(struct net_device *netdev, ++ struct ieee_ets *ets) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ unsigned int i, tc_ets, tc_ets_weight; ++ ++ tc_ets = 0; ++ tc_ets_weight = 0; ++ for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { ++ DBGPR(" TC%u: tx_bw=%hhu, rx_bw=%hhu, tsa=%hhu\n", i, ++ ets->tc_tx_bw[i], ets->tc_rx_bw[i], ets->tc_tsa[i]); ++ DBGPR(" PRIO%u: TC=%hhu\n", i, ets->prio_tc[i]); ++ ++ if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) && ++ (i >= pdata->hw_feat.tc_cnt)) ++ return -EINVAL; ++ ++ if (ets->prio_tc[i] >= pdata->hw_feat.tc_cnt) ++ return -EINVAL; ++ ++ switch (ets->tc_tsa[i]) { ++ case IEEE_8021QAZ_TSA_STRICT: ++ break; ++ case IEEE_8021QAZ_TSA_ETS: ++ tc_ets = 1; ++ tc_ets_weight += ets->tc_tx_bw[i]; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ /* Weights must add up to 100% */ ++ if (tc_ets && (tc_ets_weight != 100)) ++ return -EINVAL; ++ ++ if (!pdata->ets) { ++ pdata->ets = devm_kzalloc(pdata->dev, sizeof(*pdata->ets), ++ GFP_KERNEL); ++ if (!pdata->ets) ++ return -ENOMEM; ++ } ++ ++ memcpy(pdata->ets, ets, sizeof(*pdata->ets)); ++ ++ pdata->hw_if.config_dcb_tc(pdata); ++ ++ return 0; ++} ++ ++static int xgbe_dcb_ieee_getpfc(struct net_device *netdev, ++ struct ieee_pfc *pfc) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ /* Set number of supported PFC traffic classes */ ++ pfc->pfc_cap = pdata->hw_feat.tc_cnt; ++ ++ if (pdata->pfc) { ++ pfc->pfc_en = pdata->pfc->pfc_en; ++ pfc->mbc = pdata->pfc->mbc; ++ pfc->delay = pdata->pfc->delay; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_dcb_ieee_setpfc(struct net_device *netdev, ++ struct ieee_pfc *pfc) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ DBGPR(" cap=%hhu, en=%hhx, mbc=%hhu, delay=%hhu\n", ++ pfc->pfc_cap, pfc->pfc_en, pfc->mbc, pfc->delay); ++ ++ if (!pdata->pfc) { ++ pdata->pfc = devm_kzalloc(pdata->dev, sizeof(*pdata->pfc), ++ GFP_KERNEL); ++ if (!pdata->pfc) ++ return -ENOMEM; ++ } ++ ++ memcpy(pdata->pfc, pfc, sizeof(*pdata->pfc)); ++ ++ pdata->hw_if.config_dcb_pfc(pdata); ++ ++ return 0; ++} ++ ++static u8 xgbe_dcb_getdcbx(struct net_device *netdev) ++{ ++ return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE; ++} ++ ++static u8 xgbe_dcb_setdcbx(struct net_device *netdev, u8 dcbx) ++{ ++ u8 support = xgbe_dcb_getdcbx(netdev); ++ ++ DBGPR(" DCBX=%#hhx\n", dcbx); ++ ++ if (dcbx & ~support) ++ return 1; ++ ++ if ((dcbx & support) != support) ++ return 1; ++ ++ return 0; ++} ++ ++static const struct dcbnl_rtnl_ops xgbe_dcbnl_ops = { ++ /* IEEE 802.1Qaz std */ ++ .ieee_getets = xgbe_dcb_ieee_getets, ++ .ieee_setets = xgbe_dcb_ieee_setets, ++ .ieee_getpfc = xgbe_dcb_ieee_getpfc, ++ .ieee_setpfc = xgbe_dcb_ieee_setpfc, ++ ++ /* DCBX configuration */ ++ .getdcbx = xgbe_dcb_getdcbx, ++ .setdcbx = xgbe_dcb_setdcbx, ++}; ++ ++const struct dcbnl_rtnl_ops *xgbe_a0_get_dcbnl_ops(void) ++{ ++ return &xgbe_dcbnl_ops; ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c +new file mode 100644 +index 0000000..ecfa6f9 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c +@@ -0,0 +1,373 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static ssize_t xgbe_common_read(char __user *buffer, size_t count, ++ loff_t *ppos, unsigned int value) ++{ ++ char *buf; ++ ssize_t len; ++ ++ if (*ppos != 0) ++ return 0; ++ ++ buf = kasprintf(GFP_KERNEL, "0x%08x\n", value); ++ if (!buf) ++ return -ENOMEM; ++ ++ if (count < strlen(buf)) { ++ kfree(buf); ++ return -ENOSPC; ++ } ++ ++ len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); ++ kfree(buf); ++ ++ return len; ++} ++ ++static ssize_t xgbe_common_write(const char __user *buffer, size_t count, ++ loff_t *ppos, unsigned int *value) ++{ ++ char workarea[32]; ++ ssize_t len; ++ int ret; ++ ++ if (*ppos != 0) ++ return 0; ++ ++ if (count >= sizeof(workarea)) ++ return -ENOSPC; ++ ++ len = simple_write_to_buffer(workarea, sizeof(workarea) - 1, ppos, ++ buffer, count); ++ if (len < 0) ++ return len; ++ ++ workarea[len] = '\0'; ++ ret = kstrtouint(workarea, 16, value); ++ if (ret) ++ return -EIO; ++ ++ return len; ++} ++ ++static ssize_t xgmac_reg_addr_read(struct file *filp, char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xgmac_reg); ++} ++ ++static ssize_t xgmac_reg_addr_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_write(buffer, count, ppos, ++ &pdata->debugfs_xgmac_reg); ++} ++ ++static ssize_t xgmac_reg_value_read(struct file *filp, char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ unsigned int value; ++ ++ value = XGMAC_IOREAD(pdata, pdata->debugfs_xgmac_reg); ++ ++ return xgbe_common_read(buffer, count, ppos, value); ++} ++ ++static ssize_t xgmac_reg_value_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ unsigned int value; ++ ssize_t len; ++ ++ len = xgbe_common_write(buffer, count, ppos, &value); ++ if (len < 0) ++ return len; ++ ++ XGMAC_IOWRITE(pdata, pdata->debugfs_xgmac_reg, value); ++ ++ return len; ++} ++ ++static const struct file_operations xgmac_reg_addr_fops = { ++ .owner = THIS_MODULE, ++ .open = simple_open, ++ .read = xgmac_reg_addr_read, ++ .write = xgmac_reg_addr_write, ++}; ++ ++static const struct file_operations xgmac_reg_value_fops = { ++ .owner = THIS_MODULE, ++ .open = simple_open, ++ .read = xgmac_reg_value_read, ++ .write = xgmac_reg_value_write, ++}; ++ ++static ssize_t xpcs_mmd_read(struct file *filp, char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_mmd); ++} ++ ++static ssize_t xpcs_mmd_write(struct file *filp, const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_write(buffer, count, ppos, ++ &pdata->debugfs_xpcs_mmd); ++} ++ ++static ssize_t xpcs_reg_addr_read(struct file *filp, char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_reg); ++} ++ ++static ssize_t xpcs_reg_addr_write(struct file *filp, const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ ++ return xgbe_common_write(buffer, count, ppos, ++ &pdata->debugfs_xpcs_reg); ++} ++ ++static ssize_t xpcs_reg_value_read(struct file *filp, char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ unsigned int value; ++ ++ value = XMDIO_READ(pdata, pdata->debugfs_xpcs_mmd, ++ pdata->debugfs_xpcs_reg); ++ ++ return xgbe_common_read(buffer, count, ppos, value); ++} ++ ++static ssize_t xpcs_reg_value_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct xgbe_prv_data *pdata = filp->private_data; ++ unsigned int value; ++ ssize_t len; ++ ++ len = xgbe_common_write(buffer, count, ppos, &value); ++ if (len < 0) ++ return len; ++ ++ XMDIO_WRITE(pdata, pdata->debugfs_xpcs_mmd, pdata->debugfs_xpcs_reg, ++ value); ++ ++ return len; ++} ++ ++static const struct file_operations xpcs_mmd_fops = { ++ .owner = THIS_MODULE, ++ .open = simple_open, ++ .read = xpcs_mmd_read, ++ .write = xpcs_mmd_write, ++}; ++ ++static const struct file_operations xpcs_reg_addr_fops = { ++ .owner = THIS_MODULE, ++ .open = simple_open, ++ .read = xpcs_reg_addr_read, ++ .write = xpcs_reg_addr_write, ++}; ++ ++static const struct file_operations xpcs_reg_value_fops = { ++ .owner = THIS_MODULE, ++ .open = simple_open, ++ .read = xpcs_reg_value_read, ++ .write = xpcs_reg_value_write, ++}; ++ ++void xgbe_a0_debugfs_init(struct xgbe_prv_data *pdata) ++{ ++ struct dentry *pfile; ++ char *buf; ++ ++ /* Set defaults */ ++ pdata->debugfs_xgmac_reg = 0; ++ pdata->debugfs_xpcs_mmd = 1; ++ pdata->debugfs_xpcs_reg = 0; ++ ++ buf = kasprintf(GFP_KERNEL, "amd-xgbe-a0-%s", pdata->netdev->name); ++ pdata->xgbe_debugfs = debugfs_create_dir(buf, NULL); ++ if (!pdata->xgbe_debugfs) { ++ netdev_err(pdata->netdev, "debugfs_create_dir failed\n"); ++ return; ++ } ++ ++ pfile = debugfs_create_file("xgmac_register", 0600, ++ pdata->xgbe_debugfs, pdata, ++ &xgmac_reg_addr_fops); ++ if (!pfile) ++ netdev_err(pdata->netdev, "debugfs_create_file failed\n"); ++ ++ pfile = debugfs_create_file("xgmac_register_value", 0600, ++ pdata->xgbe_debugfs, pdata, ++ &xgmac_reg_value_fops); ++ if (!pfile) ++ netdev_err(pdata->netdev, "debugfs_create_file failed\n"); ++ ++ pfile = debugfs_create_file("xpcs_mmd", 0600, ++ pdata->xgbe_debugfs, pdata, ++ &xpcs_mmd_fops); ++ if (!pfile) ++ netdev_err(pdata->netdev, "debugfs_create_file failed\n"); ++ ++ pfile = debugfs_create_file("xpcs_register", 0600, ++ pdata->xgbe_debugfs, pdata, ++ &xpcs_reg_addr_fops); ++ if (!pfile) ++ netdev_err(pdata->netdev, "debugfs_create_file failed\n"); ++ ++ pfile = debugfs_create_file("xpcs_register_value", 0600, ++ pdata->xgbe_debugfs, pdata, ++ &xpcs_reg_value_fops); ++ if (!pfile) ++ netdev_err(pdata->netdev, "debugfs_create_file failed\n"); ++ ++ kfree(buf); ++} ++ ++void xgbe_a0_debugfs_exit(struct xgbe_prv_data *pdata) ++{ ++ debugfs_remove_recursive(pdata->xgbe_debugfs); ++ pdata->xgbe_debugfs = NULL; ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c +new file mode 100644 +index 0000000..5dd5777 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c +@@ -0,0 +1,636 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static void xgbe_unmap_rdata(struct xgbe_prv_data *, struct xgbe_ring_data *); ++ ++static void xgbe_free_ring(struct xgbe_prv_data *pdata, ++ struct xgbe_ring *ring) ++{ ++ struct xgbe_ring_data *rdata; ++ unsigned int i; ++ ++ if (!ring) ++ return; ++ ++ if (ring->rdata) { ++ for (i = 0; i < ring->rdesc_count; i++) { ++ rdata = XGBE_GET_DESC_DATA(ring, i); ++ xgbe_unmap_rdata(pdata, rdata); ++ } ++ ++ kfree(ring->rdata); ++ ring->rdata = NULL; ++ } ++ ++ if (ring->rx_hdr_pa.pages) { ++ dma_unmap_page(pdata->dev, ring->rx_hdr_pa.pages_dma, ++ ring->rx_hdr_pa.pages_len, DMA_FROM_DEVICE); ++ put_page(ring->rx_hdr_pa.pages); ++ ++ ring->rx_hdr_pa.pages = NULL; ++ ring->rx_hdr_pa.pages_len = 0; ++ ring->rx_hdr_pa.pages_offset = 0; ++ ring->rx_hdr_pa.pages_dma = 0; ++ } ++ ++ if (ring->rx_buf_pa.pages) { ++ dma_unmap_page(pdata->dev, ring->rx_buf_pa.pages_dma, ++ ring->rx_buf_pa.pages_len, DMA_FROM_DEVICE); ++ put_page(ring->rx_buf_pa.pages); ++ ++ ring->rx_buf_pa.pages = NULL; ++ ring->rx_buf_pa.pages_len = 0; ++ ring->rx_buf_pa.pages_offset = 0; ++ ring->rx_buf_pa.pages_dma = 0; ++ } ++ ++ if (ring->rdesc) { ++ dma_free_coherent(pdata->dev, ++ (sizeof(struct xgbe_ring_desc) * ++ ring->rdesc_count), ++ ring->rdesc, ring->rdesc_dma); ++ ring->rdesc = NULL; ++ } ++} ++ ++static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_free_ring_resources\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ xgbe_free_ring(pdata, channel->tx_ring); ++ xgbe_free_ring(pdata, channel->rx_ring); ++ } ++ ++ DBGPR("<--xgbe_free_ring_resources\n"); ++} ++ ++static int xgbe_init_ring(struct xgbe_prv_data *pdata, ++ struct xgbe_ring *ring, unsigned int rdesc_count) ++{ ++ DBGPR("-->xgbe_init_ring\n"); ++ ++ if (!ring) ++ return 0; ++ ++ /* Descriptors */ ++ ring->rdesc_count = rdesc_count; ++ ring->rdesc = dma_alloc_coherent(pdata->dev, ++ (sizeof(struct xgbe_ring_desc) * ++ rdesc_count), &ring->rdesc_dma, ++ GFP_KERNEL); ++ if (!ring->rdesc) ++ return -ENOMEM; ++ ++ /* Descriptor information */ ++ ring->rdata = kcalloc(rdesc_count, sizeof(struct xgbe_ring_data), ++ GFP_KERNEL); ++ if (!ring->rdata) ++ return -ENOMEM; ++ ++ DBGPR(" rdesc=0x%p, rdesc_dma=0x%llx, rdata=0x%p\n", ++ ring->rdesc, ring->rdesc_dma, ring->rdata); ++ ++ DBGPR("<--xgbe_init_ring\n"); ++ ++ return 0; ++} ++ ++static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ int ret; ++ ++ DBGPR("-->xgbe_alloc_ring_resources\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ DBGPR(" %s - tx_ring:\n", channel->name); ++ ret = xgbe_init_ring(pdata, channel->tx_ring, ++ pdata->tx_desc_count); ++ if (ret) { ++ netdev_alert(pdata->netdev, ++ "error initializing Tx ring\n"); ++ goto err_ring; ++ } ++ ++ DBGPR(" %s - rx_ring:\n", channel->name); ++ ret = xgbe_init_ring(pdata, channel->rx_ring, ++ pdata->rx_desc_count); ++ if (ret) { ++ netdev_alert(pdata->netdev, ++ "error initializing Tx ring\n"); ++ goto err_ring; ++ } ++ } ++ ++ DBGPR("<--xgbe_alloc_ring_resources\n"); ++ ++ return 0; ++ ++err_ring: ++ xgbe_free_ring_resources(pdata); ++ ++ return ret; ++} ++ ++static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, ++ struct xgbe_page_alloc *pa, gfp_t gfp, int order) ++{ ++ struct page *pages = NULL; ++ dma_addr_t pages_dma; ++ int ret; ++ ++ /* Try to obtain pages, decreasing order if necessary */ ++ gfp |= __GFP_COLD | __GFP_COMP; ++ while (order >= 0) { ++ pages = alloc_pages(gfp, order); ++ if (pages) ++ break; ++ ++ order--; ++ } ++ if (!pages) ++ return -ENOMEM; ++ ++ /* Map the pages */ ++ pages_dma = dma_map_page(pdata->dev, pages, 0, ++ PAGE_SIZE << order, DMA_FROM_DEVICE); ++ ret = dma_mapping_error(pdata->dev, pages_dma); ++ if (ret) { ++ put_page(pages); ++ return ret; ++ } ++ ++ pa->pages = pages; ++ pa->pages_len = PAGE_SIZE << order; ++ pa->pages_offset = 0; ++ pa->pages_dma = pages_dma; ++ ++ return 0; ++} ++ ++static void xgbe_set_buffer_data(struct xgbe_buffer_data *bd, ++ struct xgbe_page_alloc *pa, ++ unsigned int len) ++{ ++ get_page(pa->pages); ++ bd->pa = *pa; ++ ++ bd->dma = pa->pages_dma + pa->pages_offset; ++ bd->dma_len = len; ++ ++ pa->pages_offset += len; ++ if ((pa->pages_offset + len) > pa->pages_len) { ++ /* This data descriptor is responsible for unmapping page(s) */ ++ bd->pa_unmap = *pa; ++ ++ /* Get a new allocation next time */ ++ pa->pages = NULL; ++ pa->pages_len = 0; ++ pa->pages_offset = 0; ++ pa->pages_dma = 0; ++ } ++} ++ ++static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata, ++ struct xgbe_ring *ring, ++ struct xgbe_ring_data *rdata) ++{ ++ int order, ret; ++ ++ if (!ring->rx_hdr_pa.pages) { ++ ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0); ++ if (ret) ++ return ret; ++ } ++ ++ if (!ring->rx_buf_pa.pages) { ++ order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0); ++ ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC, ++ order); ++ if (ret) ++ return ret; ++ } ++ ++ /* Set up the header page info */ ++ xgbe_set_buffer_data(&rdata->rx.hdr, &ring->rx_hdr_pa, ++ XGBE_SKB_ALLOC_SIZE); ++ ++ /* Set up the buffer page info */ ++ xgbe_set_buffer_data(&rdata->rx.buf, &ring->rx_buf_pa, ++ pdata->rx_buf_size); ++ ++ return 0; ++} ++ ++static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ struct xgbe_ring *ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_ring_desc *rdesc; ++ dma_addr_t rdesc_dma; ++ unsigned int i, j; ++ ++ DBGPR("-->xgbe_wrapper_tx_descriptor_init\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ ring = channel->tx_ring; ++ if (!ring) ++ break; ++ ++ rdesc = ring->rdesc; ++ rdesc_dma = ring->rdesc_dma; ++ ++ for (j = 0; j < ring->rdesc_count; j++) { ++ rdata = XGBE_GET_DESC_DATA(ring, j); ++ ++ rdata->rdesc = rdesc; ++ rdata->rdesc_dma = rdesc_dma; ++ ++ rdesc++; ++ rdesc_dma += sizeof(struct xgbe_ring_desc); ++ } ++ ++ ring->cur = 0; ++ ring->dirty = 0; ++ memset(&ring->tx, 0, sizeof(ring->tx)); ++ ++ hw_if->tx_desc_init(channel); ++ } ++ ++ DBGPR("<--xgbe_wrapper_tx_descriptor_init\n"); ++} ++ ++static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ struct xgbe_ring *ring; ++ struct xgbe_ring_desc *rdesc; ++ struct xgbe_ring_data *rdata; ++ dma_addr_t rdesc_dma; ++ unsigned int i, j; ++ ++ DBGPR("-->xgbe_wrapper_rx_descriptor_init\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ ring = channel->rx_ring; ++ if (!ring) ++ break; ++ ++ rdesc = ring->rdesc; ++ rdesc_dma = ring->rdesc_dma; ++ ++ for (j = 0; j < ring->rdesc_count; j++) { ++ rdata = XGBE_GET_DESC_DATA(ring, j); ++ ++ rdata->rdesc = rdesc; ++ rdata->rdesc_dma = rdesc_dma; ++ ++ if (xgbe_map_rx_buffer(pdata, ring, rdata)) ++ break; ++ ++ rdesc++; ++ rdesc_dma += sizeof(struct xgbe_ring_desc); ++ } ++ ++ ring->cur = 0; ++ ring->dirty = 0; ++ ++ hw_if->rx_desc_init(channel); ++ } ++ ++ DBGPR("<--xgbe_wrapper_rx_descriptor_init\n"); ++} ++ ++static void xgbe_unmap_rdata(struct xgbe_prv_data *pdata, ++ struct xgbe_ring_data *rdata) ++{ ++ if (rdata->skb_dma) { ++ if (rdata->mapped_as_page) { ++ dma_unmap_page(pdata->dev, rdata->skb_dma, ++ rdata->skb_dma_len, DMA_TO_DEVICE); ++ } else { ++ dma_unmap_single(pdata->dev, rdata->skb_dma, ++ rdata->skb_dma_len, DMA_TO_DEVICE); ++ } ++ rdata->skb_dma = 0; ++ rdata->skb_dma_len = 0; ++ } ++ ++ if (rdata->skb) { ++ dev_kfree_skb_any(rdata->skb); ++ rdata->skb = NULL; ++ } ++ ++ if (rdata->rx.hdr.pa.pages) ++ put_page(rdata->rx.hdr.pa.pages); ++ ++ if (rdata->rx.hdr.pa_unmap.pages) { ++ dma_unmap_page(pdata->dev, rdata->rx.hdr.pa_unmap.pages_dma, ++ rdata->rx.hdr.pa_unmap.pages_len, ++ DMA_FROM_DEVICE); ++ put_page(rdata->rx.hdr.pa_unmap.pages); ++ } ++ ++ if (rdata->rx.buf.pa.pages) ++ put_page(rdata->rx.buf.pa.pages); ++ ++ if (rdata->rx.buf.pa_unmap.pages) { ++ dma_unmap_page(pdata->dev, rdata->rx.buf.pa_unmap.pages_dma, ++ rdata->rx.buf.pa_unmap.pages_len, ++ DMA_FROM_DEVICE); ++ put_page(rdata->rx.buf.pa_unmap.pages); ++ } ++ ++ memset(&rdata->tx, 0, sizeof(rdata->tx)); ++ memset(&rdata->rx, 0, sizeof(rdata->rx)); ++ ++ rdata->mapped_as_page = 0; ++ ++ if (rdata->state_saved) { ++ rdata->state_saved = 0; ++ rdata->state.incomplete = 0; ++ rdata->state.context_next = 0; ++ rdata->state.skb = NULL; ++ rdata->state.len = 0; ++ rdata->state.error = 0; ++ } ++} ++ ++static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_ring *ring = channel->tx_ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_packet_data *packet; ++ struct skb_frag_struct *frag; ++ dma_addr_t skb_dma; ++ unsigned int start_index, cur_index; ++ unsigned int offset, tso, vlan, datalen, len; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_map_tx_skb: cur = %d\n", ring->cur); ++ ++ offset = 0; ++ start_index = ring->cur; ++ cur_index = ring->cur; ++ ++ packet = &ring->packet_data; ++ packet->rdesc_count = 0; ++ packet->length = 0; ++ ++ tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ TSO_ENABLE); ++ vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ VLAN_CTAG); ++ ++ /* Save space for a context descriptor if needed */ ++ if ((tso && (packet->mss != ring->tx.cur_mss)) || ++ (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))) ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ ++ if (tso) { ++ DBGPR(" TSO packet\n"); ++ ++ /* Map the TSO header */ ++ skb_dma = dma_map_single(pdata->dev, skb->data, ++ packet->header_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(pdata->dev, skb_dma)) { ++ netdev_alert(pdata->netdev, "dma_map_single failed\n"); ++ goto err_out; ++ } ++ rdata->skb_dma = skb_dma; ++ rdata->skb_dma_len = packet->header_len; ++ ++ offset = packet->header_len; ++ ++ packet->length += packet->header_len; ++ ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ } ++ ++ /* Map the (remainder of the) packet */ ++ for (datalen = skb_headlen(skb) - offset; datalen; ) { ++ len = min_t(unsigned int, datalen, XGBE_TX_MAX_BUF_SIZE); ++ ++ skb_dma = dma_map_single(pdata->dev, skb->data + offset, len, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(pdata->dev, skb_dma)) { ++ netdev_alert(pdata->netdev, "dma_map_single failed\n"); ++ goto err_out; ++ } ++ rdata->skb_dma = skb_dma; ++ rdata->skb_dma_len = len; ++ DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n", ++ cur_index, skb_dma, len); ++ ++ datalen -= len; ++ offset += len; ++ ++ packet->length += len; ++ ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ } ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ DBGPR(" mapping frag %u\n", i); ++ ++ frag = &skb_shinfo(skb)->frags[i]; ++ offset = 0; ++ ++ for (datalen = skb_frag_size(frag); datalen; ) { ++ len = min_t(unsigned int, datalen, ++ XGBE_TX_MAX_BUF_SIZE); ++ ++ skb_dma = skb_frag_dma_map(pdata->dev, frag, offset, ++ len, DMA_TO_DEVICE); ++ if (dma_mapping_error(pdata->dev, skb_dma)) { ++ netdev_alert(pdata->netdev, ++ "skb_frag_dma_map failed\n"); ++ goto err_out; ++ } ++ rdata->skb_dma = skb_dma; ++ rdata->skb_dma_len = len; ++ rdata->mapped_as_page = 1; ++ DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n", ++ cur_index, skb_dma, len); ++ ++ datalen -= len; ++ offset += len; ++ ++ packet->length += len; ++ ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ } ++ } ++ ++ /* Save the skb address in the last entry. We always have some data ++ * that has been mapped so rdata is always advanced past the last ++ * piece of mapped data - use the entry pointed to by cur_index - 1. ++ */ ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index - 1); ++ rdata->skb = skb; ++ ++ /* Save the number of descriptor entries used */ ++ packet->rdesc_count = cur_index - start_index; ++ ++ DBGPR("<--xgbe_map_tx_skb: count=%u\n", packet->rdesc_count); ++ ++ return packet->rdesc_count; ++ ++err_out: ++ while (start_index < cur_index) { ++ rdata = XGBE_GET_DESC_DATA(ring, start_index++); ++ xgbe_unmap_rdata(pdata, rdata); ++ } ++ ++ DBGPR("<--xgbe_map_tx_skb: count=0\n"); ++ ++ return 0; ++} ++ ++void xgbe_a0_init_function_ptrs_desc(struct xgbe_desc_if *desc_if) ++{ ++ DBGPR("-->xgbe_a0_init_function_ptrs_desc\n"); ++ ++ desc_if->alloc_ring_resources = xgbe_alloc_ring_resources; ++ desc_if->free_ring_resources = xgbe_free_ring_resources; ++ desc_if->map_tx_skb = xgbe_map_tx_skb; ++ desc_if->map_rx_buffer = xgbe_map_rx_buffer; ++ desc_if->unmap_rdata = xgbe_unmap_rdata; ++ desc_if->wrapper_tx_desc_init = xgbe_wrapper_tx_descriptor_init; ++ desc_if->wrapper_rx_desc_init = xgbe_wrapper_rx_descriptor_init; ++ ++ DBGPR("<--xgbe_a0_init_function_ptrs_desc\n"); ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c +new file mode 100644 +index 0000000..2d88739 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c +@@ -0,0 +1,2930 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, ++ unsigned int usec) ++{ ++ unsigned long rate; ++ unsigned int ret; ++ ++ DBGPR("-->xgbe_usec_to_riwt\n"); ++ ++ rate = pdata->sysclk_rate; ++ ++ /* ++ * Convert the input usec value to the watchdog timer value. Each ++ * watchdog timer value is equivalent to 256 clock cycles. ++ * Calculate the required value as: ++ * ( usec * ( system_clock_mhz / 10^6 ) / 256 ++ */ ++ ret = (usec * (rate / 1000000)) / 256; ++ ++ DBGPR("<--xgbe_usec_to_riwt\n"); ++ ++ return ret; ++} ++ ++static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, ++ unsigned int riwt) ++{ ++ unsigned long rate; ++ unsigned int ret; ++ ++ DBGPR("-->xgbe_riwt_to_usec\n"); ++ ++ rate = pdata->sysclk_rate; ++ ++ /* ++ * Convert the input watchdog timer value to the usec value. Each ++ * watchdog timer value is equivalent to 256 clock cycles. ++ * Calculate the required value as: ++ * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) ++ */ ++ ret = (riwt * 256) / (rate / 1000000); ++ ++ DBGPR("<--xgbe_riwt_to_usec\n"); ++ ++ return ret; ++} ++ ++static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, ++ pdata->pblx8); ++ ++ return 0; ++} ++ ++static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) ++{ ++ return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); ++} ++ ++static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, ++ pdata->tx_pbl); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) ++{ ++ return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); ++} ++ ++static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, ++ pdata->rx_pbl); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, ++ pdata->tx_osp_mode); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pdata->rx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); ++ ++ return 0; ++} ++ ++static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); ++ ++ return 0; ++} ++ ++static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, ++ unsigned int val) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pdata->rx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); ++ ++ return 0; ++} ++ ++static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, ++ unsigned int val) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); ++ ++ return 0; ++} ++ ++static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, ++ pdata->rx_riwt); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) ++{ ++ return 0; ++} ++ ++static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, ++ pdata->rx_buf_size); ++ } ++} ++ ++static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); ++ } ++} ++ ++static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); ++ } ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); ++} ++ ++static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, ++ unsigned int index, unsigned int val) ++{ ++ unsigned int wait; ++ int ret = 0; ++ ++ mutex_lock(&pdata->rss_mutex); ++ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { ++ ret = -EBUSY; ++ goto unlock; ++ } ++ ++ XGMAC_IOWRITE(pdata, MAC_RSSDR, val); ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); ++ ++ wait = 1000; ++ while (wait--) { ++ if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) ++ goto unlock; ++ ++ usleep_range(1000, 1500); ++ } ++ ++ ret = -EBUSY; ++ ++unlock: ++ mutex_unlock(&pdata->rss_mutex); ++ ++ return ret; ++} ++ ++static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) ++{ ++ unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); ++ unsigned int *key = (unsigned int *)&pdata->rss_key; ++ int ret; ++ ++ while (key_regs--) { ++ ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, ++ key_regs, *key++); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) ++{ ++ unsigned int i; ++ int ret; ++ ++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { ++ ret = xgbe_write_rss_reg(pdata, ++ XGBE_RSS_LOOKUP_TABLE_TYPE, i, ++ pdata->rss_table[i]); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) ++{ ++ memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); ++ ++ return xgbe_write_rss_hash_key(pdata); ++} ++ ++static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, ++ const u32 *table) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) ++ XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); ++ ++ return xgbe_write_rss_lookup_table(pdata); ++} ++ ++static int xgbe_enable_rss(struct xgbe_prv_data *pdata) ++{ ++ int ret; ++ ++ if (!pdata->hw_feat.rss) ++ return -EOPNOTSUPP; ++ ++ /* Program the hash key */ ++ ret = xgbe_write_rss_hash_key(pdata); ++ if (ret) ++ return ret; ++ ++ /* Program the lookup table */ ++ ret = xgbe_write_rss_lookup_table(pdata); ++ if (ret) ++ return ret; ++ ++ /* Set the RSS options */ ++ XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); ++ ++ /* Enable RSS */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); ++ ++ return 0; ++} ++ ++static int xgbe_disable_rss(struct xgbe_prv_data *pdata) ++{ ++ if (!pdata->hw_feat.rss) ++ return -EOPNOTSUPP; ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); ++ ++ return 0; ++} ++ ++static void xgbe_config_rss(struct xgbe_prv_data *pdata) ++{ ++ int ret; ++ ++ if (!pdata->hw_feat.rss) ++ return; ++ ++ if (pdata->netdev->features & NETIF_F_RXHASH) ++ ret = xgbe_enable_rss(pdata); ++ else ++ ret = xgbe_disable_rss(pdata); ++ ++ if (ret) ++ netdev_err(pdata->netdev, ++ "error configuring RSS, RSS disabled\n"); ++} ++ ++static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ unsigned int max_q_count, q_count; ++ unsigned int reg, reg_val; ++ unsigned int i; ++ ++ /* Clear MTL flow control */ ++ for (i = 0; i < pdata->rx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); ++ ++ /* Clear MAC flow control */ ++ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; ++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ reg = MAC_Q0TFCR; ++ for (i = 0; i < q_count; i++) { ++ reg_val = XGMAC_IOREAD(pdata, reg); ++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); ++ XGMAC_IOWRITE(pdata, reg, reg_val); ++ ++ reg += MAC_QTFCR_INC; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ unsigned int max_q_count, q_count; ++ unsigned int reg, reg_val; ++ unsigned int i; ++ ++ /* Set MTL flow control */ ++ for (i = 0; i < pdata->rx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); ++ ++ /* Set MAC flow control */ ++ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; ++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ reg = MAC_Q0TFCR; ++ for (i = 0; i < q_count; i++) { ++ reg_val = XGMAC_IOREAD(pdata, reg); ++ ++ /* Enable transmit flow control */ ++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); ++ /* Set pause time */ ++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); ++ ++ XGMAC_IOWRITE(pdata, reg, reg_val); ++ ++ reg += MAC_QTFCR_INC; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); ++ ++ return 0; ++} ++ ++static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); ++ ++ return 0; ++} ++ ++static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ struct ieee_pfc *pfc = pdata->pfc; ++ ++ if (pdata->tx_pause || (pfc && pfc->pfc_en)) ++ xgbe_enable_tx_flow_control(pdata); ++ else ++ xgbe_disable_tx_flow_control(pdata); ++ ++ return 0; ++} ++ ++static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) ++{ ++ struct ieee_pfc *pfc = pdata->pfc; ++ ++ if (pdata->rx_pause || (pfc && pfc->pfc_en)) ++ xgbe_enable_rx_flow_control(pdata); ++ else ++ xgbe_disable_rx_flow_control(pdata); ++ ++ return 0; ++} ++ ++static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) ++{ ++ struct ieee_pfc *pfc = pdata->pfc; ++ ++ xgbe_config_tx_flow_control(pdata); ++ xgbe_config_rx_flow_control(pdata); ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, ++ (pfc && pfc->pfc_en) ? 1 : 0); ++} ++ ++static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int dma_ch_isr, dma_ch_ier; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ /* Clear all the interrupts which are set */ ++ dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); ++ ++ /* Clear all interrupt enable bits */ ++ dma_ch_ier = 0; ++ ++ /* Enable following interrupts ++ * NIE - Normal Interrupt Summary Enable ++ * AIE - Abnormal Interrupt Summary Enable ++ * FBEE - Fatal Bus Error Enable ++ */ ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); ++ ++ if (channel->tx_ring) { ++ /* Enable the following Tx interrupts ++ * TIE - Transmit Interrupt Enable (unless using ++ * per channel interrupts) ++ */ ++ if (!pdata->per_channel_irq) ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); ++ } ++ if (channel->rx_ring) { ++ /* Enable following Rx interrupts ++ * RBUE - Receive Buffer Unavailable Enable ++ * RIE - Receive Interrupt Enable (unless using ++ * per channel interrupts) ++ */ ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); ++ if (!pdata->per_channel_irq) ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); ++ } ++ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); ++ } ++} ++ ++static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) ++{ ++ unsigned int mtl_q_isr; ++ unsigned int q_count, i; ++ ++ q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); ++ for (i = 0; i < q_count; i++) { ++ /* Clear all the interrupts which are set */ ++ mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); ++ XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); ++ ++ /* No MTL interrupts to be enabled */ ++ XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); ++ } ++} ++ ++static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) ++{ ++ unsigned int mac_ier = 0; ++ ++ /* Enable Timestamp interrupt */ ++ XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); ++ ++ XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); ++ ++ /* Enable all counter interrupts */ ++ XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); ++ XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); ++} ++ ++static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) ++{ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3) ++ return 0; ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); ++ ++ return 0; ++} ++ ++static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) ++{ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2) ++ return 0; ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); ++ ++ return 0; ++} ++ ++static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) ++{ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0) ++ return 0; ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); ++ ++ return 0; ++} ++ ++static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, ++ unsigned int enable) ++{ ++ unsigned int val = enable ? 1 : 0; ++ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) ++ return 0; ++ ++ DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving"); ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); ++ ++ return 0; ++} ++ ++static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, ++ unsigned int enable) ++{ ++ unsigned int val = enable ? 1 : 0; ++ ++ if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) ++ return 0; ++ ++ DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving"); ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); ++ ++ return 0; ++} ++ ++static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, ++ struct netdev_hw_addr *ha, unsigned int *mac_reg) ++{ ++ unsigned int mac_addr_hi, mac_addr_lo; ++ u8 *mac_addr; ++ ++ mac_addr_lo = 0; ++ mac_addr_hi = 0; ++ ++ if (ha) { ++ mac_addr = (u8 *)&mac_addr_lo; ++ mac_addr[0] = ha->addr[0]; ++ mac_addr[1] = ha->addr[1]; ++ mac_addr[2] = ha->addr[2]; ++ mac_addr[3] = ha->addr[3]; ++ mac_addr = (u8 *)&mac_addr_hi; ++ mac_addr[0] = ha->addr[4]; ++ mac_addr[1] = ha->addr[5]; ++ ++ DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr, ++ *mac_reg); ++ ++ XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); ++ } ++ ++ XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); ++ *mac_reg += MAC_MACA_INC; ++ XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); ++ *mac_reg += MAC_MACA_INC; ++} ++ ++static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) ++{ ++ struct net_device *netdev = pdata->netdev; ++ struct netdev_hw_addr *ha; ++ unsigned int mac_reg; ++ unsigned int addn_macs; ++ ++ mac_reg = MAC_MACA1HR; ++ addn_macs = pdata->hw_feat.addn_mac; ++ ++ if (netdev_uc_count(netdev) > addn_macs) { ++ xgbe_set_promiscuous_mode(pdata, 1); ++ } else { ++ netdev_for_each_uc_addr(ha, netdev) { ++ xgbe_set_mac_reg(pdata, ha, &mac_reg); ++ addn_macs--; ++ } ++ ++ if (netdev_mc_count(netdev) > addn_macs) { ++ xgbe_set_all_multicast_mode(pdata, 1); ++ } else { ++ netdev_for_each_mc_addr(ha, netdev) { ++ xgbe_set_mac_reg(pdata, ha, &mac_reg); ++ addn_macs--; ++ } ++ } ++ } ++ ++ /* Clear remaining additional MAC address entries */ ++ while (addn_macs--) ++ xgbe_set_mac_reg(pdata, NULL, &mac_reg); ++} ++ ++static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) ++{ ++ struct net_device *netdev = pdata->netdev; ++ struct netdev_hw_addr *ha; ++ unsigned int hash_reg; ++ unsigned int hash_table_shift, hash_table_count; ++ u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; ++ u32 crc; ++ unsigned int i; ++ ++ hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); ++ hash_table_count = pdata->hw_feat.hash_table_size / 32; ++ memset(hash_table, 0, sizeof(hash_table)); ++ ++ /* Build the MAC Hash Table register values */ ++ netdev_for_each_uc_addr(ha, netdev) { ++ crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); ++ crc >>= hash_table_shift; ++ hash_table[crc >> 5] |= (1 << (crc & 0x1f)); ++ } ++ ++ netdev_for_each_mc_addr(ha, netdev) { ++ crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); ++ crc >>= hash_table_shift; ++ hash_table[crc >> 5] |= (1 << (crc & 0x1f)); ++ } ++ ++ /* Set the MAC Hash Table registers */ ++ hash_reg = MAC_HTR0; ++ for (i = 0; i < hash_table_count; i++) { ++ XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); ++ hash_reg += MAC_HTR_INC; ++ } ++} ++ ++static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) ++{ ++ if (pdata->hw_feat.hash_table_size) ++ xgbe_set_mac_hash_table(pdata); ++ else ++ xgbe_set_mac_addn_addrs(pdata); ++ ++ return 0; ++} ++ ++static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) ++{ ++ unsigned int mac_addr_hi, mac_addr_lo; ++ ++ mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); ++ mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | ++ (addr[1] << 8) | (addr[0] << 0); ++ ++ XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); ++ XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); ++ ++ return 0; ++} ++ ++static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, ++ int mmd_reg) ++{ ++ unsigned int mmd_address; ++ int mmd_data; ++ ++ if (mmd_reg & MII_ADDR_C45) ++ mmd_address = mmd_reg & ~MII_ADDR_C45; ++ else ++ mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); ++ ++ /* The PCS implementation has reversed the devices in ++ * package registers so we need to change 05 to 06 and ++ * 06 to 05 if being read (these registers are readonly ++ * so no need to do this in the write function) ++ */ ++ if ((mmd_address & 0xffff) == 0x05) ++ mmd_address = (mmd_address & ~0xffff) | 0x06; ++ else if ((mmd_address & 0xffff) == 0x06) ++ mmd_address = (mmd_address & ~0xffff) | 0x05; ++ ++ /* The PCS registers are accessed using mmio. The underlying APB3 ++ * management interface uses indirect addressing to access the MMD ++ * register sets. This requires accessing of the PCS register in two ++ * phases, an address phase and a data phase. ++ * ++ * The mmio interface is based on 32-bit offsets and values. All ++ * register offsets must therefore be adjusted by left shifting the ++ * offset 2 bits and reading 32 bits of data. ++ */ ++ mutex_lock(&pdata->xpcs_mutex); ++ XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); ++ mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); ++ mutex_unlock(&pdata->xpcs_mutex); ++ ++ return mmd_data; ++} ++ ++static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, ++ int mmd_reg, int mmd_data) ++{ ++ unsigned int mmd_address; ++ ++ if (mmd_reg & MII_ADDR_C45) ++ mmd_address = mmd_reg & ~MII_ADDR_C45; ++ else ++ mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); ++ ++ /* If the PCS is changing modes, match the MAC speed to it */ ++ if (((mmd_address >> 16) == MDIO_MMD_PCS) && ++ ((mmd_address & 0xffff) == MDIO_CTRL2)) { ++ struct phy_device *phydev = pdata->phydev; ++ ++ if (mmd_data & MDIO_PCS_CTRL2_TYPE) { ++ /* KX mode */ ++ if (phydev->supported & SUPPORTED_1000baseKX_Full) ++ xgbe_set_gmii_speed(pdata); ++ else ++ xgbe_set_gmii_2500_speed(pdata); ++ } else { ++ /* KR mode */ ++ xgbe_set_xgmii_speed(pdata); ++ } ++ } ++ ++ /* The PCS registers are accessed using mmio. The underlying APB3 ++ * management interface uses indirect addressing to access the MMD ++ * register sets. This requires accessing of the PCS register in two ++ * phases, an address phase and a data phase. ++ * ++ * The mmio interface is based on 32-bit offsets and values. All ++ * register offsets must therefore be adjusted by left shifting the ++ * offset 2 bits and reading 32 bits of data. ++ */ ++ mutex_lock(&pdata->xpcs_mutex); ++ XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); ++ XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); ++ mutex_unlock(&pdata->xpcs_mutex); ++} ++ ++static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) ++{ ++ return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); ++} ++ ++static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) ++{ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); ++ ++ return 0; ++} ++ ++static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) ++{ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); ++ ++ return 0; ++} ++ ++static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) ++{ ++ /* Put the VLAN tag in the Rx descriptor */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); ++ ++ /* Don't check the VLAN type */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); ++ ++ /* Check only C-TAG (0x8100) packets */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); ++ ++ /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); ++ ++ /* Enable VLAN tag stripping */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); ++ ++ return 0; ++} ++ ++static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) ++{ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); ++ ++ return 0; ++} ++ ++static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) ++{ ++ /* Enable VLAN filtering */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); ++ ++ /* Enable VLAN Hash Table filtering */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); ++ ++ /* Disable VLAN tag inverse matching */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); ++ ++ /* Only filter on the lower 12-bits of the VLAN tag */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); ++ ++ /* In order for the VLAN Hash Table filtering to be effective, ++ * the VLAN tag identifier in the VLAN Tag Register must not ++ * be zero. Set the VLAN tag identifier to "1" to enable the ++ * VLAN Hash Table filtering. This implies that a VLAN tag of ++ * 1 will always pass filtering. ++ */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); ++ ++ return 0; ++} ++ ++static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) ++{ ++ /* Disable VLAN filtering */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); ++ ++ return 0; ++} ++ ++#ifndef CRCPOLY_LE ++#define CRCPOLY_LE 0xedb88320 ++#endif ++static u32 xgbe_vid_crc32_le(__le16 vid_le) ++{ ++ u32 poly = CRCPOLY_LE; ++ u32 crc = ~0; ++ u32 temp = 0; ++ unsigned char *data = (unsigned char *)&vid_le; ++ unsigned char data_byte = 0; ++ int i, bits; ++ ++ bits = get_bitmask_order(VLAN_VID_MASK); ++ for (i = 0; i < bits; i++) { ++ if ((i % 8) == 0) ++ data_byte = data[i / 8]; ++ ++ temp = ((crc & 1) ^ data_byte) & 1; ++ crc >>= 1; ++ data_byte >>= 1; ++ ++ if (temp) ++ crc ^= poly; ++ } ++ ++ return crc; ++} ++ ++static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) ++{ ++ u32 crc; ++ u16 vid; ++ __le16 vid_le; ++ u16 vlan_hash_table = 0; ++ ++ /* Generate the VLAN Hash Table value */ ++ for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { ++ /* Get the CRC32 value of the VLAN ID */ ++ vid_le = cpu_to_le16(vid); ++ crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; ++ ++ vlan_hash_table |= (1 << crc); ++ } ++ ++ /* Set the VLAN Hash Table filtering register */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); ++ ++ return 0; ++} ++ ++static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) ++{ ++ struct xgbe_ring_desc *rdesc = rdata->rdesc; ++ ++ /* Reset the Tx descriptor ++ * Set buffer 1 (lo) address to zero ++ * Set buffer 1 (hi) address to zero ++ * Reset all other control bits (IC, TTSE, B2L & B1L) ++ * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) ++ */ ++ rdesc->desc0 = 0; ++ rdesc->desc1 = 0; ++ rdesc->desc2 = 0; ++ rdesc->desc3 = 0; ++ ++ /* Make sure ownership is written to the descriptor */ ++ wmb(); ++} ++ ++static void xgbe_tx_desc_init(struct xgbe_channel *channel) ++{ ++ struct xgbe_ring *ring = channel->tx_ring; ++ struct xgbe_ring_data *rdata; ++ int i; ++ int start_index = ring->cur; ++ ++ DBGPR("-->tx_desc_init\n"); ++ ++ /* Initialze all descriptors */ ++ for (i = 0; i < ring->rdesc_count; i++) { ++ rdata = XGBE_GET_DESC_DATA(ring, i); ++ ++ /* Initialize Tx descriptor */ ++ xgbe_tx_desc_reset(rdata); ++ } ++ ++ /* Update the total number of Tx descriptors */ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); ++ ++ /* Update the starting address of descriptor ring */ ++ rdata = XGBE_GET_DESC_DATA(ring, start_index); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, ++ upper_32_bits(rdata->rdesc_dma)); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, ++ lower_32_bits(rdata->rdesc_dma)); ++ ++ DBGPR("<--tx_desc_init\n"); ++} ++ ++static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata) ++{ ++ struct xgbe_ring_desc *rdesc = rdata->rdesc; ++ ++ /* Reset the Rx descriptor ++ * Set buffer 1 (lo) address to header dma address (lo) ++ * Set buffer 1 (hi) address to header dma address (hi) ++ * Set buffer 2 (lo) address to buffer dma address (lo) ++ * Set buffer 2 (hi) address to buffer dma address (hi) and ++ * set control bits OWN and INTE ++ */ ++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma)); ++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma)); ++ rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma)); ++ rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma)); ++ ++ XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, ++ rdata->interrupt ? 1 : 0); ++ ++ /* Since the Rx DMA engine is likely running, make sure everything ++ * is written to the descriptor(s) before setting the OWN bit ++ * for the descriptor ++ */ ++ wmb(); ++ ++ XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); ++ ++ /* Make sure ownership is written to the descriptor */ ++ wmb(); ++} ++ ++static void xgbe_rx_desc_init(struct xgbe_channel *channel) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_ring *ring = channel->rx_ring; ++ struct xgbe_ring_data *rdata; ++ unsigned int start_index = ring->cur; ++ unsigned int rx_coalesce, rx_frames; ++ unsigned int i; ++ ++ DBGPR("-->rx_desc_init\n"); ++ ++ rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0; ++ rx_frames = pdata->rx_frames; ++ ++ /* Initialize all descriptors */ ++ for (i = 0; i < ring->rdesc_count; i++) { ++ rdata = XGBE_GET_DESC_DATA(ring, i); ++ ++ /* Set interrupt on completion bit as appropriate */ ++ if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) ++ rdata->interrupt = 0; ++ else ++ rdata->interrupt = 1; ++ ++ /* Initialize Rx descriptor */ ++ xgbe_rx_desc_reset(rdata); ++ } ++ ++ /* Update the total number of Rx descriptors */ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); ++ ++ /* Update the starting address of descriptor ring */ ++ rdata = XGBE_GET_DESC_DATA(ring, start_index); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, ++ upper_32_bits(rdata->rdesc_dma)); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, ++ lower_32_bits(rdata->rdesc_dma)); ++ ++ /* Update the Rx Descriptor Tail Pointer */ ++ rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, ++ lower_32_bits(rdata->rdesc_dma)); ++ ++ DBGPR("<--rx_desc_init\n"); ++} ++ ++static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, ++ unsigned int addend) ++{ ++ /* Set the addend register value and tell the device */ ++ XGMAC_IOWRITE(pdata, MAC_TSAR, addend); ++ XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); ++ ++ /* Wait for addend update to complete */ ++ while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) ++ udelay(5); ++} ++ ++static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, ++ unsigned int nsec) ++{ ++ /* Set the time values and tell the device */ ++ XGMAC_IOWRITE(pdata, MAC_STSUR, sec); ++ XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); ++ XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); ++ ++ /* Wait for time update to complete */ ++ while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) ++ udelay(5); ++} ++ ++static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) ++{ ++ u64 nsec; ++ ++ nsec = XGMAC_IOREAD(pdata, MAC_STSR); ++ nsec *= NSEC_PER_SEC; ++ nsec += XGMAC_IOREAD(pdata, MAC_STNR); ++ ++ return nsec; ++} ++ ++static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) ++{ ++ unsigned int tx_snr; ++ u64 nsec; ++ ++ tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); ++ if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) ++ return 0; ++ ++ nsec = XGMAC_IOREAD(pdata, MAC_TXSSR); ++ nsec *= NSEC_PER_SEC; ++ nsec += tx_snr; ++ ++ return nsec; ++} ++ ++static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, ++ struct xgbe_ring_desc *rdesc) ++{ ++ u64 nsec; ++ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && ++ !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { ++ nsec = le32_to_cpu(rdesc->desc1); ++ nsec <<= 32; ++ nsec |= le32_to_cpu(rdesc->desc0); ++ if (nsec != 0xffffffffffffffffULL) { ++ packet->rx_tstamp = nsec; ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ RX_TSTAMP, 1); ++ } ++ } ++} ++ ++static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, ++ unsigned int mac_tscr) ++{ ++ /* Set one nano-second accuracy */ ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); ++ ++ /* Set fine timestamp update */ ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); ++ ++ /* Overwrite earlier timestamps */ ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); ++ ++ XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); ++ ++ /* Exit if timestamping is not enabled */ ++ if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) ++ return 0; ++ ++ /* Initialize time registers */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); ++ XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); ++ xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); ++ xgbe_set_tstamp_time(pdata, 0, 0); ++ ++ /* Initialize the timecounter */ ++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, ++ ktime_to_ns(ktime_get_real())); ++ ++ return 0; ++} ++ ++static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) ++{ ++ struct ieee_ets *ets = pdata->ets; ++ unsigned int total_weight, min_weight, weight; ++ unsigned int i; ++ ++ if (!ets) ++ return; ++ ++ /* Set Tx to deficit weighted round robin scheduling algorithm (when ++ * traffic class is using ETS algorithm) ++ */ ++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); ++ ++ /* Set Traffic Class algorithms */ ++ total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; ++ min_weight = total_weight / 100; ++ if (!min_weight) ++ min_weight = 1; ++ ++ for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { ++ switch (ets->tc_tsa[i]) { ++ case IEEE_8021QAZ_TSA_STRICT: ++ DBGPR(" TC%u using SP\n", i); ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, ++ MTL_TSA_SP); ++ break; ++ case IEEE_8021QAZ_TSA_ETS: ++ weight = total_weight * ets->tc_tx_bw[i] / 100; ++ weight = clamp(weight, min_weight, total_weight); ++ ++ DBGPR(" TC%u using DWRR (weight %u)\n", i, weight); ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, ++ MTL_TSA_ETS); ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, ++ weight); ++ break; ++ } ++ } ++} ++ ++static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) ++{ ++ struct ieee_pfc *pfc = pdata->pfc; ++ struct ieee_ets *ets = pdata->ets; ++ unsigned int mask, reg, reg_val; ++ unsigned int tc, prio; ++ ++ if (!pfc || !ets) ++ return; ++ ++ for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) { ++ mask = 0; ++ for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { ++ if ((pfc->pfc_en & (1 << prio)) && ++ (ets->prio_tc[prio] == tc)) ++ mask |= (1 << prio); ++ } ++ mask &= 0xff; ++ ++ DBGPR(" TC%u PFC mask=%#x\n", tc, mask); ++ reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG)); ++ reg_val = XGMAC_IOREAD(pdata, reg); ++ ++ reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3)); ++ reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3)); ++ ++ XGMAC_IOWRITE(pdata, reg, reg_val); ++ } ++ ++ xgbe_config_flow_control(pdata); ++} ++ ++static void xgbe_tx_start_xmit(struct xgbe_channel *channel, ++ struct xgbe_ring *ring) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_ring_data *rdata; ++ ++ /* Issue a poll command to Tx DMA by writing address ++ * of next immediate free descriptor */ ++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, ++ lower_32_bits(rdata->rdesc_dma)); ++ ++ /* Start the Tx coalescing timer */ ++ if (pdata->tx_usecs && !channel->tx_timer_active) { ++ channel->tx_timer_active = 1; ++ hrtimer_start(&channel->tx_timer, ++ ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC), ++ HRTIMER_MODE_REL); ++ } ++ ++ ring->tx.xmit_more = 0; ++} ++ ++static void xgbe_dev_xmit(struct xgbe_channel *channel) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_ring *ring = channel->tx_ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_ring_desc *rdesc; ++ struct xgbe_packet_data *packet = &ring->packet_data; ++ unsigned int csum, tso, vlan; ++ unsigned int tso_context, vlan_context; ++ unsigned int tx_set_ic; ++ int start_index = ring->cur; ++ int cur_index = ring->cur; ++ int i; ++ ++ DBGPR("-->xgbe_dev_xmit\n"); ++ ++ csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ CSUM_ENABLE); ++ tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ TSO_ENABLE); ++ vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ VLAN_CTAG); ++ ++ if (tso && (packet->mss != ring->tx.cur_mss)) ++ tso_context = 1; ++ else ++ tso_context = 0; ++ ++ if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) ++ vlan_context = 1; ++ else ++ vlan_context = 0; ++ ++ /* Determine if an interrupt should be generated for this Tx: ++ * Interrupt: ++ * - Tx frame count exceeds the frame count setting ++ * - Addition of Tx frame count to the frame count since the ++ * last interrupt was set exceeds the frame count setting ++ * No interrupt: ++ * - No frame count setting specified (ethtool -C ethX tx-frames 0) ++ * - Addition of Tx frame count to the frame count since the ++ * last interrupt was set does not exceed the frame count setting ++ */ ++ ring->coalesce_count += packet->tx_packets; ++ if (!pdata->tx_frames) ++ tx_set_ic = 0; ++ else if (packet->tx_packets > pdata->tx_frames) ++ tx_set_ic = 1; ++ else if ((ring->coalesce_count % pdata->tx_frames) < ++ packet->tx_packets) ++ tx_set_ic = 1; ++ else ++ tx_set_ic = 0; ++ ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ rdesc = rdata->rdesc; ++ ++ /* Create a context descriptor if this is a TSO packet */ ++ if (tso_context || vlan_context) { ++ if (tso_context) { ++ DBGPR(" TSO context descriptor, mss=%u\n", ++ packet->mss); ++ ++ /* Set the MSS size */ ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, ++ MSS, packet->mss); ++ ++ /* Mark it as a CONTEXT descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, ++ CTXT, 1); ++ ++ /* Indicate this descriptor contains the MSS */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, ++ TCMSSV, 1); ++ ++ ring->tx.cur_mss = packet->mss; ++ } ++ ++ if (vlan_context) { ++ DBGPR(" VLAN context descriptor, ctag=%u\n", ++ packet->vlan_ctag); ++ ++ /* Mark it as a CONTEXT descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, ++ CTXT, 1); ++ ++ /* Set the VLAN tag */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, ++ VT, packet->vlan_ctag); ++ ++ /* Indicate this descriptor contains the VLAN tag */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, ++ VLTV, 1); ++ ++ ring->tx.cur_vlan_ctag = packet->vlan_ctag; ++ } ++ ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ rdesc = rdata->rdesc; ++ } ++ ++ /* Update buffer address (for TSO this is the header) */ ++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); ++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); ++ ++ /* Update the buffer length */ ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, ++ rdata->skb_dma_len); ++ ++ /* VLAN tag insertion check */ ++ if (vlan) ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, ++ TX_NORMAL_DESC2_VLAN_INSERT); ++ ++ /* Timestamp enablement check */ ++ if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); ++ ++ /* Mark it as First Descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); ++ ++ /* Mark it as a NORMAL descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); ++ ++ /* Set OWN bit if not the first descriptor */ ++ if (cur_index != start_index) ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); ++ ++ if (tso) { ++ /* Enable TSO */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, ++ packet->tcp_payload_len); ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, ++ packet->tcp_header_len / 4); ++ } else { ++ /* Enable CRC and Pad Insertion */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); ++ ++ /* Enable HW CSUM */ ++ if (csum) ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, ++ CIC, 0x3); ++ ++ /* Set the total length to be transmitted */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, ++ packet->length); ++ } ++ ++ for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { ++ cur_index++; ++ rdata = XGBE_GET_DESC_DATA(ring, cur_index); ++ rdesc = rdata->rdesc; ++ ++ /* Update buffer address */ ++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); ++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); ++ ++ /* Update the buffer length */ ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, ++ rdata->skb_dma_len); ++ ++ /* Set OWN bit */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); ++ ++ /* Mark it as NORMAL descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); ++ ++ /* Enable HW CSUM */ ++ if (csum) ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, ++ CIC, 0x3); ++ } ++ ++ /* Set LAST bit for the last descriptor */ ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); ++ ++ /* Set IC bit based on Tx coalescing settings */ ++ if (tx_set_ic) ++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); ++ ++ /* Save the Tx info to report back during cleanup */ ++ rdata->tx.packets = packet->tx_packets; ++ rdata->tx.bytes = packet->tx_bytes; ++ ++ /* In case the Tx DMA engine is running, make sure everything ++ * is written to the descriptor(s) before setting the OWN bit ++ * for the first descriptor ++ */ ++ wmb(); ++ ++ /* Set OWN bit for the first descriptor */ ++ rdata = XGBE_GET_DESC_DATA(ring, start_index); ++ rdesc = rdata->rdesc; ++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); ++ ++#ifdef XGMAC_ENABLE_TX_DESC_DUMP ++ xgbe_a0_dump_tx_desc(ring, start_index, packet->rdesc_count, 1); ++#endif ++ ++ /* Make sure ownership is written to the descriptor */ ++ wmb(); ++ ++ ring->cur = cur_index + 1; ++ if (!packet->skb->xmit_more || ++ netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, ++ channel->queue_index))) ++ xgbe_tx_start_xmit(channel, ring); ++ else ++ ring->tx.xmit_more = 1; ++ ++ DBGPR(" %s: descriptors %u to %u written\n", ++ channel->name, start_index & (ring->rdesc_count - 1), ++ (ring->cur - 1) & (ring->rdesc_count - 1)); ++ ++ DBGPR("<--xgbe_dev_xmit\n"); ++} ++ ++static int xgbe_dev_read(struct xgbe_channel *channel) ++{ ++ struct xgbe_ring *ring = channel->rx_ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_ring_desc *rdesc; ++ struct xgbe_packet_data *packet = &ring->packet_data; ++ struct net_device *netdev = channel->pdata->netdev; ++ unsigned int err, etlt, l34t; ++ ++ DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); ++ ++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); ++ rdesc = rdata->rdesc; ++ ++ /* Check for data availability */ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) ++ return 1; ++ ++ /* Make sure descriptor fields are read after reading the OWN bit */ ++ rmb(); ++ ++#ifdef XGMAC_ENABLE_RX_DESC_DUMP ++ xgbe_a0_dump_rx_desc(ring, rdesc, ring->cur); ++#endif ++ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { ++ /* Timestamp Context Descriptor */ ++ xgbe_get_rx_tstamp(packet, rdesc); ++ ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ CONTEXT, 1); ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ CONTEXT_NEXT, 0); ++ return 0; ++ } ++ ++ /* Normal Descriptor, be sure Context Descriptor bit is off */ ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); ++ ++ /* Indicate if a Context Descriptor is next */ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ CONTEXT_NEXT, 1); ++ ++ /* Get the header length */ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) ++ rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, ++ RX_NORMAL_DESC2, HL); ++ ++ /* Get the RSS hash */ ++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ RSS_HASH, 1); ++ ++ packet->rss_hash = le32_to_cpu(rdesc->desc1); ++ ++ l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); ++ switch (l34t) { ++ case RX_DESC3_L34T_IPV4_TCP: ++ case RX_DESC3_L34T_IPV4_UDP: ++ case RX_DESC3_L34T_IPV6_TCP: ++ case RX_DESC3_L34T_IPV6_UDP: ++ packet->rss_hash_type = PKT_HASH_TYPE_L4; ++ break; ++ default: ++ packet->rss_hash_type = PKT_HASH_TYPE_L3; ++ } ++ } ++ ++ /* Get the packet length */ ++ rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); ++ ++ if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { ++ /* Not all the data has been transferred for this packet */ ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ INCOMPLETE, 1); ++ return 0; ++ } ++ ++ /* This is the last of the data for this packet */ ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ INCOMPLETE, 0); ++ ++ /* Set checksum done indicator as appropriate */ ++ if (channel->pdata->netdev->features & NETIF_F_RXCSUM) ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ CSUM_DONE, 1); ++ ++ /* Check for errors (only valid in last descriptor) */ ++ err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); ++ etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); ++ DBGPR(" err=%u, etlt=%#x\n", err, etlt); ++ ++ if (!err || !etlt) { ++ /* No error if err is 0 or etlt is 0 */ ++ if ((etlt == 0x09) && ++ (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ VLAN_CTAG, 1); ++ packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, ++ RX_NORMAL_DESC0, ++ OVT); ++ DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag); ++ } ++ } else { ++ if ((etlt == 0x05) || (etlt == 0x06)) ++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, ++ CSUM_DONE, 0); ++ else ++ XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, ++ FRAME, 1); ++ } ++ ++ DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, ++ ring->cur & (ring->rdesc_count - 1), ring->cur); ++ ++ return 0; ++} ++ ++static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) ++{ ++ /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ ++ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); ++} ++ ++static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) ++{ ++ /* Rx and Tx share LD bit, so check TDES3.LD bit */ ++ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); ++} ++ ++static int xgbe_enable_int(struct xgbe_channel *channel, ++ enum xgbe_int int_id) ++{ ++ unsigned int dma_ch_ier; ++ ++ dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); ++ ++ switch (int_id) { ++ case XGMAC_INT_DMA_CH_SR_TI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TPS: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TBU: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RBU: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RPS: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TI_RI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); ++ break; ++ case XGMAC_INT_DMA_CH_SR_FBE: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); ++ break; ++ case XGMAC_INT_DMA_ALL: ++ dma_ch_ier |= channel->saved_ier; ++ break; ++ default: ++ return -1; ++ } ++ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); ++ ++ return 0; ++} ++ ++static int xgbe_disable_int(struct xgbe_channel *channel, ++ enum xgbe_int int_id) ++{ ++ unsigned int dma_ch_ier; ++ ++ dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); ++ ++ switch (int_id) { ++ case XGMAC_INT_DMA_CH_SR_TI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TPS: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TBU: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RBU: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_RPS: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_TI_RI: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); ++ break; ++ case XGMAC_INT_DMA_CH_SR_FBE: ++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); ++ break; ++ case XGMAC_INT_DMA_ALL: ++ channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; ++ dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; ++ break; ++ default: ++ return -1; ++ } ++ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); ++ ++ return 0; ++} ++ ++static int xgbe_exit(struct xgbe_prv_data *pdata) ++{ ++ unsigned int count = 2000; ++ ++ DBGPR("-->xgbe_exit\n"); ++ ++ /* Issue a software reset */ ++ XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); ++ usleep_range(10, 15); ++ ++ /* Poll Until Poll Condition */ ++ while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) ++ usleep_range(500, 600); ++ ++ if (!count) ++ return -EBUSY; ++ ++ DBGPR("<--xgbe_exit\n"); ++ ++ return 0; ++} ++ ++static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) ++{ ++ unsigned int i, count; ++ ++ if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) ++ return 0; ++ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); ++ ++ /* Poll Until Poll Condition */ ++ for (i = 0; i < pdata->tx_q_count; i++) { ++ count = 2000; ++ while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i, ++ MTL_Q_TQOMR, FTQ)) ++ usleep_range(500, 600); ++ ++ if (!count) ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) ++{ ++ /* Set enhanced addressing mode */ ++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); ++ ++ /* Set the System Bus mode */ ++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); ++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); ++} ++ ++static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) ++{ ++ unsigned int arcache, awcache; ++ ++ arcache = 0; ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); ++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); ++ XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); ++ ++ awcache = 0; ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); ++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); ++ XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); ++} ++ ++static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) ++{ ++ unsigned int i; ++ ++ /* Set Tx to weighted round robin scheduling algorithm */ ++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); ++ ++ /* Set Tx traffic classes to use WRR algorithm with equal weights */ ++ for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, ++ MTL_TSA_ETS); ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); ++ } ++ ++ /* Set Rx to strict priority algorithm */ ++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); ++} ++ ++static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, ++ unsigned int queue_count) ++{ ++ unsigned int q_fifo_size = 0; ++ enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256; ++ ++ /* Calculate Tx/Rx fifo share per queue */ ++ switch (fifo_size) { ++ case 0: ++ q_fifo_size = XGBE_FIFO_SIZE_B(128); ++ break; ++ case 1: ++ q_fifo_size = XGBE_FIFO_SIZE_B(256); ++ break; ++ case 2: ++ q_fifo_size = XGBE_FIFO_SIZE_B(512); ++ break; ++ case 3: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(1); ++ break; ++ case 4: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(2); ++ break; ++ case 5: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(4); ++ break; ++ case 6: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(8); ++ break; ++ case 7: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(16); ++ break; ++ case 8: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(32); ++ break; ++ case 9: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(64); ++ break; ++ case 10: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(128); ++ break; ++ case 11: ++ q_fifo_size = XGBE_FIFO_SIZE_KB(256); ++ break; ++ } ++ ++ /* The configured value is not the actual amount of fifo RAM */ ++ q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); ++ ++ q_fifo_size = q_fifo_size / queue_count; ++ ++ /* Set the queue fifo size programmable value */ ++ if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_256K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_128K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_64K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_32K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_16K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_8K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_4K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_2K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_1K; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_512; ++ else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256)) ++ p_fifo = XGMAC_MTL_FIFO_SIZE_256; ++ ++ return p_fifo; ++} ++ ++static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) ++{ ++ enum xgbe_mtl_fifo_size fifo_size; ++ unsigned int i; ++ ++ fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, ++ pdata->tx_q_count); ++ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); ++ ++ netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n", ++ pdata->tx_q_count, ((fifo_size + 1) * 256)); ++} ++ ++static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) ++{ ++ enum xgbe_mtl_fifo_size fifo_size; ++ unsigned int i; ++ ++ fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, ++ pdata->rx_q_count); ++ ++ for (i = 0; i < pdata->rx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); ++ ++ netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n", ++ pdata->rx_q_count, ((fifo_size + 1) * 256)); ++} ++ ++static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) ++{ ++ unsigned int qptc, qptc_extra, queue; ++ unsigned int prio_queues; ++ unsigned int ppq, ppq_extra, prio; ++ unsigned int mask; ++ unsigned int i, j, reg, reg_val; ++ ++ /* Map the MTL Tx Queues to Traffic Classes ++ * Note: Tx Queues >= Traffic Classes ++ */ ++ qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; ++ qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; ++ ++ for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { ++ for (j = 0; j < qptc; j++) { ++ DBGPR(" TXq%u mapped to TC%u\n", queue, i); ++ XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, ++ Q2TCMAP, i); ++ pdata->q2tc_map[queue++] = i; ++ } ++ ++ if (i < qptc_extra) { ++ DBGPR(" TXq%u mapped to TC%u\n", queue, i); ++ XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, ++ Q2TCMAP, i); ++ pdata->q2tc_map[queue++] = i; ++ } ++ } ++ ++ /* Map the 8 VLAN priority values to available MTL Rx queues */ ++ prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, ++ pdata->rx_q_count); ++ ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; ++ ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; ++ ++ reg = MAC_RQC2R; ++ reg_val = 0; ++ for (i = 0, prio = 0; i < prio_queues;) { ++ mask = 0; ++ for (j = 0; j < ppq; j++) { ++ DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); ++ mask |= (1 << prio); ++ pdata->prio2q_map[prio++] = i; ++ } ++ ++ if (i < ppq_extra) { ++ DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); ++ mask |= (1 << prio); ++ pdata->prio2q_map[prio++] = i; ++ } ++ ++ reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); ++ ++ if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) ++ continue; ++ ++ XGMAC_IOWRITE(pdata, reg, reg_val); ++ reg += MAC_RQC2_INC; ++ reg_val = 0; ++ } ++ ++ /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ ++ reg = MTL_RQDCM0R; ++ reg_val = 0; ++ for (i = 0; i < pdata->rx_q_count;) { ++ reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); ++ ++ if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) ++ continue; ++ ++ XGMAC_IOWRITE(pdata, reg, reg_val); ++ ++ reg += MTL_RQDCM_INC; ++ reg_val = 0; ++ } ++} ++ ++static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pdata->rx_q_count; i++) { ++ /* Activate flow control when less than 4k left in fifo */ ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2); ++ ++ /* De-activate flow control when more than 6k left in fifo */ ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4); ++ } ++} ++ ++static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) ++{ ++ xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); ++ ++ /* Filtering is done using perfect filtering and hash filtering */ ++ if (pdata->hw_feat.hash_table_size) { ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); ++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); ++ } ++} ++ ++static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) ++{ ++ unsigned int val; ++ ++ val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; ++ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); ++} ++ ++static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) ++{ ++ switch (pdata->phy_speed) { ++ case SPEED_10000: ++ xgbe_set_xgmii_speed(pdata); ++ break; ++ ++ case SPEED_2500: ++ xgbe_set_gmii_2500_speed(pdata); ++ break; ++ ++ case SPEED_1000: ++ xgbe_set_gmii_speed(pdata); ++ break; ++ } ++} ++ ++static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) ++{ ++ if (pdata->netdev->features & NETIF_F_RXCSUM) ++ xgbe_enable_rx_csum(pdata); ++ else ++ xgbe_disable_rx_csum(pdata); ++} ++ ++static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) ++{ ++ /* Indicate that VLAN Tx CTAGs come from context descriptors */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); ++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); ++ ++ /* Set the current VLAN Hash Table register value */ ++ xgbe_update_vlan_hash_table(pdata); ++ ++ if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) ++ xgbe_enable_rx_vlan_filtering(pdata); ++ else ++ xgbe_disable_rx_vlan_filtering(pdata); ++ ++ if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ++ xgbe_enable_rx_vlan_stripping(pdata); ++ else ++ xgbe_disable_rx_vlan_stripping(pdata); ++} ++ ++static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) ++{ ++ bool read_hi; ++ u64 val; ++ ++ switch (reg_lo) { ++ /* These registers are always 64 bit */ ++ case MMC_TXOCTETCOUNT_GB_LO: ++ case MMC_TXOCTETCOUNT_G_LO: ++ case MMC_RXOCTETCOUNT_GB_LO: ++ case MMC_RXOCTETCOUNT_G_LO: ++ read_hi = true; ++ break; ++ ++ default: ++ read_hi = false; ++ }; ++ ++ val = XGMAC_IOREAD(pdata, reg_lo); ++ ++ if (read_hi) ++ val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); ++ ++ return val; ++} ++ ++static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats; ++ unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) ++ stats->txoctetcount_gb += ++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) ++ stats->txframecount_gb += ++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) ++ stats->txbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) ++ stats->txmulticastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) ++ stats->tx64octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) ++ stats->tx65to127octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) ++ stats->tx128to255octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) ++ stats->tx256to511octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) ++ stats->tx512to1023octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) ++ stats->tx1024tomaxoctets_gb += ++ xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) ++ stats->txunicastframes_gb += ++ xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) ++ stats->txmulticastframes_gb += ++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) ++ stats->txbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) ++ stats->txunderflowerror += ++ xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) ++ stats->txoctetcount_g += ++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) ++ stats->txframecount_g += ++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) ++ stats->txpauseframes += ++ xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) ++ stats->txvlanframes_g += ++ xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); ++} ++ ++static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats; ++ unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) ++ stats->rxframecount_gb += ++ xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) ++ stats->rxoctetcount_gb += ++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) ++ stats->rxoctetcount_g += ++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) ++ stats->rxbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) ++ stats->rxmulticastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) ++ stats->rxcrcerror += ++ xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) ++ stats->rxrunterror += ++ xgbe_mmc_read(pdata, MMC_RXRUNTERROR); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) ++ stats->rxjabbererror += ++ xgbe_mmc_read(pdata, MMC_RXJABBERERROR); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) ++ stats->rxundersize_g += ++ xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) ++ stats->rxoversize_g += ++ xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) ++ stats->rx64octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) ++ stats->rx65to127octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) ++ stats->rx128to255octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) ++ stats->rx256to511octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) ++ stats->rx512to1023octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) ++ stats->rx1024tomaxoctets_gb += ++ xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) ++ stats->rxunicastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) ++ stats->rxlengtherror += ++ xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) ++ stats->rxoutofrangetype += ++ xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) ++ stats->rxpauseframes += ++ xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) ++ stats->rxfifooverflow += ++ xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) ++ stats->rxvlanframes_gb += ++ xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); ++ ++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) ++ stats->rxwatchdogerror += ++ xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); ++} ++ ++static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats; ++ ++ /* Freeze counters */ ++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); ++ ++ stats->txoctetcount_gb += ++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); ++ ++ stats->txframecount_gb += ++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); ++ ++ stats->txbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); ++ ++ stats->txmulticastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); ++ ++ stats->tx64octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); ++ ++ stats->tx65to127octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); ++ ++ stats->tx128to255octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); ++ ++ stats->tx256to511octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); ++ ++ stats->tx512to1023octets_gb += ++ xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); ++ ++ stats->tx1024tomaxoctets_gb += ++ xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); ++ ++ stats->txunicastframes_gb += ++ xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); ++ ++ stats->txmulticastframes_gb += ++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); ++ ++ stats->txbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); ++ ++ stats->txunderflowerror += ++ xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); ++ ++ stats->txoctetcount_g += ++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); ++ ++ stats->txframecount_g += ++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); ++ ++ stats->txpauseframes += ++ xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); ++ ++ stats->txvlanframes_g += ++ xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); ++ ++ stats->rxframecount_gb += ++ xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); ++ ++ stats->rxoctetcount_gb += ++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); ++ ++ stats->rxoctetcount_g += ++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); ++ ++ stats->rxbroadcastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); ++ ++ stats->rxmulticastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); ++ ++ stats->rxcrcerror += ++ xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); ++ ++ stats->rxrunterror += ++ xgbe_mmc_read(pdata, MMC_RXRUNTERROR); ++ ++ stats->rxjabbererror += ++ xgbe_mmc_read(pdata, MMC_RXJABBERERROR); ++ ++ stats->rxundersize_g += ++ xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); ++ ++ stats->rxoversize_g += ++ xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); ++ ++ stats->rx64octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); ++ ++ stats->rx65to127octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); ++ ++ stats->rx128to255octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); ++ ++ stats->rx256to511octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); ++ ++ stats->rx512to1023octets_gb += ++ xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); ++ ++ stats->rx1024tomaxoctets_gb += ++ xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); ++ ++ stats->rxunicastframes_g += ++ xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); ++ ++ stats->rxlengtherror += ++ xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); ++ ++ stats->rxoutofrangetype += ++ xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); ++ ++ stats->rxpauseframes += ++ xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); ++ ++ stats->rxfifooverflow += ++ xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); ++ ++ stats->rxvlanframes_gb += ++ xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); ++ ++ stats->rxwatchdogerror += ++ xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); ++ ++ /* Un-freeze counters */ ++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); ++} ++ ++static void xgbe_config_mmc(struct xgbe_prv_data *pdata) ++{ ++ /* Set counters to reset on read */ ++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); ++ ++ /* Reset the counters */ ++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); ++} ++ ++static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, ++ struct xgbe_channel *channel) ++{ ++ unsigned int tx_dsr, tx_pos, tx_qidx; ++ unsigned int tx_status; ++ unsigned long tx_timeout; ++ ++ /* Calculate the status register to read and the position within */ ++ if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { ++ tx_dsr = DMA_DSR0; ++ tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) + ++ DMA_DSR0_TPS_START; ++ } else { ++ tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; ++ ++ tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); ++ tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + ++ DMA_DSRX_TPS_START; ++ } ++ ++ /* The Tx engine cannot be stopped if it is actively processing ++ * descriptors. Wait for the Tx engine to enter the stopped or ++ * suspended state. Don't wait forever though... ++ */ ++ tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); ++ while (time_before(jiffies, tx_timeout)) { ++ tx_status = XGMAC_IOREAD(pdata, tx_dsr); ++ tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); ++ if ((tx_status == DMA_TPS_STOPPED) || ++ (tx_status == DMA_TPS_SUSPENDED)) ++ break; ++ ++ usleep_range(500, 1000); ++ } ++ ++ if (!time_before(jiffies, tx_timeout)) ++ netdev_info(pdata->netdev, ++ "timed out waiting for Tx DMA channel %u to stop\n", ++ channel->queue_index); ++} ++ ++static void xgbe_enable_tx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Enable each Tx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); ++ } ++ ++ /* Enable each Tx queue */ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, ++ MTL_Q_ENABLED); ++ ++ /* Enable MAC Tx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); ++} ++ ++static void xgbe_disable_tx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Prepare for Tx DMA channel stop */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ xgbe_prepare_tx_stop(pdata, channel); ++ } ++ ++ /* Disable MAC Tx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); ++ ++ /* Disable each Tx queue */ ++ for (i = 0; i < pdata->tx_q_count; i++) ++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); ++ ++ /* Disable each Tx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); ++ } ++} ++ ++static void xgbe_enable_rx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int reg_val, i; ++ ++ /* Enable each Rx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); ++ } ++ ++ /* Enable each Rx queue */ ++ reg_val = 0; ++ for (i = 0; i < pdata->rx_q_count; i++) ++ reg_val |= (0x02 << (i << 1)); ++ XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); ++ ++ /* Enable MAC Rx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); ++} ++ ++static void xgbe_disable_rx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Disable MAC Rx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); ++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); ++ ++ /* Disable each Rx queue */ ++ XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); ++ ++ /* Disable each Rx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); ++ } ++} ++ ++static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Enable each Tx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); ++ } ++ ++ /* Enable MAC Tx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); ++} ++ ++static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Prepare for Tx DMA channel stop */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ xgbe_prepare_tx_stop(pdata, channel); ++ } ++ ++ /* Disable MAC Tx */ ++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); ++ ++ /* Disable each Tx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); ++ } ++} ++ ++static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Enable each Rx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); ++ } ++} ++ ++static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ /* Disable each Rx DMA channel */ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->rx_ring) ++ break; ++ ++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); ++ } ++} ++ ++static int xgbe_init(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ int ret; ++ ++ DBGPR("-->xgbe_init\n"); ++ ++ /* Flush Tx queues */ ++ ret = xgbe_flush_tx_queues(pdata); ++ if (ret) ++ return ret; ++ ++ /* ++ * Initialize DMA related features ++ */ ++ xgbe_config_dma_bus(pdata); ++ xgbe_config_dma_cache(pdata); ++ xgbe_config_osp_mode(pdata); ++ xgbe_config_pblx8(pdata); ++ xgbe_config_tx_pbl_val(pdata); ++ xgbe_config_rx_pbl_val(pdata); ++ xgbe_config_rx_coalesce(pdata); ++ xgbe_config_tx_coalesce(pdata); ++ xgbe_config_rx_buffer_size(pdata); ++ xgbe_config_tso_mode(pdata); ++ xgbe_config_sph_mode(pdata); ++ xgbe_config_rss(pdata); ++ desc_if->wrapper_tx_desc_init(pdata); ++ desc_if->wrapper_rx_desc_init(pdata); ++ xgbe_enable_dma_interrupts(pdata); ++ ++ /* ++ * Initialize MTL related features ++ */ ++ xgbe_config_mtl_mode(pdata); ++ xgbe_config_queue_mapping(pdata); ++ xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); ++ xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); ++ xgbe_config_tx_threshold(pdata, pdata->tx_threshold); ++ xgbe_config_rx_threshold(pdata, pdata->rx_threshold); ++ xgbe_config_tx_fifo_size(pdata); ++ xgbe_config_rx_fifo_size(pdata); ++ xgbe_config_flow_control_threshold(pdata); ++ /*TODO: Error Packet and undersized good Packet forwarding enable ++ (FEP and FUP) ++ */ ++ xgbe_config_dcb_tc(pdata); ++ xgbe_config_dcb_pfc(pdata); ++ xgbe_enable_mtl_interrupts(pdata); ++ ++ /* ++ * Initialize MAC related features ++ */ ++ xgbe_config_mac_address(pdata); ++ xgbe_config_jumbo_enable(pdata); ++ xgbe_config_flow_control(pdata); ++ xgbe_config_mac_speed(pdata); ++ xgbe_config_checksum_offload(pdata); ++ xgbe_config_vlan_support(pdata); ++ xgbe_config_mmc(pdata); ++ xgbe_enable_mac_interrupts(pdata); ++ ++ DBGPR("<--xgbe_init\n"); ++ ++ return 0; ++} ++ ++void xgbe_a0_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) ++{ ++ DBGPR("-->xgbe_a0_init_function_ptrs\n"); ++ ++ hw_if->tx_complete = xgbe_tx_complete; ++ ++ hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode; ++ hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode; ++ hw_if->add_mac_addresses = xgbe_add_mac_addresses; ++ hw_if->set_mac_address = xgbe_set_mac_address; ++ ++ hw_if->enable_rx_csum = xgbe_enable_rx_csum; ++ hw_if->disable_rx_csum = xgbe_disable_rx_csum; ++ ++ hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; ++ hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; ++ hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; ++ hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; ++ hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; ++ ++ hw_if->read_mmd_regs = xgbe_read_mmd_regs; ++ hw_if->write_mmd_regs = xgbe_write_mmd_regs; ++ ++ hw_if->set_gmii_speed = xgbe_set_gmii_speed; ++ hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; ++ hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; ++ ++ hw_if->enable_tx = xgbe_enable_tx; ++ hw_if->disable_tx = xgbe_disable_tx; ++ hw_if->enable_rx = xgbe_enable_rx; ++ hw_if->disable_rx = xgbe_disable_rx; ++ ++ hw_if->powerup_tx = xgbe_powerup_tx; ++ hw_if->powerdown_tx = xgbe_powerdown_tx; ++ hw_if->powerup_rx = xgbe_powerup_rx; ++ hw_if->powerdown_rx = xgbe_powerdown_rx; ++ ++ hw_if->dev_xmit = xgbe_dev_xmit; ++ hw_if->dev_read = xgbe_dev_read; ++ hw_if->enable_int = xgbe_enable_int; ++ hw_if->disable_int = xgbe_disable_int; ++ hw_if->init = xgbe_init; ++ hw_if->exit = xgbe_exit; ++ ++ /* Descriptor related Sequences have to be initialized here */ ++ hw_if->tx_desc_init = xgbe_tx_desc_init; ++ hw_if->rx_desc_init = xgbe_rx_desc_init; ++ hw_if->tx_desc_reset = xgbe_tx_desc_reset; ++ hw_if->rx_desc_reset = xgbe_rx_desc_reset; ++ hw_if->is_last_desc = xgbe_is_last_desc; ++ hw_if->is_context_desc = xgbe_is_context_desc; ++ hw_if->tx_start_xmit = xgbe_tx_start_xmit; ++ ++ /* For FLOW ctrl */ ++ hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; ++ hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; ++ ++ /* For RX coalescing */ ++ hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; ++ hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; ++ hw_if->usec_to_riwt = xgbe_usec_to_riwt; ++ hw_if->riwt_to_usec = xgbe_riwt_to_usec; ++ ++ /* For RX and TX threshold config */ ++ hw_if->config_rx_threshold = xgbe_config_rx_threshold; ++ hw_if->config_tx_threshold = xgbe_config_tx_threshold; ++ ++ /* For RX and TX Store and Forward Mode config */ ++ hw_if->config_rsf_mode = xgbe_config_rsf_mode; ++ hw_if->config_tsf_mode = xgbe_config_tsf_mode; ++ ++ /* For TX DMA Operating on Second Frame config */ ++ hw_if->config_osp_mode = xgbe_config_osp_mode; ++ ++ /* For RX and TX PBL config */ ++ hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; ++ hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; ++ hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; ++ hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; ++ hw_if->config_pblx8 = xgbe_config_pblx8; ++ ++ /* For MMC statistics support */ ++ hw_if->tx_mmc_int = xgbe_tx_mmc_int; ++ hw_if->rx_mmc_int = xgbe_rx_mmc_int; ++ hw_if->read_mmc_stats = xgbe_read_mmc_stats; ++ ++ /* For PTP config */ ++ hw_if->config_tstamp = xgbe_config_tstamp; ++ hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; ++ hw_if->set_tstamp_time = xgbe_set_tstamp_time; ++ hw_if->get_tstamp_time = xgbe_get_tstamp_time; ++ hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; ++ ++ /* For Data Center Bridging config */ ++ hw_if->config_dcb_tc = xgbe_config_dcb_tc; ++ hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; ++ ++ /* For Receive Side Scaling */ ++ hw_if->enable_rss = xgbe_enable_rss; ++ hw_if->disable_rss = xgbe_disable_rss; ++ hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; ++ hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; ++ ++ DBGPR("<--xgbe_a0_init_function_ptrs\n"); ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c +new file mode 100644 +index 0000000..ca4af9e +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c +@@ -0,0 +1,2218 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static int xgbe_one_poll(struct napi_struct *, int); ++static int xgbe_all_poll(struct napi_struct *, int); ++static void xgbe_set_rx_mode(struct net_device *); ++ ++static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel_mem, *channel; ++ struct xgbe_ring *tx_ring, *rx_ring; ++ unsigned int count, i; ++ int ret = -ENOMEM; ++ ++ count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); ++ ++ channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); ++ if (!channel_mem) ++ goto err_channel; ++ ++ tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), ++ GFP_KERNEL); ++ if (!tx_ring) ++ goto err_tx_ring; ++ ++ rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), ++ GFP_KERNEL); ++ if (!rx_ring) ++ goto err_rx_ring; ++ ++ for (i = 0, channel = channel_mem; i < count; i++, channel++) { ++ snprintf(channel->name, sizeof(channel->name), "channel-%d", i); ++ channel->pdata = pdata; ++ channel->queue_index = i; ++ channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + ++ (DMA_CH_INC * i); ++ ++ if (pdata->per_channel_irq) { ++ /* Get the DMA interrupt (offset 1) */ ++ ret = platform_get_irq(pdata->pdev, i + 1); ++ if (ret < 0) { ++ netdev_err(pdata->netdev, ++ "platform_get_irq %u failed\n", ++ i + 1); ++ goto err_irq; ++ } ++ ++ channel->dma_irq = ret; ++ } ++ ++ if (i < pdata->tx_ring_count) { ++ spin_lock_init(&tx_ring->lock); ++ channel->tx_ring = tx_ring++; ++ } ++ ++ if (i < pdata->rx_ring_count) { ++ spin_lock_init(&rx_ring->lock); ++ channel->rx_ring = rx_ring++; ++ } ++ ++ DBGPR(" %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", ++ channel->name, channel->queue_index, channel->dma_regs, ++ channel->dma_irq, channel->tx_ring, channel->rx_ring); ++ } ++ ++ pdata->channel = channel_mem; ++ pdata->channel_count = count; ++ ++ return 0; ++ ++err_irq: ++ kfree(rx_ring); ++ ++err_rx_ring: ++ kfree(tx_ring); ++ ++err_tx_ring: ++ kfree(channel_mem); ++ ++err_channel: ++ return ret; ++} ++ ++static void xgbe_free_channels(struct xgbe_prv_data *pdata) ++{ ++ if (!pdata->channel) ++ return; ++ ++ kfree(pdata->channel->rx_ring); ++ kfree(pdata->channel->tx_ring); ++ kfree(pdata->channel); ++ ++ pdata->channel = NULL; ++ pdata->channel_count = 0; ++} ++ ++static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) ++{ ++ return (ring->rdesc_count - (ring->cur - ring->dirty)); ++} ++ ++static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) ++{ ++ return (ring->cur - ring->dirty); ++} ++ ++static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, ++ struct xgbe_ring *ring, unsigned int count) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ ++ if (count > xgbe_tx_avail_desc(ring)) { ++ DBGPR(" Tx queue stopped, not enough descriptors available\n"); ++ netif_stop_subqueue(pdata->netdev, channel->queue_index); ++ ring->tx.queue_stopped = 1; ++ ++ /* If we haven't notified the hardware because of xmit_more ++ * support, tell it now ++ */ ++ if (ring->tx.xmit_more) ++ pdata->hw_if.tx_start_xmit(channel, ring); ++ ++ return NETDEV_TX_BUSY; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) ++{ ++ unsigned int rx_buf_size; ++ ++ if (mtu > XGMAC_JUMBO_PACKET_MTU) { ++ netdev_alert(netdev, "MTU exceeds maximum supported value\n"); ++ return -EINVAL; ++ } ++ ++ rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; ++ rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); ++ ++ rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & ++ ~(XGBE_RX_BUF_ALIGN - 1); ++ ++ return rx_buf_size; ++} ++ ++static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ enum xgbe_int int_id; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (channel->tx_ring && channel->rx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_TI_RI; ++ else if (channel->tx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_TI; ++ else if (channel->rx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_RI; ++ else ++ continue; ++ ++ hw_if->enable_int(channel, int_id); ++ } ++} ++ ++static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ enum xgbe_int int_id; ++ unsigned int i; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (channel->tx_ring && channel->rx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_TI_RI; ++ else if (channel->tx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_TI; ++ else if (channel->rx_ring) ++ int_id = XGMAC_INT_DMA_CH_SR_RI; ++ else ++ continue; ++ ++ hw_if->disable_int(channel, int_id); ++ } ++} ++ ++static irqreturn_t xgbe_isr(int irq, void *data) ++{ ++ struct xgbe_prv_data *pdata = data; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ unsigned int dma_isr, dma_ch_isr; ++ unsigned int mac_isr, mac_tssr; ++ unsigned int i; ++ ++ /* The DMA interrupt status register also reports MAC and MTL ++ * interrupts. So for polling mode, we just need to check for ++ * this register to be non-zero ++ */ ++ dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); ++ if (!dma_isr) ++ goto isr_done; ++ ++ DBGPR(" DMA_ISR = %08x\n", dma_isr); ++ ++ for (i = 0; i < pdata->channel_count; i++) { ++ if (!(dma_isr & (1 << i))) ++ continue; ++ ++ channel = pdata->channel + i; ++ ++ dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); ++ DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr); ++ ++ /* The TI or RI interrupt bits may still be set even if using ++ * per channel DMA interrupts. Check to be sure those are not ++ * enabled before using the private data napi structure. ++ */ ++ if (!pdata->per_channel_irq && ++ (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || ++ XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { ++ if (napi_schedule_prep(&pdata->napi)) { ++ /* Disable Tx and Rx interrupts */ ++ xgbe_disable_rx_tx_ints(pdata); ++ ++ /* Turn on polling */ ++ __napi_schedule(&pdata->napi); ++ } ++ } ++ ++ /* Restart the device on a Fatal Bus Error */ ++ if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) ++ schedule_work(&pdata->restart_work); ++ ++ /* Clear all interrupt signals */ ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); ++ } ++ ++ if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { ++ mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); ++ ++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) ++ hw_if->tx_mmc_int(pdata); ++ ++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) ++ hw_if->rx_mmc_int(pdata); ++ ++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { ++ mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); ++ ++ if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { ++ /* Read Tx Timestamp to clear interrupt */ ++ pdata->tx_tstamp = ++ hw_if->get_tx_tstamp(pdata); ++ schedule_work(&pdata->tx_tstamp_work); ++ } ++ } ++ } ++ ++ DBGPR(" DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR)); ++ ++isr_done: ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t xgbe_dma_isr(int irq, void *data) ++{ ++ struct xgbe_channel *channel = data; ++ ++ /* Per channel DMA interrupts are enabled, so we use the per ++ * channel napi structure and not the private data napi structure ++ */ ++ if (napi_schedule_prep(&channel->napi)) { ++ /* Disable Tx and Rx interrupts */ ++ disable_irq_nosync(channel->dma_irq); ++ ++ /* Turn on polling */ ++ __napi_schedule(&channel->napi); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer) ++{ ++ struct xgbe_channel *channel = container_of(timer, ++ struct xgbe_channel, ++ tx_timer); ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct napi_struct *napi; ++ ++ DBGPR("-->xgbe_tx_timer\n"); ++ ++ napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; ++ ++ if (napi_schedule_prep(napi)) { ++ /* Disable Tx and Rx interrupts */ ++ if (pdata->per_channel_irq) ++ disable_irq(channel->dma_irq); ++ else ++ xgbe_disable_rx_tx_ints(pdata); ++ ++ /* Turn on polling */ ++ __napi_schedule(napi); ++ } ++ ++ channel->tx_timer_active = 0; ++ ++ DBGPR("<--xgbe_tx_timer\n"); ++ ++ return HRTIMER_NORESTART; ++} ++ ++static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_init_tx_timers\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ DBGPR(" %s adding tx timer\n", channel->name); ++ hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC, ++ HRTIMER_MODE_REL); ++ channel->tx_timer.function = xgbe_tx_timer; ++ } ++ ++ DBGPR("<--xgbe_init_tx_timers\n"); ++} ++ ++static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_stop_tx_timers\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ break; ++ ++ DBGPR(" %s deleting tx timer\n", channel->name); ++ channel->tx_timer_active = 0; ++ hrtimer_cancel(&channel->tx_timer); ++ } ++ ++ DBGPR("<--xgbe_stop_tx_timers\n"); ++} ++ ++void xgbe_a0_get_all_hw_features(struct xgbe_prv_data *pdata) ++{ ++ unsigned int mac_hfr0, mac_hfr1, mac_hfr2; ++ struct xgbe_hw_features *hw_feat = &pdata->hw_feat; ++ ++ DBGPR("-->xgbe_a0_get_all_hw_features\n"); ++ ++ mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); ++ mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); ++ mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); ++ ++ memset(hw_feat, 0, sizeof(*hw_feat)); ++ ++ hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); ++ ++ /* Hardware feature register 0 */ ++ hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); ++ hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); ++ hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); ++ hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); ++ hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); ++ hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); ++ hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); ++ hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); ++ hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); ++ hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); ++ hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); ++ hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ++ ADDMACADRSEL); ++ hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); ++ hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); ++ ++ /* Hardware feature register 1 */ ++ hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ++ RXFIFOSIZE); ++ hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ++ TXFIFOSIZE); ++ hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); ++ hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); ++ hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); ++ hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); ++ hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); ++ hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); ++ hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ++ HASHTBLSZ); ++ hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ++ L3L4FNUM); ++ ++ /* Hardware feature register 2 */ ++ hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); ++ hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); ++ hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); ++ hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); ++ hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); ++ hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); ++ ++ /* Translate the Hash Table size into actual number */ ++ switch (hw_feat->hash_table_size) { ++ case 0: ++ break; ++ case 1: ++ hw_feat->hash_table_size = 64; ++ break; ++ case 2: ++ hw_feat->hash_table_size = 128; ++ break; ++ case 3: ++ hw_feat->hash_table_size = 256; ++ break; ++ } ++ ++ /* The Queue, Channel and TC counts are zero based so increment them ++ * to get the actual number ++ */ ++ hw_feat->rx_q_cnt++; ++ hw_feat->tx_q_cnt++; ++ hw_feat->rx_ch_cnt++; ++ hw_feat->tx_ch_cnt++; ++ hw_feat->tc_cnt++; ++ ++#define XGBE_TC_CNT 2 ++ hw_feat->tc_cnt = XGBE_TC_CNT; ++ ++ DBGPR("<--xgbe_a0_get_all_hw_features\n"); ++} ++ ++static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ if (pdata->per_channel_irq) { ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (add) ++ netif_napi_add(pdata->netdev, &channel->napi, ++ xgbe_one_poll, NAPI_POLL_WEIGHT); ++ ++ napi_enable(&channel->napi); ++ } ++ } else { ++ if (add) ++ netif_napi_add(pdata->netdev, &pdata->napi, ++ xgbe_all_poll, NAPI_POLL_WEIGHT); ++ ++ napi_enable(&pdata->napi); ++ } ++} ++ ++static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ if (pdata->per_channel_irq) { ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ napi_disable(&channel->napi); ++ ++ if (del) ++ netif_napi_del(&channel->napi); ++ } ++ } else { ++ napi_disable(&pdata->napi); ++ ++ if (del) ++ netif_napi_del(&pdata->napi); ++ } ++} ++ ++static int xgbe_request_irqs(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ struct net_device *netdev = pdata->netdev; ++ unsigned int i; ++ int ret; ++ ++ ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, ++ netdev->name, pdata); ++ if (ret) { ++ netdev_alert(netdev, "error requesting irq %d\n", ++ pdata->dev_irq); ++ return ret; ++ } ++ ++ if (!pdata->per_channel_irq) ++ return 0; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ snprintf(channel->dma_irq_name, ++ sizeof(channel->dma_irq_name) - 1, ++ "%s-TxRx-%u", netdev_name(netdev), ++ channel->queue_index); ++ ++ ret = devm_request_irq(pdata->dev, channel->dma_irq, ++ xgbe_dma_isr, 0, ++ channel->dma_irq_name, channel); ++ if (ret) { ++ netdev_alert(netdev, "error requesting irq %d\n", ++ channel->dma_irq); ++ goto err_irq; ++ } ++ } ++ ++ return 0; ++ ++err_irq: ++ /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ ++ for (i--, channel--; i < pdata->channel_count; i--, channel--) ++ devm_free_irq(pdata->dev, channel->dma_irq, channel); ++ ++ devm_free_irq(pdata->dev, pdata->dev_irq, pdata); ++ ++ return ret; ++} ++ ++static void xgbe_free_irqs(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ devm_free_irq(pdata->dev, pdata->dev_irq, pdata); ++ ++ if (!pdata->per_channel_irq) ++ return; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) ++ devm_free_irq(pdata->dev, channel->dma_irq, channel); ++} ++ ++void xgbe_a0_init_tx_coalesce(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ ++ DBGPR("-->xgbe_a0_init_tx_coalesce\n"); ++ ++ pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; ++ pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; ++ ++ hw_if->config_tx_coalesce(pdata); ++ ++ DBGPR("<--xgbe_a0_init_tx_coalesce\n"); ++} ++ ++void xgbe_a0_init_rx_coalesce(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ ++ DBGPR("-->xgbe_a0_init_rx_coalesce\n"); ++ ++ pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); ++ pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; ++ ++ hw_if->config_rx_coalesce(pdata); ++ ++ DBGPR("<--xgbe_a0_init_rx_coalesce\n"); ++} ++ ++static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ struct xgbe_channel *channel; ++ struct xgbe_ring *ring; ++ struct xgbe_ring_data *rdata; ++ unsigned int i, j; ++ ++ DBGPR("-->xgbe_free_tx_data\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ ring = channel->tx_ring; ++ if (!ring) ++ break; ++ ++ for (j = 0; j < ring->rdesc_count; j++) { ++ rdata = XGBE_GET_DESC_DATA(ring, j); ++ desc_if->unmap_rdata(pdata, rdata); ++ } ++ } ++ ++ DBGPR("<--xgbe_free_tx_data\n"); ++} ++ ++static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ struct xgbe_channel *channel; ++ struct xgbe_ring *ring; ++ struct xgbe_ring_data *rdata; ++ unsigned int i, j; ++ ++ DBGPR("-->xgbe_free_rx_data\n"); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ ring = channel->rx_ring; ++ if (!ring) ++ break; ++ ++ for (j = 0; j < ring->rdesc_count; j++) { ++ rdata = XGBE_GET_DESC_DATA(ring, j); ++ desc_if->unmap_rdata(pdata, rdata); ++ } ++ } ++ ++ DBGPR("<--xgbe_free_rx_data\n"); ++} ++ ++static void xgbe_adjust_link(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct phy_device *phydev = pdata->phydev; ++ int new_state = 0; ++ ++ if (!phydev) ++ return; ++ ++ if (phydev->link) { ++ /* Flow control support */ ++ if (pdata->pause_autoneg) { ++ if (phydev->pause || phydev->asym_pause) { ++ pdata->tx_pause = 1; ++ pdata->rx_pause = 1; ++ } else { ++ pdata->tx_pause = 0; ++ pdata->rx_pause = 0; ++ } ++ } ++ ++ if (pdata->tx_pause != pdata->phy_tx_pause) { ++ hw_if->config_tx_flow_control(pdata); ++ pdata->phy_tx_pause = pdata->tx_pause; ++ } ++ ++ if (pdata->rx_pause != pdata->phy_rx_pause) { ++ hw_if->config_rx_flow_control(pdata); ++ pdata->phy_rx_pause = pdata->rx_pause; ++ } ++ ++ /* Speed support */ ++ if (phydev->speed != pdata->phy_speed) { ++ new_state = 1; ++ ++ switch (phydev->speed) { ++ case SPEED_10000: ++ hw_if->set_xgmii_speed(pdata); ++ break; ++ ++ case SPEED_2500: ++ hw_if->set_gmii_2500_speed(pdata); ++ break; ++ ++ case SPEED_1000: ++ hw_if->set_gmii_speed(pdata); ++ break; ++ } ++ pdata->phy_speed = phydev->speed; ++ } ++ ++ if (phydev->link != pdata->phy_link) { ++ new_state = 1; ++ pdata->phy_link = 1; ++ } ++ } else if (pdata->phy_link) { ++ new_state = 1; ++ pdata->phy_link = 0; ++ pdata->phy_speed = SPEED_UNKNOWN; ++ } ++ ++ if (new_state) ++ phy_print_status(phydev); ++} ++ ++static int xgbe_phy_init(struct xgbe_prv_data *pdata) ++{ ++ struct net_device *netdev = pdata->netdev; ++ struct phy_device *phydev = pdata->phydev; ++ int ret; ++ ++ pdata->phy_link = -1; ++ pdata->phy_speed = SPEED_UNKNOWN; ++ pdata->phy_tx_pause = pdata->tx_pause; ++ pdata->phy_rx_pause = pdata->rx_pause; ++ ++ ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link, ++ pdata->phy_mode); ++ if (ret) { ++ netdev_err(netdev, "phy_connect_direct failed\n"); ++ return ret; ++ } ++ ++ if (!phydev->drv || (phydev->drv->phy_id == 0)) { ++ netdev_err(netdev, "phy_id not valid\n"); ++ ret = -ENODEV; ++ goto err_phy_connect; ++ } ++ DBGPR(" phy_connect_direct succeeded for PHY %s, link=%d\n", ++ dev_name(&phydev->dev), phydev->link); ++ ++ return 0; ++ ++err_phy_connect: ++ phy_disconnect(phydev); ++ ++ return ret; ++} ++ ++static void xgbe_phy_exit(struct xgbe_prv_data *pdata) ++{ ++ if (!pdata->phydev) ++ return; ++ ++ phy_disconnect(pdata->phydev); ++} ++ ++int xgbe_a0_powerdown(struct net_device *netdev, unsigned int caller) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned long flags; ++ ++ DBGPR("-->xgbe_a0_powerdown\n"); ++ ++ if (!netif_running(netdev) || ++ (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { ++ netdev_alert(netdev, "Device is already powered down\n"); ++ DBGPR("<--xgbe_a0_powerdown\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&pdata->lock, flags); ++ ++ if (caller == XGMAC_DRIVER_CONTEXT) ++ netif_device_detach(netdev); ++ ++ netif_tx_stop_all_queues(netdev); ++ ++ hw_if->powerdown_tx(pdata); ++ hw_if->powerdown_rx(pdata); ++ ++ xgbe_napi_disable(pdata, 0); ++ ++ phy_stop(pdata->phydev); ++ ++ pdata->power_down = 1; ++ ++ spin_unlock_irqrestore(&pdata->lock, flags); ++ ++ DBGPR("<--xgbe_a0_powerdown\n"); ++ ++ return 0; ++} ++ ++int xgbe_a0_powerup(struct net_device *netdev, unsigned int caller) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned long flags; ++ ++ DBGPR("-->xgbe_a0_powerup\n"); ++ ++ if (!netif_running(netdev) || ++ (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { ++ netdev_alert(netdev, "Device is already powered up\n"); ++ DBGPR("<--xgbe_a0_powerup\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&pdata->lock, flags); ++ ++ pdata->power_down = 0; ++ ++ phy_start(pdata->phydev); ++ ++ xgbe_napi_enable(pdata, 0); ++ ++ hw_if->powerup_tx(pdata); ++ hw_if->powerup_rx(pdata); ++ ++ if (caller == XGMAC_DRIVER_CONTEXT) ++ netif_device_attach(netdev); ++ ++ netif_tx_start_all_queues(netdev); ++ ++ spin_unlock_irqrestore(&pdata->lock, flags); ++ ++ DBGPR("<--xgbe_a0_powerup\n"); ++ ++ return 0; ++} ++ ++static int xgbe_start(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct net_device *netdev = pdata->netdev; ++ int ret; ++ ++ DBGPR("-->xgbe_start\n"); ++ ++ xgbe_set_rx_mode(netdev); ++ ++ hw_if->init(pdata); ++ ++ phy_start(pdata->phydev); ++ ++ xgbe_napi_enable(pdata, 1); ++ ++ ret = xgbe_request_irqs(pdata); ++ if (ret) ++ goto err_napi; ++ ++ hw_if->enable_tx(pdata); ++ hw_if->enable_rx(pdata); ++ ++ xgbe_init_tx_timers(pdata); ++ ++ netif_tx_start_all_queues(netdev); ++ ++ DBGPR("<--xgbe_start\n"); ++ ++ return 0; ++ ++err_napi: ++ xgbe_napi_disable(pdata, 1); ++ ++ phy_stop(pdata->phydev); ++ ++ hw_if->exit(pdata); ++ ++ return ret; ++} ++ ++static void xgbe_stop(struct xgbe_prv_data *pdata) ++{ ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_channel *channel; ++ struct net_device *netdev = pdata->netdev; ++ struct netdev_queue *txq; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_stop\n"); ++ ++ netif_tx_stop_all_queues(netdev); ++ ++ xgbe_stop_tx_timers(pdata); ++ ++ hw_if->disable_tx(pdata); ++ hw_if->disable_rx(pdata); ++ ++ xgbe_free_irqs(pdata); ++ ++ xgbe_napi_disable(pdata, 1); ++ ++ phy_stop(pdata->phydev); ++ ++ hw_if->exit(pdata); ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ if (!channel->tx_ring) ++ continue; ++ ++ txq = netdev_get_tx_queue(netdev, channel->queue_index); ++ netdev_tx_reset_queue(txq); ++ } ++ ++ DBGPR("<--xgbe_stop\n"); ++} ++ ++static void xgbe_restart_dev(struct xgbe_prv_data *pdata) ++{ ++ DBGPR("-->xgbe_restart_dev\n"); ++ ++ /* If not running, "restart" will happen on open */ ++ if (!netif_running(pdata->netdev)) ++ return; ++ ++ xgbe_stop(pdata); ++ ++ xgbe_free_tx_data(pdata); ++ xgbe_free_rx_data(pdata); ++ ++ xgbe_start(pdata); ++ ++ DBGPR("<--xgbe_restart_dev\n"); ++} ++ ++static void xgbe_restart(struct work_struct *work) ++{ ++ struct xgbe_prv_data *pdata = container_of(work, ++ struct xgbe_prv_data, ++ restart_work); ++ ++ rtnl_lock(); ++ ++ xgbe_restart_dev(pdata); ++ ++ rtnl_unlock(); ++} ++ ++static void xgbe_tx_tstamp(struct work_struct *work) ++{ ++ struct xgbe_prv_data *pdata = container_of(work, ++ struct xgbe_prv_data, ++ tx_tstamp_work); ++ struct skb_shared_hwtstamps hwtstamps; ++ u64 nsec; ++ unsigned long flags; ++ ++ if (pdata->tx_tstamp) { ++ nsec = timecounter_cyc2time(&pdata->tstamp_tc, ++ pdata->tx_tstamp); ++ ++ memset(&hwtstamps, 0, sizeof(hwtstamps)); ++ hwtstamps.hwtstamp = ns_to_ktime(nsec); ++ skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); ++ } ++ ++ dev_kfree_skb_any(pdata->tx_tstamp_skb); ++ ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ pdata->tx_tstamp_skb = NULL; ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++} ++ ++static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, ++ struct ifreq *ifreq) ++{ ++ if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, ++ sizeof(pdata->tstamp_config))) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, ++ struct ifreq *ifreq) ++{ ++ struct hwtstamp_config config; ++ unsigned int mac_tscr; ++ ++ if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) ++ return -EFAULT; ++ ++ if (config.flags) ++ return -EINVAL; ++ ++ mac_tscr = 0; ++ ++ switch (config.tx_type) { ++ case HWTSTAMP_TX_OFF: ++ break; ++ ++ case HWTSTAMP_TX_ON: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ default: ++ return -ERANGE; ++ } ++ ++ switch (config.rx_filter) { ++ case HWTSTAMP_FILTER_NONE: ++ break; ++ ++ case HWTSTAMP_FILTER_ALL: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2, UDP, any kind of event packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ /* PTP v1, UDP, any kind of event packet */ ++ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2, UDP, Sync packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ /* PTP v1, UDP, Sync packet */ ++ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2, UDP, Delay_req packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ /* PTP v1, UDP, Delay_req packet */ ++ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* 802.AS1, Ethernet, any kind of event packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* 802.AS1, Ethernet, Sync packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* 802.AS1, Ethernet, Delay_req packet */ ++ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2/802.AS1, any layer, any kind of event packet */ ++ case HWTSTAMP_FILTER_PTP_V2_EVENT: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2/802.AS1, any layer, Sync packet */ ++ case HWTSTAMP_FILTER_PTP_V2_SYNC: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ /* PTP v2/802.AS1, any layer, Delay_req packet */ ++ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); ++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); ++ break; ++ ++ default: ++ return -ERANGE; ++ } ++ ++ pdata->hw_if.config_tstamp(pdata, mac_tscr); ++ ++ memcpy(&pdata->tstamp_config, &config, sizeof(config)); ++ ++ return 0; ++} ++ ++static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, ++ struct sk_buff *skb, ++ struct xgbe_packet_data *packet) ++{ ++ unsigned long flags; ++ ++ if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ if (pdata->tx_tstamp_skb) { ++ /* Another timestamp in progress, ignore this one */ ++ XGMAC_SET_BITS(packet->attributes, ++ TX_PACKET_ATTRIBUTES, PTP, 0); ++ } else { ++ pdata->tx_tstamp_skb = skb_get(skb); ++ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; ++ } ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++ } ++ ++ if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) ++ skb_tx_timestamp(skb); ++} ++ ++static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) ++{ ++ if (skb_vlan_tag_present(skb)) ++ packet->vlan_ctag = skb_vlan_tag_get(skb); ++} ++ ++static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) ++{ ++ int ret; ++ ++ if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ TSO_ENABLE)) ++ return 0; ++ ++ ret = skb_cow_head(skb, 0); ++ if (ret) ++ return ret; ++ ++ packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); ++ packet->tcp_header_len = tcp_hdrlen(skb); ++ packet->tcp_payload_len = skb->len - packet->header_len; ++ packet->mss = skb_shinfo(skb)->gso_size; ++ DBGPR(" packet->header_len=%u\n", packet->header_len); ++ DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", ++ packet->tcp_header_len, packet->tcp_payload_len); ++ DBGPR(" packet->mss=%u\n", packet->mss); ++ ++ /* Update the number of packets that will ultimately be transmitted ++ * along with the extra bytes for each extra packet ++ */ ++ packet->tx_packets = skb_shinfo(skb)->gso_segs; ++ packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; ++ ++ return 0; ++} ++ ++static int xgbe_is_tso(struct sk_buff *skb) ++{ ++ if (skb->ip_summed != CHECKSUM_PARTIAL) ++ return 0; ++ ++ if (!skb_is_gso(skb)) ++ return 0; ++ ++ DBGPR(" TSO packet to be processed\n"); ++ ++ return 1; ++} ++ ++static void xgbe_packet_info(struct xgbe_prv_data *pdata, ++ struct xgbe_ring *ring, struct sk_buff *skb, ++ struct xgbe_packet_data *packet) ++{ ++ struct skb_frag_struct *frag; ++ unsigned int context_desc; ++ unsigned int len; ++ unsigned int i; ++ ++ packet->skb = skb; ++ ++ context_desc = 0; ++ packet->rdesc_count = 0; ++ ++ packet->tx_packets = 1; ++ packet->tx_bytes = skb->len; ++ ++ if (xgbe_is_tso(skb)) { ++ /* TSO requires an extra descriptor if mss is different */ ++ if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { ++ context_desc = 1; ++ packet->rdesc_count++; ++ } ++ ++ /* TSO requires an extra descriptor for TSO header */ ++ packet->rdesc_count++; ++ ++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ TSO_ENABLE, 1); ++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ CSUM_ENABLE, 1); ++ } else if (skb->ip_summed == CHECKSUM_PARTIAL) ++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ CSUM_ENABLE, 1); ++ ++ if (skb_vlan_tag_present(skb)) { ++ /* VLAN requires an extra descriptor if tag is different */ ++ if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) ++ /* We can share with the TSO context descriptor */ ++ if (!context_desc) { ++ context_desc = 1; ++ packet->rdesc_count++; ++ } ++ ++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ VLAN_CTAG, 1); ++ } ++ ++ if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && ++ (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) ++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, ++ PTP, 1); ++ ++ for (len = skb_headlen(skb); len;) { ++ packet->rdesc_count++; ++ len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); ++ } ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ frag = &skb_shinfo(skb)->frags[i]; ++ for (len = skb_frag_size(frag); len; ) { ++ packet->rdesc_count++; ++ len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); ++ } ++ } ++} ++ ++static int xgbe_open(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ int ret; ++ ++ DBGPR("-->xgbe_open\n"); ++ ++ /* Initialize the phy */ ++ ret = xgbe_phy_init(pdata); ++ if (ret) ++ return ret; ++ ++ /* Enable the clocks */ ++ ret = clk_prepare_enable(pdata->sysclk); ++ if (ret) { ++ netdev_alert(netdev, "dma clk_prepare_enable failed\n"); ++ goto err_phy_init; ++ } ++ ++ ret = clk_prepare_enable(pdata->ptpclk); ++ if (ret) { ++ netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); ++ goto err_sysclk; ++ } ++ ++ /* Calculate the Rx buffer size before allocating rings */ ++ ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); ++ if (ret < 0) ++ goto err_ptpclk; ++ pdata->rx_buf_size = ret; ++ ++ /* Allocate the channel and ring structures */ ++ ret = xgbe_alloc_channels(pdata); ++ if (ret) ++ goto err_ptpclk; ++ ++ /* Allocate the ring descriptors and buffers */ ++ ret = desc_if->alloc_ring_resources(pdata); ++ if (ret) ++ goto err_channels; ++ ++ /* Initialize the device restart and Tx timestamp work struct */ ++ INIT_WORK(&pdata->restart_work, xgbe_restart); ++ INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); ++ ++ ret = xgbe_start(pdata); ++ if (ret) ++ goto err_rings; ++ ++ DBGPR("<--xgbe_open\n"); ++ ++ return 0; ++ ++err_rings: ++ desc_if->free_ring_resources(pdata); ++ ++err_channels: ++ xgbe_free_channels(pdata); ++ ++err_ptpclk: ++ clk_disable_unprepare(pdata->ptpclk); ++ ++err_sysclk: ++ clk_disable_unprepare(pdata->sysclk); ++ ++err_phy_init: ++ xgbe_phy_exit(pdata); ++ ++ return ret; ++} ++ ++static int xgbe_close(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ ++ DBGPR("-->xgbe_close\n"); ++ ++ /* Stop the device */ ++ xgbe_stop(pdata); ++ ++ /* Free the ring descriptors and buffers */ ++ desc_if->free_ring_resources(pdata); ++ ++ /* Free the channel and ring structures */ ++ xgbe_free_channels(pdata); ++ ++ /* Disable the clocks */ ++ clk_disable_unprepare(pdata->ptpclk); ++ clk_disable_unprepare(pdata->sysclk); ++ ++ /* Release the phy */ ++ xgbe_phy_exit(pdata); ++ ++ DBGPR("<--xgbe_close\n"); ++ ++ return 0; ++} ++ ++static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ struct xgbe_channel *channel; ++ struct xgbe_ring *ring; ++ struct xgbe_packet_data *packet; ++ struct netdev_queue *txq; ++ int ret; ++ ++ DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); ++ ++ channel = pdata->channel + skb->queue_mapping; ++ txq = netdev_get_tx_queue(netdev, channel->queue_index); ++ ring = channel->tx_ring; ++ packet = &ring->packet_data; ++ ++ ret = NETDEV_TX_OK; ++ ++ if (skb->len == 0) { ++ netdev_err(netdev, "empty skb received from stack\n"); ++ dev_kfree_skb_any(skb); ++ goto tx_netdev_return; ++ } ++ ++ /* Calculate preliminary packet info */ ++ memset(packet, 0, sizeof(*packet)); ++ xgbe_packet_info(pdata, ring, skb, packet); ++ ++ /* Check that there are enough descriptors available */ ++ ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); ++ if (ret) ++ goto tx_netdev_return; ++ ++ ret = xgbe_prep_tso(skb, packet); ++ if (ret) { ++ netdev_err(netdev, "error processing TSO packet\n"); ++ dev_kfree_skb_any(skb); ++ goto tx_netdev_return; ++ } ++ xgbe_prep_vlan(skb, packet); ++ ++ if (!desc_if->map_tx_skb(channel, skb)) { ++ dev_kfree_skb_any(skb); ++ goto tx_netdev_return; ++ } ++ ++ xgbe_prep_tx_tstamp(pdata, skb, packet); ++ ++ /* Report on the actual number of bytes (to be) sent */ ++ netdev_tx_sent_queue(txq, packet->tx_bytes); ++ ++ /* Configure required descriptor fields for transmission */ ++ hw_if->dev_xmit(channel); ++ ++#ifdef XGMAC_ENABLE_TX_PKT_DUMP ++ xgbe_a0_print_pkt(netdev, skb, true); ++#endif ++ ++ /* Stop the queue in advance if there may not be enough descriptors */ ++ xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); ++ ++ ret = NETDEV_TX_OK; ++ ++tx_netdev_return: ++ return ret; ++} ++ ++static void xgbe_set_rx_mode(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned int pr_mode, am_mode; ++ ++ DBGPR("-->xgbe_set_rx_mode\n"); ++ ++ pr_mode = ((netdev->flags & IFF_PROMISC) != 0); ++ am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); ++ ++ hw_if->set_promiscuous_mode(pdata, pr_mode); ++ hw_if->set_all_multicast_mode(pdata, am_mode); ++ ++ hw_if->add_mac_addresses(pdata); ++ ++ DBGPR("<--xgbe_set_rx_mode\n"); ++} ++ ++static int xgbe_set_mac_address(struct net_device *netdev, void *addr) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct sockaddr *saddr = addr; ++ ++ DBGPR("-->xgbe_set_mac_address\n"); ++ ++ if (!is_valid_ether_addr(saddr->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); ++ ++ hw_if->set_mac_address(pdata, netdev->dev_addr); ++ ++ DBGPR("<--xgbe_set_mac_address\n"); ++ ++ return 0; ++} ++ ++static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ int ret; ++ ++ switch (cmd) { ++ case SIOCGHWTSTAMP: ++ ret = xgbe_get_hwtstamp_settings(pdata, ifreq); ++ break; ++ ++ case SIOCSHWTSTAMP: ++ ret = xgbe_set_hwtstamp_settings(pdata, ifreq); ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ } ++ ++ return ret; ++} ++ ++static int xgbe_change_mtu(struct net_device *netdev, int mtu) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ int ret; ++ ++ DBGPR("-->xgbe_change_mtu\n"); ++ ++ ret = xgbe_calc_rx_buf_size(netdev, mtu); ++ if (ret < 0) ++ return ret; ++ ++ pdata->rx_buf_size = ret; ++ netdev->mtu = mtu; ++ ++ xgbe_restart_dev(pdata); ++ ++ DBGPR("<--xgbe_change_mtu\n"); ++ ++ return 0; ++} ++ ++static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, ++ struct rtnl_link_stats64 *s) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ pdata->hw_if.read_mmc_stats(pdata); ++ ++ s->rx_packets = pstats->rxframecount_gb; ++ s->rx_bytes = pstats->rxoctetcount_gb; ++ s->rx_errors = pstats->rxframecount_gb - ++ pstats->rxbroadcastframes_g - ++ pstats->rxmulticastframes_g - ++ pstats->rxunicastframes_g; ++ s->multicast = pstats->rxmulticastframes_g; ++ s->rx_length_errors = pstats->rxlengtherror; ++ s->rx_crc_errors = pstats->rxcrcerror; ++ s->rx_fifo_errors = pstats->rxfifooverflow; ++ ++ s->tx_packets = pstats->txframecount_gb; ++ s->tx_bytes = pstats->txoctetcount_gb; ++ s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; ++ s->tx_dropped = netdev->stats.tx_dropped; ++ ++ DBGPR("<--%s\n", __func__); ++ ++ return s; ++} ++ ++static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, ++ u16 vid) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ set_bit(vid, pdata->active_vlans); ++ hw_if->update_vlan_hash_table(pdata); ++ ++ DBGPR("<--%s\n", __func__); ++ ++ return 0; ++} ++ ++static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, ++ u16 vid) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ clear_bit(vid, pdata->active_vlans); ++ hw_if->update_vlan_hash_table(pdata); ++ ++ DBGPR("<--%s\n", __func__); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void xgbe_poll_controller(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_channel *channel; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_poll_controller\n"); ++ ++ if (pdata->per_channel_irq) { ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) ++ xgbe_dma_isr(channel->dma_irq, channel); ++ } else { ++ disable_irq(pdata->dev_irq); ++ xgbe_isr(pdata->dev_irq, pdata); ++ enable_irq(pdata->dev_irq); ++ } ++ ++ DBGPR("<--xgbe_poll_controller\n"); ++} ++#endif /* End CONFIG_NET_POLL_CONTROLLER */ ++ ++static int xgbe_setup_tc(struct net_device *netdev, u8 tc) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ unsigned int offset, queue; ++ u8 i; ++ ++ if (tc && (tc != pdata->hw_feat.tc_cnt)) ++ return -EINVAL; ++ ++ if (tc) { ++ netdev_set_num_tc(netdev, tc); ++ for (i = 0, queue = 0, offset = 0; i < tc; i++) { ++ while ((queue < pdata->tx_q_count) && ++ (pdata->q2tc_map[queue] == i)) ++ queue++; ++ ++ DBGPR(" TC%u using TXq%u-%u\n", i, offset, queue - 1); ++ netdev_set_tc_queue(netdev, i, queue - offset, offset); ++ offset = queue; ++ } ++ } else { ++ netdev_reset_tc(netdev); ++ } ++ ++ return 0; ++} ++ ++static int xgbe_set_features(struct net_device *netdev, ++ netdev_features_t features) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; ++ int ret = 0; ++ ++ rxhash = pdata->netdev_features & NETIF_F_RXHASH; ++ rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; ++ rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; ++ rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; ++ ++ if ((features & NETIF_F_RXHASH) && !rxhash) ++ ret = hw_if->enable_rss(pdata); ++ else if (!(features & NETIF_F_RXHASH) && rxhash) ++ ret = hw_if->disable_rss(pdata); ++ if (ret) ++ return ret; ++ ++ if ((features & NETIF_F_RXCSUM) && !rxcsum) ++ hw_if->enable_rx_csum(pdata); ++ else if (!(features & NETIF_F_RXCSUM) && rxcsum) ++ hw_if->disable_rx_csum(pdata); ++ ++ if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) ++ hw_if->enable_rx_vlan_stripping(pdata); ++ else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) ++ hw_if->disable_rx_vlan_stripping(pdata); ++ ++ if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) ++ hw_if->enable_rx_vlan_filtering(pdata); ++ else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) ++ hw_if->disable_rx_vlan_filtering(pdata); ++ ++ pdata->netdev_features = features; ++ ++ DBGPR("<--xgbe_set_features\n"); ++ ++ return 0; ++} ++ ++static const struct net_device_ops xgbe_netdev_ops = { ++ .ndo_open = xgbe_open, ++ .ndo_stop = xgbe_close, ++ .ndo_start_xmit = xgbe_xmit, ++ .ndo_set_rx_mode = xgbe_set_rx_mode, ++ .ndo_set_mac_address = xgbe_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_do_ioctl = xgbe_ioctl, ++ .ndo_change_mtu = xgbe_change_mtu, ++ .ndo_get_stats64 = xgbe_get_stats64, ++ .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, ++ .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = xgbe_poll_controller, ++#endif ++ .ndo_setup_tc = xgbe_setup_tc, ++ .ndo_set_features = xgbe_set_features, ++}; ++ ++struct net_device_ops *xgbe_a0_get_netdev_ops(void) ++{ ++ return (struct net_device_ops *)&xgbe_netdev_ops; ++} ++ ++static void xgbe_rx_refresh(struct xgbe_channel *channel) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ struct xgbe_ring *ring = channel->rx_ring; ++ struct xgbe_ring_data *rdata; ++ ++ while (ring->dirty != ring->cur) { ++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); ++ ++ /* Reset rdata values */ ++ desc_if->unmap_rdata(pdata, rdata); ++ ++ if (desc_if->map_rx_buffer(pdata, ring, rdata)) ++ break; ++ ++ hw_if->rx_desc_reset(rdata); ++ ++ ring->dirty++; ++ } ++ ++ /* Update the Rx Tail Pointer Register with address of ++ * the last cleaned entry */ ++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); ++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, ++ lower_32_bits(rdata->rdesc_dma)); ++} ++ ++static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, ++ struct xgbe_ring_data *rdata, ++ unsigned int *len) ++{ ++ struct net_device *netdev = pdata->netdev; ++ struct sk_buff *skb; ++ u8 *packet; ++ unsigned int copy_len; ++ ++ skb = netdev_alloc_skb_ip_align(netdev, rdata->rx.hdr.dma_len); ++ if (!skb) ++ return NULL; ++ ++ packet = page_address(rdata->rx.hdr.pa.pages) + ++ rdata->rx.hdr.pa.pages_offset; ++ copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : *len; ++ copy_len = min(rdata->rx.hdr.dma_len, copy_len); ++ skb_copy_to_linear_data(skb, packet, copy_len); ++ skb_put(skb, copy_len); ++ ++ *len -= copy_len; ++ ++ return skb; ++} ++ ++static int xgbe_tx_poll(struct xgbe_channel *channel) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_desc_if *desc_if = &pdata->desc_if; ++ struct xgbe_ring *ring = channel->tx_ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_ring_desc *rdesc; ++ struct net_device *netdev = pdata->netdev; ++ struct netdev_queue *txq; ++ int processed = 0; ++ unsigned int tx_packets = 0, tx_bytes = 0; ++ ++ DBGPR("-->xgbe_tx_poll\n"); ++ ++ /* Nothing to do if there isn't a Tx ring for this channel */ ++ if (!ring) ++ return 0; ++ ++ txq = netdev_get_tx_queue(netdev, channel->queue_index); ++ ++ while ((processed < XGBE_TX_DESC_MAX_PROC) && ++ (ring->dirty != ring->cur)) { ++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); ++ rdesc = rdata->rdesc; ++ ++ if (!hw_if->tx_complete(rdesc)) ++ break; ++ ++ /* Make sure descriptor fields are read after reading the OWN ++ * bit */ ++ rmb(); ++ ++#ifdef XGMAC_ENABLE_TX_DESC_DUMP ++ xgbe_a0_dump_tx_desc(ring, ring->dirty, 1, 0); ++#endif ++ ++ if (hw_if->is_last_desc(rdesc)) { ++ tx_packets += rdata->tx.packets; ++ tx_bytes += rdata->tx.bytes; ++ } ++ ++ /* Free the SKB and reset the descriptor for re-use */ ++ desc_if->unmap_rdata(pdata, rdata); ++ hw_if->tx_desc_reset(rdata); ++ ++ processed++; ++ ring->dirty++; ++ } ++ ++ if (!processed) ++ return 0; ++ ++ netdev_tx_completed_queue(txq, tx_packets, tx_bytes); ++ ++ if ((ring->tx.queue_stopped == 1) && ++ (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { ++ ring->tx.queue_stopped = 0; ++ netif_tx_wake_queue(txq); ++ } ++ ++ DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); ++ ++ return processed; ++} ++ ++static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) ++{ ++ struct xgbe_prv_data *pdata = channel->pdata; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ struct xgbe_ring *ring = channel->rx_ring; ++ struct xgbe_ring_data *rdata; ++ struct xgbe_packet_data *packet; ++ struct net_device *netdev = pdata->netdev; ++ struct napi_struct *napi; ++ struct sk_buff *skb; ++ struct skb_shared_hwtstamps *hwtstamps; ++ unsigned int incomplete, error, context_next, context; ++ unsigned int len, put_len, max_len; ++ unsigned int received = 0; ++ int packet_count = 0; ++ ++ DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); ++ ++ /* Nothing to do if there isn't a Rx ring for this channel */ ++ if (!ring) ++ return 0; ++ ++ napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; ++ ++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); ++ packet = &ring->packet_data; ++ while (packet_count < budget) { ++ DBGPR(" cur = %d\n", ring->cur); ++ ++ /* First time in loop see if we need to restore state */ ++ if (!received && rdata->state_saved) { ++ incomplete = rdata->state.incomplete; ++ context_next = rdata->state.context_next; ++ skb = rdata->state.skb; ++ error = rdata->state.error; ++ len = rdata->state.len; ++ } else { ++ memset(packet, 0, sizeof(*packet)); ++ incomplete = 0; ++ context_next = 0; ++ skb = NULL; ++ error = 0; ++ len = 0; ++ } ++ ++read_again: ++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); ++ ++ if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) ++ xgbe_rx_refresh(channel); ++ ++ if (hw_if->dev_read(channel)) ++ break; ++ ++ received++; ++ ring->cur++; ++ ++ incomplete = XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, ++ INCOMPLETE); ++ context_next = XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, ++ CONTEXT_NEXT); ++ context = XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, ++ CONTEXT); ++ ++ /* Earlier error, just drain the remaining data */ ++ if ((incomplete || context_next) && error) ++ goto read_again; ++ ++ if (error || packet->errors) { ++ if (packet->errors) ++ DBGPR("Error in received packet\n"); ++ dev_kfree_skb(skb); ++ goto next_packet; ++ } ++ ++ if (!context) { ++ put_len = rdata->rx.len - len; ++ len += put_len; ++ ++ if (!skb) { ++ dma_sync_single_for_cpu(pdata->dev, ++ rdata->rx.hdr.dma, ++ rdata->rx.hdr.dma_len, ++ DMA_FROM_DEVICE); ++ ++ skb = xgbe_create_skb(pdata, rdata, &put_len); ++ if (!skb) { ++ error = 1; ++ goto skip_data; ++ } ++ } ++ ++ if (put_len) { ++ dma_sync_single_for_cpu(pdata->dev, ++ rdata->rx.buf.dma, ++ rdata->rx.buf.dma_len, ++ DMA_FROM_DEVICE); ++ ++ skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, ++ rdata->rx.buf.pa.pages, ++ rdata->rx.buf.pa.pages_offset, ++ put_len, rdata->rx.buf.dma_len); ++ rdata->rx.buf.pa.pages = NULL; ++ } ++ } ++ ++skip_data: ++ if (incomplete || context_next) ++ goto read_again; ++ ++ if (!skb) ++ goto next_packet; ++ ++ /* Be sure we don't exceed the configured MTU */ ++ max_len = netdev->mtu + ETH_HLEN; ++ if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && ++ (skb->protocol == htons(ETH_P_8021Q))) ++ max_len += VLAN_HLEN; ++ ++ if (skb->len > max_len) { ++ DBGPR("packet length exceeds configured MTU\n"); ++ dev_kfree_skb(skb); ++ goto next_packet; ++ } ++ ++#ifdef XGMAC_ENABLE_RX_PKT_DUMP ++ xgbe_a0_print_pkt(netdev, skb, false); ++#endif ++ ++ skb_checksum_none_assert(skb); ++ if (XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, CSUM_DONE)) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ ++ if (XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, VLAN_CTAG)) ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ++ packet->vlan_ctag); ++ ++ if (XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { ++ u64 nsec; ++ ++ nsec = timecounter_cyc2time(&pdata->tstamp_tc, ++ packet->rx_tstamp); ++ hwtstamps = skb_hwtstamps(skb); ++ hwtstamps->hwtstamp = ns_to_ktime(nsec); ++ } ++ ++ if (XGMAC_GET_BITS(packet->attributes, ++ RX_PACKET_ATTRIBUTES, RSS_HASH)) ++ skb_set_hash(skb, packet->rss_hash, ++ packet->rss_hash_type); ++ ++ skb->dev = netdev; ++ skb->protocol = eth_type_trans(skb, netdev); ++ skb_record_rx_queue(skb, channel->queue_index); ++ skb_mark_napi_id(skb, napi); ++ ++ netdev->last_rx = jiffies; ++ napi_gro_receive(napi, skb); ++ ++next_packet: ++ packet_count++; ++ } ++ ++ /* Check if we need to save state before leaving */ ++ if (received && (incomplete || context_next)) { ++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); ++ rdata->state_saved = 1; ++ rdata->state.incomplete = incomplete; ++ rdata->state.context_next = context_next; ++ rdata->state.skb = skb; ++ rdata->state.len = len; ++ rdata->state.error = error; ++ } ++ ++ DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); ++ ++ return packet_count; ++} ++ ++static int xgbe_one_poll(struct napi_struct *napi, int budget) ++{ ++ struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, ++ napi); ++ int processed = 0; ++ ++ DBGPR("-->xgbe_one_poll: budget=%d\n", budget); ++ ++ /* Cleanup Tx ring first */ ++ xgbe_tx_poll(channel); ++ ++ /* Process Rx ring next */ ++ processed = xgbe_rx_poll(channel, budget); ++ ++ /* If we processed everything, we are done */ ++ if (processed < budget) { ++ /* Turn off polling */ ++ napi_complete(napi); ++ ++ /* Enable Tx and Rx interrupts */ ++ enable_irq(channel->dma_irq); ++ } ++ ++ DBGPR("<--xgbe_one_poll: received = %d\n", processed); ++ ++ return processed; ++} ++ ++static int xgbe_all_poll(struct napi_struct *napi, int budget) ++{ ++ struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, ++ napi); ++ struct xgbe_channel *channel; ++ int ring_budget; ++ int processed, last_processed; ++ unsigned int i; ++ ++ DBGPR("-->xgbe_all_poll: budget=%d\n", budget); ++ ++ processed = 0; ++ ring_budget = budget / pdata->rx_ring_count; ++ do { ++ last_processed = processed; ++ ++ channel = pdata->channel; ++ for (i = 0; i < pdata->channel_count; i++, channel++) { ++ /* Cleanup Tx ring first */ ++ xgbe_tx_poll(channel); ++ ++ /* Process Rx ring next */ ++ if (ring_budget > (budget - processed)) ++ ring_budget = budget - processed; ++ processed += xgbe_rx_poll(channel, ring_budget); ++ } ++ } while ((processed < budget) && (processed != last_processed)); ++ ++ /* If we processed everything, we are done */ ++ if (processed < budget) { ++ /* Turn off polling */ ++ napi_complete(napi); ++ ++ /* Enable Tx and Rx interrupts */ ++ xgbe_enable_rx_tx_ints(pdata); ++ } ++ ++ DBGPR("<--xgbe_all_poll: received = %d\n", processed); ++ ++ return processed; ++} ++ ++void xgbe_a0_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx, ++ unsigned int count, unsigned int flag) ++{ ++ struct xgbe_ring_data *rdata; ++ struct xgbe_ring_desc *rdesc; ++ ++ while (count--) { ++ rdata = XGBE_GET_DESC_DATA(ring, idx); ++ rdesc = rdata->rdesc; ++ pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, ++ (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", ++ le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), ++ le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); ++ idx++; ++ } ++} ++ ++void xgbe_a0_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc, ++ unsigned int idx) ++{ ++ pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx, ++ le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1), ++ le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3)); ++} ++ ++void xgbe_a0_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) ++{ ++ struct ethhdr *eth = (struct ethhdr *)skb->data; ++ unsigned char *buf = skb->data; ++ unsigned char buffer[128]; ++ unsigned int i, j; ++ ++ netdev_alert(netdev, "\n************** SKB dump ****************\n"); ++ ++ netdev_alert(netdev, "%s packet of %d bytes\n", ++ (tx_rx ? "TX" : "RX"), skb->len); ++ ++ netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest); ++ netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source); ++ netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto)); ++ ++ for (i = 0, j = 0; i < skb->len;) { ++ j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", ++ buf[i++]); ++ ++ if ((i % 32) == 0) { ++ netdev_alert(netdev, " 0x%04x: %s\n", i - 32, buffer); ++ j = 0; ++ } else if ((i % 16) == 0) { ++ buffer[j++] = ' '; ++ buffer[j++] = ' '; ++ } else if ((i % 4) == 0) { ++ buffer[j++] = ' '; ++ } ++ } ++ if (i % 32) ++ netdev_alert(netdev, " 0x%04x: %s\n", i - (i % 32), buffer); ++ ++ netdev_alert(netdev, "\n************** SKB dump ****************\n"); ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c +new file mode 100644 +index 0000000..165ff1c +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c +@@ -0,0 +1,616 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++struct xgbe_stats { ++ char stat_string[ETH_GSTRING_LEN]; ++ int stat_size; ++ int stat_offset; ++}; ++ ++#define XGMAC_MMC_STAT(_string, _var) \ ++ { _string, \ ++ FIELD_SIZEOF(struct xgbe_mmc_stats, _var), \ ++ offsetof(struct xgbe_prv_data, mmc_stats._var), \ ++ } ++ ++static const struct xgbe_stats xgbe_gstring_stats[] = { ++ XGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), ++ XGMAC_MMC_STAT("tx_packets", txframecount_gb), ++ XGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), ++ XGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), ++ XGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), ++ XGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), ++ XGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), ++ XGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), ++ XGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), ++ XGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), ++ XGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), ++ XGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), ++ XGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), ++ XGMAC_MMC_STAT("tx_pause_frames", txpauseframes), ++ ++ XGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), ++ XGMAC_MMC_STAT("rx_packets", rxframecount_gb), ++ XGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), ++ XGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), ++ XGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), ++ XGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), ++ XGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), ++ XGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), ++ XGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), ++ XGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), ++ XGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), ++ XGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), ++ XGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), ++ XGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), ++ XGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), ++ XGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), ++ XGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), ++ XGMAC_MMC_STAT("rx_length_errors", rxlengtherror), ++ XGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), ++ XGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), ++ XGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), ++ XGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), ++}; ++ ++#define XGBE_STATS_COUNT ARRAY_SIZE(xgbe_gstring_stats) ++ ++static void xgbe_get_strings(struct net_device *netdev, u32 stringset, u8 *data) ++{ ++ int i; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ switch (stringset) { ++ case ETH_SS_STATS: ++ for (i = 0; i < XGBE_STATS_COUNT; i++) { ++ memcpy(data, xgbe_gstring_stats[i].stat_string, ++ ETH_GSTRING_LEN); ++ data += ETH_GSTRING_LEN; ++ } ++ break; ++ } ++ ++ DBGPR("<--%s\n", __func__); ++} ++ ++static void xgbe_get_ethtool_stats(struct net_device *netdev, ++ struct ethtool_stats *stats, u64 *data) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ u8 *stat; ++ int i; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ pdata->hw_if.read_mmc_stats(pdata); ++ for (i = 0; i < XGBE_STATS_COUNT; i++) { ++ stat = (u8 *)pdata + xgbe_gstring_stats[i].stat_offset; ++ *data++ = *(u64 *)stat; ++ } ++ ++ DBGPR("<--%s\n", __func__); ++} ++ ++static int xgbe_get_sset_count(struct net_device *netdev, int stringset) ++{ ++ int ret; ++ ++ DBGPR("-->%s\n", __func__); ++ ++ switch (stringset) { ++ case ETH_SS_STATS: ++ ret = XGBE_STATS_COUNT; ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ } ++ ++ DBGPR("<--%s\n", __func__); ++ ++ return ret; ++} ++ ++static void xgbe_get_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ DBGPR("-->xgbe_get_pauseparam\n"); ++ ++ pause->autoneg = pdata->pause_autoneg; ++ pause->tx_pause = pdata->tx_pause; ++ pause->rx_pause = pdata->rx_pause; ++ ++ DBGPR("<--xgbe_get_pauseparam\n"); ++} ++ ++static int xgbe_set_pauseparam(struct net_device *netdev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct phy_device *phydev = pdata->phydev; ++ int ret = 0; ++ ++ DBGPR("-->xgbe_set_pauseparam\n"); ++ ++ DBGPR(" autoneg = %d, tx_pause = %d, rx_pause = %d\n", ++ pause->autoneg, pause->tx_pause, pause->rx_pause); ++ ++ pdata->pause_autoneg = pause->autoneg; ++ if (pause->autoneg) { ++ phydev->advertising |= ADVERTISED_Pause; ++ phydev->advertising |= ADVERTISED_Asym_Pause; ++ ++ } else { ++ phydev->advertising &= ~ADVERTISED_Pause; ++ phydev->advertising &= ~ADVERTISED_Asym_Pause; ++ ++ pdata->tx_pause = pause->tx_pause; ++ pdata->rx_pause = pause->rx_pause; ++ } ++ ++ if (netif_running(netdev)) ++ ret = phy_start_aneg(phydev); ++ ++ DBGPR("<--xgbe_set_pauseparam\n"); ++ ++ return ret; ++} ++ ++static int xgbe_get_settings(struct net_device *netdev, ++ struct ethtool_cmd *cmd) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ int ret; ++ ++ DBGPR("-->xgbe_get_settings\n"); ++ ++ if (!pdata->phydev) ++ return -ENODEV; ++ ++ ret = phy_ethtool_gset(pdata->phydev, cmd); ++ cmd->transceiver = XCVR_EXTERNAL; ++ ++ DBGPR("<--xgbe_get_settings\n"); ++ ++ return ret; ++} ++ ++static int xgbe_set_settings(struct net_device *netdev, ++ struct ethtool_cmd *cmd) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct phy_device *phydev = pdata->phydev; ++ u32 speed; ++ int ret; ++ ++ DBGPR("-->xgbe_set_settings\n"); ++ ++ if (!pdata->phydev) ++ return -ENODEV; ++ ++ speed = ethtool_cmd_speed(cmd); ++ ++ if (cmd->phy_address != phydev->addr) ++ return -EINVAL; ++ ++ if ((cmd->autoneg != AUTONEG_ENABLE) && ++ (cmd->autoneg != AUTONEG_DISABLE)) ++ return -EINVAL; ++ ++ if (cmd->autoneg == AUTONEG_DISABLE) { ++ switch (speed) { ++ case SPEED_10000: ++ case SPEED_2500: ++ case SPEED_1000: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (cmd->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ } ++ ++ cmd->advertising &= phydev->supported; ++ if ((cmd->autoneg == AUTONEG_ENABLE) && !cmd->advertising) ++ return -EINVAL; ++ ++ ret = 0; ++ phydev->autoneg = cmd->autoneg; ++ phydev->speed = speed; ++ phydev->duplex = cmd->duplex; ++ phydev->advertising = cmd->advertising; ++ ++ if (cmd->autoneg == AUTONEG_ENABLE) ++ phydev->advertising |= ADVERTISED_Autoneg; ++ else ++ phydev->advertising &= ~ADVERTISED_Autoneg; ++ ++ if (netif_running(netdev)) ++ ret = phy_start_aneg(phydev); ++ ++ DBGPR("<--xgbe_set_settings\n"); ++ ++ return ret; ++} ++ ++static void xgbe_get_drvinfo(struct net_device *netdev, ++ struct ethtool_drvinfo *drvinfo) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_features *hw_feat = &pdata->hw_feat; ++ ++ strlcpy(drvinfo->driver, XGBE_DRV_NAME, sizeof(drvinfo->driver)); ++ strlcpy(drvinfo->version, XGBE_DRV_VERSION, sizeof(drvinfo->version)); ++ strlcpy(drvinfo->bus_info, dev_name(pdata->dev), ++ sizeof(drvinfo->bus_info)); ++ snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "%d.%d.%d", ++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER), ++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID), ++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER)); ++ drvinfo->n_stats = XGBE_STATS_COUNT; ++} ++ ++static int xgbe_get_coalesce(struct net_device *netdev, ++ struct ethtool_coalesce *ec) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned int riwt; ++ ++ DBGPR("-->xgbe_get_coalesce\n"); ++ ++ memset(ec, 0, sizeof(struct ethtool_coalesce)); ++ ++ riwt = pdata->rx_riwt; ++ ec->rx_coalesce_usecs = hw_if->riwt_to_usec(pdata, riwt); ++ ec->rx_max_coalesced_frames = pdata->rx_frames; ++ ++ ec->tx_coalesce_usecs = pdata->tx_usecs; ++ ec->tx_max_coalesced_frames = pdata->tx_frames; ++ ++ DBGPR("<--xgbe_get_coalesce\n"); ++ ++ return 0; ++} ++ ++static int xgbe_set_coalesce(struct net_device *netdev, ++ struct ethtool_coalesce *ec) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned int rx_frames, rx_riwt, rx_usecs; ++ unsigned int tx_frames, tx_usecs; ++ ++ DBGPR("-->xgbe_set_coalesce\n"); ++ ++ /* Check for not supported parameters */ ++ if ((ec->rx_coalesce_usecs_irq) || ++ (ec->rx_max_coalesced_frames_irq) || ++ (ec->tx_coalesce_usecs_irq) || ++ (ec->tx_max_coalesced_frames_irq) || ++ (ec->stats_block_coalesce_usecs) || ++ (ec->use_adaptive_rx_coalesce) || ++ (ec->use_adaptive_tx_coalesce) || ++ (ec->pkt_rate_low) || ++ (ec->rx_coalesce_usecs_low) || ++ (ec->rx_max_coalesced_frames_low) || ++ (ec->tx_coalesce_usecs_low) || ++ (ec->tx_max_coalesced_frames_low) || ++ (ec->pkt_rate_high) || ++ (ec->rx_coalesce_usecs_high) || ++ (ec->rx_max_coalesced_frames_high) || ++ (ec->tx_coalesce_usecs_high) || ++ (ec->tx_max_coalesced_frames_high) || ++ (ec->rate_sample_interval)) ++ return -EOPNOTSUPP; ++ ++ /* Can only change rx-frames when interface is down (see ++ * rx_descriptor_init in xgbe-dev.c) ++ */ ++ rx_frames = pdata->rx_frames; ++ if (rx_frames != ec->rx_max_coalesced_frames && netif_running(netdev)) { ++ netdev_alert(netdev, ++ "interface must be down to change rx-frames\n"); ++ return -EINVAL; ++ } ++ ++ rx_riwt = hw_if->usec_to_riwt(pdata, ec->rx_coalesce_usecs); ++ rx_frames = ec->rx_max_coalesced_frames; ++ ++ /* Use smallest possible value if conversion resulted in zero */ ++ if (ec->rx_coalesce_usecs && !rx_riwt) ++ rx_riwt = 1; ++ ++ /* Check the bounds of values for Rx */ ++ if (rx_riwt > XGMAC_MAX_DMA_RIWT) { ++ rx_usecs = hw_if->riwt_to_usec(pdata, XGMAC_MAX_DMA_RIWT); ++ netdev_alert(netdev, "rx-usec is limited to %d usecs\n", ++ rx_usecs); ++ return -EINVAL; ++ } ++ if (rx_frames > pdata->rx_desc_count) { ++ netdev_alert(netdev, "rx-frames is limited to %d frames\n", ++ pdata->rx_desc_count); ++ return -EINVAL; ++ } ++ ++ tx_usecs = ec->tx_coalesce_usecs; ++ tx_frames = ec->tx_max_coalesced_frames; ++ ++ /* Check the bounds of values for Tx */ ++ if (tx_frames > pdata->tx_desc_count) { ++ netdev_alert(netdev, "tx-frames is limited to %d frames\n", ++ pdata->tx_desc_count); ++ return -EINVAL; ++ } ++ ++ pdata->rx_riwt = rx_riwt; ++ pdata->rx_frames = rx_frames; ++ hw_if->config_rx_coalesce(pdata); ++ ++ pdata->tx_usecs = tx_usecs; ++ pdata->tx_frames = tx_frames; ++ hw_if->config_tx_coalesce(pdata); ++ ++ DBGPR("<--xgbe_set_coalesce\n"); ++ ++ return 0; ++} ++ ++static int xgbe_get_rxnfc(struct net_device *netdev, ++ struct ethtool_rxnfc *rxnfc, u32 *rule_locs) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ switch (rxnfc->cmd) { ++ case ETHTOOL_GRXRINGS: ++ rxnfc->data = pdata->rx_ring_count; ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static u32 xgbe_get_rxfh_key_size(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ return sizeof(pdata->rss_key); ++} ++ ++static u32 xgbe_get_rxfh_indir_size(struct net_device *netdev) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ return ARRAY_SIZE(pdata->rss_table); ++} ++ ++static int xgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, ++ u8 *hfunc) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ unsigned int i; ++ ++ if (indir) { ++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) ++ indir[i] = XGMAC_GET_BITS(pdata->rss_table[i], ++ MAC_RSSDR, DMCH); ++ } ++ ++ if (key) ++ memcpy(key, pdata->rss_key, sizeof(pdata->rss_key)); ++ ++ if (hfunc) ++ *hfunc = ETH_RSS_HASH_TOP; ++ ++ return 0; ++} ++ ++static int xgbe_set_rxfh(struct net_device *netdev, const u32 *indir, ++ const u8 *key, const u8 hfunc) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ unsigned int ret; ++ ++ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) ++ return -EOPNOTSUPP; ++ ++ if (indir) { ++ ret = hw_if->set_rss_lookup_table(pdata, indir); ++ if (ret) ++ return ret; ++ } ++ ++ if (key) { ++ ret = hw_if->set_rss_hash_key(pdata, key); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int xgbe_get_ts_info(struct net_device *netdev, ++ struct ethtool_ts_info *ts_info) ++{ ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | ++ SOF_TIMESTAMPING_RX_SOFTWARE | ++ SOF_TIMESTAMPING_SOFTWARE | ++ SOF_TIMESTAMPING_TX_HARDWARE | ++ SOF_TIMESTAMPING_RX_HARDWARE | ++ SOF_TIMESTAMPING_RAW_HARDWARE; ++ ++ if (pdata->ptp_clock) ++ ts_info->phc_index = ptp_clock_index(pdata->ptp_clock); ++ else ++ ts_info->phc_index = -1; ++ ++ ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); ++ ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | ++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | ++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | ++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | ++ (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | ++ (1 << HWTSTAMP_FILTER_ALL); ++ ++ return 0; ++} ++ ++static const struct ethtool_ops xgbe_ethtool_ops = { ++ .get_settings = xgbe_get_settings, ++ .set_settings = xgbe_set_settings, ++ .get_drvinfo = xgbe_get_drvinfo, ++ .get_link = ethtool_op_get_link, ++ .get_coalesce = xgbe_get_coalesce, ++ .set_coalesce = xgbe_set_coalesce, ++ .get_pauseparam = xgbe_get_pauseparam, ++ .set_pauseparam = xgbe_set_pauseparam, ++ .get_strings = xgbe_get_strings, ++ .get_ethtool_stats = xgbe_get_ethtool_stats, ++ .get_sset_count = xgbe_get_sset_count, ++ .get_rxnfc = xgbe_get_rxnfc, ++ .get_rxfh_key_size = xgbe_get_rxfh_key_size, ++ .get_rxfh_indir_size = xgbe_get_rxfh_indir_size, ++ .get_rxfh = xgbe_get_rxfh, ++ .set_rxfh = xgbe_set_rxfh, ++ .get_ts_info = xgbe_get_ts_info, ++}; ++ ++struct ethtool_ops *xgbe_a0_get_ethtool_ops(void) ++{ ++ return (struct ethtool_ops *)&xgbe_ethtool_ops; ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c +new file mode 100644 +index 0000000..deb8551 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c +@@ -0,0 +1,618 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++MODULE_AUTHOR("Tom Lendacky "); ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_VERSION(XGBE_DRV_VERSION); ++MODULE_DESCRIPTION(XGBE_DRV_DESC); ++ ++unsigned int speed = 0; ++module_param(speed, uint, 0444); ++MODULE_PARM_DESC(speed, " Select operating speed (1=1GbE, 2=2.5GbE, 10=10GbE, any other value implies auto-negotiation"); ++ ++static void xgbe_default_config(struct xgbe_prv_data *pdata) ++{ ++ DBGPR("-->xgbe_default_config\n"); ++ ++ pdata->pblx8 = DMA_PBL_X8_ENABLE; ++ pdata->tx_sf_mode = MTL_TSF_ENABLE; ++ pdata->tx_threshold = MTL_TX_THRESHOLD_64; ++ pdata->tx_pbl = DMA_PBL_16; ++ pdata->tx_osp_mode = DMA_OSP_ENABLE; ++ pdata->rx_sf_mode = MTL_RSF_DISABLE; ++ pdata->rx_threshold = MTL_RX_THRESHOLD_64; ++ pdata->rx_pbl = DMA_PBL_16; ++ pdata->pause_autoneg = 1; ++ pdata->tx_pause = 1; ++ pdata->rx_pause = 1; ++ pdata->phy_speed = SPEED_UNKNOWN; ++ pdata->power_down = 0; ++ ++ if (speed == 10) { ++ pdata->default_autoneg = AUTONEG_DISABLE; ++ pdata->default_speed = SPEED_10000; ++ } else if (speed == 2) { ++ pdata->default_autoneg = AUTONEG_DISABLE; ++ pdata->default_speed = SPEED_2500; ++ } else if (speed == 1) { ++ pdata->default_autoneg = AUTONEG_DISABLE; ++ pdata->default_speed = SPEED_1000; ++ } else { ++ pdata->default_autoneg = AUTONEG_ENABLE; ++ pdata->default_speed = SPEED_10000; ++ } ++ ++ DBGPR("<--xgbe_default_config\n"); ++} ++ ++static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata) ++{ ++ xgbe_a0_init_function_ptrs_dev(&pdata->hw_if); ++ xgbe_a0_init_function_ptrs_desc(&pdata->desc_if); ++} ++ ++#ifdef CONFIG_ACPI ++static int xgbe_acpi_support(struct xgbe_prv_data *pdata) ++{ ++ struct device *dev = pdata->dev; ++ u32 property; ++ int ret; ++ ++ /* Obtain the system clock setting */ ++ ret = device_property_read_u32(dev, XGBE_ACPI_DMA_FREQ, &property); ++ if (ret) { ++ dev_err(dev, "unable to obtain %s property\n", ++ XGBE_ACPI_DMA_FREQ); ++ return ret; ++ } ++ pdata->sysclk_rate = property; ++ ++ /* Obtain the PTP clock setting */ ++ ret = device_property_read_u32(dev, XGBE_ACPI_PTP_FREQ, &property); ++ if (ret) { ++ dev_err(dev, "unable to obtain %s property\n", ++ XGBE_ACPI_PTP_FREQ); ++ return ret; ++ } ++ pdata->ptpclk_rate = property; ++ ++ return 0; ++} ++#else /* CONFIG_ACPI */ ++static int xgbe_acpi_support(struct xgbe_prv_data *pdata) ++{ ++ return -EINVAL; ++} ++#endif /* CONFIG_ACPI */ ++ ++#ifdef CONFIG_OF ++static int xgbe_of_support(struct xgbe_prv_data *pdata) ++{ ++ struct device *dev = pdata->dev; ++ ++ /* Obtain the system clock setting */ ++ pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK); ++ if (IS_ERR(pdata->sysclk)) { ++ dev_err(dev, "dma devm_clk_get failed\n"); ++ return PTR_ERR(pdata->sysclk); ++ } ++ pdata->sysclk_rate = clk_get_rate(pdata->sysclk); ++ ++ /* Obtain the PTP clock setting */ ++ pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK); ++ if (IS_ERR(pdata->ptpclk)) { ++ dev_err(dev, "ptp devm_clk_get failed\n"); ++ return PTR_ERR(pdata->ptpclk); ++ } ++ pdata->ptpclk_rate = clk_get_rate(pdata->ptpclk); ++ ++ return 0; ++} ++#else /* CONFIG_OF */ ++static int xgbe_of_support(struct xgbe_prv_data *pdata) ++{ ++ return -EINVAL; ++} ++#endif /*CONFIG_OF */ ++ ++static int xgbe_probe(struct platform_device *pdev) ++{ ++ struct xgbe_prv_data *pdata; ++ struct xgbe_hw_if *hw_if; ++ struct xgbe_desc_if *desc_if; ++ struct net_device *netdev; ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ const char *phy_mode; ++ unsigned int i; ++ int ret; ++ ++ DBGPR("--> xgbe_probe\n"); ++ ++ netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data), ++ XGBE_MAX_DMA_CHANNELS); ++ if (!netdev) { ++ dev_err(dev, "alloc_etherdev failed\n"); ++ ret = -ENOMEM; ++ goto err_alloc; ++ } ++ SET_NETDEV_DEV(netdev, dev); ++ pdata = netdev_priv(netdev); ++ pdata->netdev = netdev; ++ pdata->pdev = pdev; ++ pdata->adev = ACPI_COMPANION(dev); ++ pdata->dev = dev; ++ platform_set_drvdata(pdev, netdev); ++ ++ spin_lock_init(&pdata->lock); ++ mutex_init(&pdata->xpcs_mutex); ++ mutex_init(&pdata->rss_mutex); ++ spin_lock_init(&pdata->tstamp_lock); ++ ++ /* Check if we should use ACPI or DT */ ++ pdata->use_acpi = (!pdata->adev || acpi_disabled) ? 0 : 1; ++ ++ /* Set and validate the number of descriptors for a ring */ ++ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT); ++ pdata->tx_desc_count = XGBE_TX_DESC_CNT; ++ if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) { ++ dev_err(dev, "tx descriptor count (%d) is not valid\n", ++ pdata->tx_desc_count); ++ ret = -EINVAL; ++ goto err_io; ++ } ++ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT); ++ pdata->rx_desc_count = XGBE_RX_DESC_CNT; ++ if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) { ++ dev_err(dev, "rx descriptor count (%d) is not valid\n", ++ pdata->rx_desc_count); ++ ret = -EINVAL; ++ goto err_io; ++ } ++ ++ /* Obtain the mmio areas for the device */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ pdata->xgmac_regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pdata->xgmac_regs)) { ++ dev_err(dev, "xgmac ioremap failed\n"); ++ ret = PTR_ERR(pdata->xgmac_regs); ++ goto err_io; ++ } ++ DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ pdata->xpcs_regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pdata->xpcs_regs)) { ++ dev_err(dev, "xpcs ioremap failed\n"); ++ ret = PTR_ERR(pdata->xpcs_regs); ++ goto err_io; ++ } ++ DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs); ++ ++ /* Retrieve the MAC address */ ++ ret = device_property_read_u8_array(dev, XGBE_MAC_ADDR_PROPERTY, ++ pdata->mac_addr, ++ sizeof(pdata->mac_addr)); ++ if (ret || !is_valid_ether_addr(pdata->mac_addr)) { ++ dev_err(dev, "invalid %s property\n", XGBE_MAC_ADDR_PROPERTY); ++ if (!ret) ++ ret = -EINVAL; ++ goto err_io; ++ } ++ ++ /* Retrieve the PHY mode - it must be "xgmii" */ ++ ret = device_property_read_string(dev, XGBE_PHY_MODE_PROPERTY, ++ &phy_mode); ++ if (ret || strcmp(phy_mode, phy_modes(PHY_INTERFACE_MODE_XGMII))) { ++ dev_err(dev, "invalid %s property\n", XGBE_PHY_MODE_PROPERTY); ++ if (!ret) ++ ret = -EINVAL; ++ goto err_io; ++ } ++ pdata->phy_mode = PHY_INTERFACE_MODE_XGMII; ++ ++ /* Check for per channel interrupt support */ ++ if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) ++ pdata->per_channel_irq = 1; ++ ++ /* Obtain device settings unique to ACPI/OF */ ++ if (pdata->use_acpi) ++ ret = xgbe_acpi_support(pdata); ++ else ++ ret = xgbe_of_support(pdata); ++ if (ret) ++ goto err_io; ++ ++ /* Set the DMA coherency values */ ++ pdata->coherent = device_dma_is_coherent(pdata->dev); ++ if (pdata->coherent) { ++ pdata->axdomain = XGBE_DMA_OS_AXDOMAIN; ++ pdata->arcache = XGBE_DMA_OS_ARCACHE; ++ pdata->awcache = XGBE_DMA_OS_AWCACHE; ++ } else { ++ pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN; ++ pdata->arcache = XGBE_DMA_SYS_ARCACHE; ++ pdata->awcache = XGBE_DMA_SYS_AWCACHE; ++ } ++ ++ /* Set the DMA mask */ ++ if (!dev->dma_mask) ++ dev->dma_mask = &dev->coherent_dma_mask; ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); ++ if (ret) { ++ dev_err(dev, "dma_set_mask_and_coherent failed\n"); ++ goto err_io; ++ } ++ ++ /* Get the device interrupt */ ++ ret = platform_get_irq(pdev, 0); ++ if (ret < 0) { ++ dev_err(dev, "platform_get_irq 0 failed\n"); ++ goto err_io; ++ } ++ pdata->dev_irq = ret; ++ ++ netdev->irq = pdata->dev_irq; ++ netdev->base_addr = (unsigned long)pdata->xgmac_regs; ++ memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len); ++ ++ /* Set all the function pointers */ ++ xgbe_init_all_fptrs(pdata); ++ hw_if = &pdata->hw_if; ++ desc_if = &pdata->desc_if; ++ ++ /* Issue software reset to device */ ++ hw_if->exit(pdata); ++ ++ /* Populate the hardware features */ ++ xgbe_a0_get_all_hw_features(pdata); ++ ++ /* Set default configuration data */ ++ xgbe_default_config(pdata); ++ ++ /* Calculate the number of Tx and Rx rings to be created ++ * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set ++ * the number of Tx queues to the number of Tx channels ++ * enabled ++ * -Rx (DMA) Channels do not map 1-to-1 so use the actual ++ * number of Rx queues ++ */ ++ pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(), ++ pdata->hw_feat.tx_ch_cnt); ++ pdata->tx_q_count = pdata->tx_ring_count; ++ ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count); ++ if (ret) { ++ dev_err(dev, "error setting real tx queue count\n"); ++ goto err_io; ++ } ++ ++ pdata->rx_ring_count = min_t(unsigned int, ++ netif_get_num_default_rss_queues(), ++ pdata->hw_feat.rx_ch_cnt); ++ pdata->rx_q_count = pdata->hw_feat.rx_q_cnt; ++ ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count); ++ if (ret) { ++ dev_err(dev, "error setting real rx queue count\n"); ++ goto err_io; ++ } ++ ++ /* Initialize RSS hash key and lookup table */ ++ netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key)); ++ ++ for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) ++ XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, ++ i % pdata->rx_ring_count); ++ ++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); ++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); ++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); ++ ++ /* Prepare to regsiter with MDIO */ ++ pdata->mii_bus_id = kasprintf(GFP_KERNEL, "%s", pdev->name); ++ if (!pdata->mii_bus_id) { ++ dev_err(dev, "failed to allocate mii bus id\n"); ++ ret = -ENOMEM; ++ goto err_io; ++ } ++ ret = xgbe_a0_mdio_register(pdata); ++ if (ret) ++ goto err_bus_id; ++ ++ /* Set device operations */ ++ netdev->netdev_ops = xgbe_a0_get_netdev_ops(); ++ netdev->ethtool_ops = xgbe_a0_get_ethtool_ops(); ++#ifdef CONFIG_AMD_XGBE_DCB ++ netdev->dcbnl_ops = xgbe_a0_get_dcbnl_ops(); ++#endif ++ ++ /* Set device features */ ++ netdev->hw_features = NETIF_F_SG | ++ NETIF_F_IP_CSUM | ++ NETIF_F_IPV6_CSUM | ++ NETIF_F_RXCSUM | ++ NETIF_F_TSO | ++ NETIF_F_TSO6 | ++ NETIF_F_GRO | ++ NETIF_F_HW_VLAN_CTAG_RX | ++ NETIF_F_HW_VLAN_CTAG_TX | ++ NETIF_F_HW_VLAN_CTAG_FILTER; ++ ++ if (pdata->hw_feat.rss) ++ netdev->hw_features |= NETIF_F_RXHASH; ++ ++ netdev->vlan_features |= NETIF_F_SG | ++ NETIF_F_IP_CSUM | ++ NETIF_F_IPV6_CSUM | ++ NETIF_F_TSO | ++ NETIF_F_TSO6; ++ ++ netdev->features |= netdev->hw_features; ++ pdata->netdev_features = netdev->features; ++ ++ netdev->priv_flags |= IFF_UNICAST_FLT; ++ ++ xgbe_a0_init_rx_coalesce(pdata); ++ xgbe_a0_init_tx_coalesce(pdata); ++ ++ netif_carrier_off(netdev); ++ ret = register_netdev(netdev); ++ if (ret) { ++ dev_err(dev, "net device registration failed\n"); ++ goto err_reg_netdev; ++ } ++ ++ xgbe_a0_ptp_register(pdata); ++ ++ xgbe_a0_debugfs_init(pdata); ++ ++ netdev_notice(netdev, "net device enabled\n"); ++ ++ DBGPR("<-- xgbe_probe\n"); ++ ++ return 0; ++ ++err_reg_netdev: ++ xgbe_a0_mdio_unregister(pdata); ++ ++err_bus_id: ++ kfree(pdata->mii_bus_id); ++ ++err_io: ++ free_netdev(netdev); ++ ++err_alloc: ++ dev_notice(dev, "net device not enabled\n"); ++ ++ return ret; ++} ++ ++static int xgbe_remove(struct platform_device *pdev) ++{ ++ struct net_device *netdev = platform_get_drvdata(pdev); ++ struct xgbe_prv_data *pdata = netdev_priv(netdev); ++ ++ DBGPR("-->xgbe_remove\n"); ++ ++ xgbe_a0_debugfs_exit(pdata); ++ ++ xgbe_a0_ptp_unregister(pdata); ++ ++ unregister_netdev(netdev); ++ ++ xgbe_a0_mdio_unregister(pdata); ++ ++ kfree(pdata->mii_bus_id); ++ ++ free_netdev(netdev); ++ ++ DBGPR("<--xgbe_remove\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int xgbe_suspend(struct device *dev) ++{ ++ struct net_device *netdev = dev_get_drvdata(dev); ++ int ret; ++ ++ DBGPR("-->xgbe_suspend\n"); ++ ++ if (!netif_running(netdev)) { ++ DBGPR("<--xgbe_dev_suspend\n"); ++ return -EINVAL; ++ } ++ ++ ret = xgbe_a0_powerdown(netdev, XGMAC_DRIVER_CONTEXT); ++ ++ DBGPR("<--xgbe_suspend\n"); ++ ++ return ret; ++} ++ ++static int xgbe_resume(struct device *dev) ++{ ++ struct net_device *netdev = dev_get_drvdata(dev); ++ int ret; ++ ++ DBGPR("-->xgbe_resume\n"); ++ ++ if (!netif_running(netdev)) { ++ DBGPR("<--xgbe_dev_resume\n"); ++ return -EINVAL; ++ } ++ ++ ret = xgbe_a0_powerup(netdev, XGMAC_DRIVER_CONTEXT); ++ ++ DBGPR("<--xgbe_resume\n"); ++ ++ return ret; ++} ++#endif /* CONFIG_PM */ ++ ++#ifdef CONFIG_ACPI ++static const struct acpi_device_id xgbe_a0_acpi_match[] = { ++ { "AMDI8000", 0 }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(acpi, xgbe_a0_acpi_match); ++#endif ++ ++#ifdef CONFIG_OF ++static const struct of_device_id xgbe_a0_of_match[] = { ++ { .compatible = "amd,xgbe-seattle-v0a", }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, xgbe_a0_of_match); ++#endif ++ ++static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume); ++ ++static struct platform_driver xgbe_a0_driver = { ++ .driver = { ++ .name = "amd-xgbe-a0", ++#ifdef CONFIG_ACPI ++ .acpi_match_table = xgbe_a0_acpi_match, ++#endif ++#ifdef CONFIG_OF ++ .of_match_table = xgbe_a0_of_match, ++#endif ++ .pm = &xgbe_pm_ops, ++ }, ++ .probe = xgbe_probe, ++ .remove = xgbe_remove, ++}; ++ ++module_platform_driver(xgbe_a0_driver); +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c +new file mode 100644 +index 0000000..b84d048 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c +@@ -0,0 +1,312 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static int xgbe_mdio_read(struct mii_bus *mii, int prtad, int mmd_reg) ++{ ++ struct xgbe_prv_data *pdata = mii->priv; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ int mmd_data; ++ ++ DBGPR_MDIO("-->xgbe_mdio_read: prtad=%#x mmd_reg=%#x\n", ++ prtad, mmd_reg); ++ ++ mmd_data = hw_if->read_mmd_regs(pdata, prtad, mmd_reg); ++ ++ DBGPR_MDIO("<--xgbe_mdio_read: mmd_data=%#x\n", mmd_data); ++ ++ return mmd_data; ++} ++ ++static int xgbe_mdio_write(struct mii_bus *mii, int prtad, int mmd_reg, ++ u16 mmd_val) ++{ ++ struct xgbe_prv_data *pdata = mii->priv; ++ struct xgbe_hw_if *hw_if = &pdata->hw_if; ++ int mmd_data = mmd_val; ++ ++ DBGPR_MDIO("-->xgbe_mdio_write: prtad=%#x mmd_reg=%#x mmd_data=%#x\n", ++ prtad, mmd_reg, mmd_data); ++ ++ hw_if->write_mmd_regs(pdata, prtad, mmd_reg, mmd_data); ++ ++ DBGPR_MDIO("<--xgbe_mdio_write\n"); ++ ++ return 0; ++} ++ ++void xgbe_a0_dump_phy_registers(struct xgbe_prv_data *pdata) ++{ ++ struct device *dev = pdata->dev; ++ struct phy_device *phydev = pdata->mii->phy_map[XGBE_PRTAD]; ++ int i; ++ ++ dev_alert(dev, "\n************* PHY Reg dump **********************\n"); ++ ++ dev_alert(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); ++ dev_alert(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); ++ dev_alert(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); ++ dev_alert(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); ++ dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); ++ dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2, ++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); ++ ++ dev_alert(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); ++ dev_alert(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); ++ dev_alert(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n", ++ MDIO_AN_ADVERTISE, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); ++ dev_alert(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n", ++ MDIO_AN_ADVERTISE + 1, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); ++ dev_alert(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n", ++ MDIO_AN_ADVERTISE + 2, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); ++ dev_alert(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n", ++ MDIO_AN_COMP_STAT, ++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); ++ ++ dev_alert(dev, "MMD Device Mask = %#x\n", ++ phydev->c45_ids.devices_in_package); ++ for (i = 0; i < ARRAY_SIZE(phydev->c45_ids.device_ids); i++) ++ dev_alert(dev, " MMD %d: ID = %#08x\n", i, ++ phydev->c45_ids.device_ids[i]); ++ ++ dev_alert(dev, "\n*************************************************\n"); ++} ++ ++int xgbe_a0_mdio_register(struct xgbe_prv_data *pdata) ++{ ++ struct mii_bus *mii; ++ struct phy_device *phydev; ++ int ret = 0; ++ ++ DBGPR("-->xgbe_a0_mdio_register\n"); ++ ++ mii = mdiobus_alloc(); ++ if (!mii) { ++ dev_err(pdata->dev, "mdiobus_alloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ /* Register on the MDIO bus (don't probe any PHYs) */ ++ mii->name = XGBE_PHY_NAME; ++ mii->read = xgbe_mdio_read; ++ mii->write = xgbe_mdio_write; ++ snprintf(mii->id, sizeof(mii->id), "%s", pdata->mii_bus_id); ++ mii->priv = pdata; ++ mii->phy_mask = ~0; ++ mii->parent = pdata->dev; ++ ret = mdiobus_register(mii); ++ if (ret) { ++ dev_err(pdata->dev, "mdiobus_register failed\n"); ++ goto err_mdiobus_alloc; ++ } ++ DBGPR(" mdiobus_register succeeded for %s\n", pdata->mii_bus_id); ++ ++ /* Probe the PCS using Clause 45 */ ++ phydev = get_phy_device(mii, XGBE_PRTAD, true); ++ if (IS_ERR(phydev) || !phydev || ++ !phydev->c45_ids.device_ids[MDIO_MMD_PCS]) { ++ dev_err(pdata->dev, "get_phy_device failed\n"); ++ ret = phydev ? PTR_ERR(phydev) : -ENOLINK; ++ goto err_mdiobus_register; ++ } ++ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, ++ MDIO_ID_ARGS(phydev->c45_ids.device_ids[MDIO_MMD_PCS])); ++ ++ ret = phy_device_register(phydev); ++ if (ret) { ++ dev_err(pdata->dev, "phy_device_register failed\n"); ++ goto err_phy_device; ++ } ++ if (!phydev->dev.driver) { ++ dev_err(pdata->dev, "phy driver probe failed\n"); ++ ret = -EIO; ++ goto err_phy_device; ++ } ++ ++ /* Add a reference to the PHY driver so it can't be unloaded */ ++ pdata->phy_module = phydev->dev.driver->owner; ++ if (!try_module_get(pdata->phy_module)) { ++ dev_err(pdata->dev, "try_module_get failed\n"); ++ ret = -EIO; ++ goto err_phy_device; ++ } ++ ++ pdata->mii = mii; ++ pdata->mdio_mmd = MDIO_MMD_PCS; ++ ++ phydev->autoneg = pdata->default_autoneg; ++ if (phydev->autoneg == AUTONEG_DISABLE) { ++ phydev->speed = pdata->default_speed; ++ phydev->duplex = DUPLEX_FULL; ++ ++ phydev->advertising &= ~ADVERTISED_Autoneg; ++ } ++ ++ pdata->phydev = phydev; ++ ++ DBGPHY_REGS(pdata); ++ ++ DBGPR("<--xgbe_a0_mdio_register\n"); ++ ++ return 0; ++ ++err_phy_device: ++ phy_device_free(phydev); ++ ++err_mdiobus_register: ++ mdiobus_unregister(mii); ++ ++err_mdiobus_alloc: ++ mdiobus_free(mii); ++ ++ return ret; ++} ++ ++void xgbe_a0_mdio_unregister(struct xgbe_prv_data *pdata) ++{ ++ DBGPR("-->xgbe_a0_mdio_unregister\n"); ++ ++ pdata->phydev = NULL; ++ ++ module_put(pdata->phy_module); ++ pdata->phy_module = NULL; ++ ++ mdiobus_unregister(pdata->mii); ++ pdata->mii->priv = NULL; ++ ++ mdiobus_free(pdata->mii); ++ pdata->mii = NULL; ++ ++ DBGPR("<--xgbe_a0_mdio_unregister\n"); ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c +new file mode 100644 +index 0000000..1016aeb +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c +@@ -0,0 +1,278 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "xgbe.h" ++#include "xgbe-common.h" ++ ++static cycle_t xgbe_cc_read(const struct cyclecounter *cc) ++{ ++ struct xgbe_prv_data *pdata = container_of(cc, ++ struct xgbe_prv_data, ++ tstamp_cc); ++ u64 nsec; ++ ++ nsec = pdata->hw_if.get_tstamp_time(pdata); ++ ++ return nsec; ++} ++ ++static int xgbe_adjfreq(struct ptp_clock_info *info, s32 delta) ++{ ++ struct xgbe_prv_data *pdata = container_of(info, ++ struct xgbe_prv_data, ++ ptp_clock_info); ++ unsigned long flags; ++ u64 adjust; ++ u32 addend, diff; ++ unsigned int neg_adjust = 0; ++ ++ if (delta < 0) { ++ neg_adjust = 1; ++ delta = -delta; ++ } ++ ++ adjust = pdata->tstamp_addend; ++ adjust *= delta; ++ diff = div_u64(adjust, 1000000000UL); ++ ++ addend = (neg_adjust) ? pdata->tstamp_addend - diff : ++ pdata->tstamp_addend + diff; ++ ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ ++ pdata->hw_if.update_tstamp_addend(pdata, addend); ++ ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++ ++ return 0; ++} ++ ++static int xgbe_adjtime(struct ptp_clock_info *info, s64 delta) ++{ ++ struct xgbe_prv_data *pdata = container_of(info, ++ struct xgbe_prv_data, ++ ptp_clock_info); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ timecounter_adjtime(&pdata->tstamp_tc, delta); ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++ ++ return 0; ++} ++ ++static int xgbe_gettime(struct ptp_clock_info *info, struct timespec64 *ts) ++{ ++ struct xgbe_prv_data *pdata = container_of(info, ++ struct xgbe_prv_data, ++ ptp_clock_info); ++ unsigned long flags; ++ u64 nsec; ++ ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ ++ nsec = timecounter_read(&pdata->tstamp_tc); ++ ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++ ++ *ts = ns_to_timespec64(nsec); ++ ++ return 0; ++} ++ ++static int xgbe_settime(struct ptp_clock_info *info, const struct timespec64 *ts) ++{ ++ struct xgbe_prv_data *pdata = container_of(info, ++ struct xgbe_prv_data, ++ ptp_clock_info); ++ unsigned long flags; ++ u64 nsec; ++ ++ nsec = timespec64_to_ns(ts); ++ ++ spin_lock_irqsave(&pdata->tstamp_lock, flags); ++ ++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec); ++ ++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags); ++ ++ return 0; ++} ++ ++static int xgbe_enable(struct ptp_clock_info *info, ++ struct ptp_clock_request *request, int on) ++{ ++ return -EOPNOTSUPP; ++} ++ ++void xgbe_a0_ptp_register(struct xgbe_prv_data *pdata) ++{ ++ struct ptp_clock_info *info = &pdata->ptp_clock_info; ++ struct ptp_clock *clock; ++ struct cyclecounter *cc = &pdata->tstamp_cc; ++ u64 dividend; ++ ++ snprintf(info->name, sizeof(info->name), "%s", ++ netdev_name(pdata->netdev)); ++ info->owner = THIS_MODULE; ++ info->max_adj = pdata->ptpclk_rate; ++ info->adjfreq = xgbe_adjfreq; ++ info->adjtime = xgbe_adjtime; ++ info->gettime64 = xgbe_gettime; ++ info->settime64 = xgbe_settime; ++ info->enable = xgbe_enable; ++ ++ clock = ptp_clock_register(info, pdata->dev); ++ if (IS_ERR(clock)) { ++ dev_err(pdata->dev, "ptp_clock_register failed\n"); ++ return; ++ } ++ ++ pdata->ptp_clock = clock; ++ ++ /* Calculate the addend: ++ * addend = 2^32 / (PTP ref clock / 50Mhz) ++ * = (2^32 * 50Mhz) / PTP ref clock ++ */ ++ dividend = 50000000; ++ dividend <<= 32; ++ pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); ++ ++ /* Setup the timecounter */ ++ cc->read = xgbe_cc_read; ++ cc->mask = CLOCKSOURCE_MASK(64); ++ cc->mult = 1; ++ cc->shift = 0; ++ ++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, ++ ktime_to_ns(ktime_get_real())); ++ ++ /* Disable all timestamping to start */ ++ XGMAC_IOWRITE(pdata, MAC_TCR, 0); ++ pdata->tstamp_config.tx_type = HWTSTAMP_TX_OFF; ++ pdata->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; ++} ++ ++void xgbe_a0_ptp_unregister(struct xgbe_prv_data *pdata) ++{ ++ if (pdata->ptp_clock) ++ ptp_clock_unregister(pdata->ptp_clock); ++} +diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe.h b/drivers/net/ethernet/amd/xgbe-a0/xgbe.h +new file mode 100644 +index 0000000..04c00d2 +--- /dev/null ++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe.h +@@ -0,0 +1,868 @@ ++/* ++ * AMD 10Gb Ethernet driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This file incorporates work covered by the following copyright and ++ * permission notice: ++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation ++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys, ++ * Inc. unless otherwise expressly agreed to in writing between Synopsys ++ * and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for Licensed ++ * Product with Synopsys or any supplement thereto. Permission is hereby ++ * granted, free of charge, to any person obtaining a copy of this software ++ * annotated with this license and the Software, to deal in the Software ++ * without restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished ++ * to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++ * THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef __XGBE_H__ ++#define __XGBE_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define XGBE_DRV_NAME "amd-xgbe" ++#define XGBE_DRV_VERSION "0.0.0-a" ++#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" ++ ++/* Descriptor related defines */ ++#define XGBE_TX_DESC_CNT 512 ++#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) ++#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) ++#define XGBE_RX_DESC_CNT 512 ++ ++#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) ++ ++/* Descriptors required for maximum contigous TSO/GSO packet */ ++#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) ++ ++/* Maximum possible descriptors needed for an SKB: ++ * - Maximum number of SKB frags ++ * - Maximum descriptors for contiguous TSO/GSO packet ++ * - Possible context descriptor ++ * - Possible TSO header descriptor ++ */ ++#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) ++ ++#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) ++#define XGBE_RX_BUF_ALIGN 64 ++#define XGBE_SKB_ALLOC_SIZE 256 ++#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ ++ ++#define XGBE_MAX_DMA_CHANNELS 16 ++#define XGBE_MAX_QUEUES 16 ++#define XGBE_DMA_STOP_TIMEOUT 5 ++ ++/* DMA cache settings - Outer sharable, write-back, write-allocate */ ++#define XGBE_DMA_OS_AXDOMAIN 0x2 ++#define XGBE_DMA_OS_ARCACHE 0xb ++#define XGBE_DMA_OS_AWCACHE 0xf ++ ++/* DMA cache settings - System, no caches used */ ++#define XGBE_DMA_SYS_AXDOMAIN 0x3 ++#define XGBE_DMA_SYS_ARCACHE 0x0 ++#define XGBE_DMA_SYS_AWCACHE 0x0 ++ ++#define XGBE_DMA_INTERRUPT_MASK 0x31c7 ++ ++#define XGMAC_MIN_PACKET 60 ++#define XGMAC_STD_PACKET_MTU 1500 ++#define XGMAC_MAX_STD_PACKET 1518 ++#define XGMAC_JUMBO_PACKET_MTU 9000 ++#define XGMAC_MAX_JUMBO_PACKET 9018 ++ ++/* MDIO bus phy name */ ++#define XGBE_PHY_NAME "amd_xgbe_phy_a0" ++#define XGBE_PRTAD 0 ++ ++/* Common property names */ ++#define XGBE_MAC_ADDR_PROPERTY "mac-address" ++#define XGBE_PHY_MODE_PROPERTY "phy-mode" ++#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" ++ ++/* Device-tree clock names */ ++#define XGBE_DMA_CLOCK "dma_clk" ++#define XGBE_PTP_CLOCK "ptp_clk" ++ ++/* ACPI property names */ ++#define XGBE_ACPI_DMA_FREQ "amd,dma-freq" ++#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" ++ ++/* Timestamp support - values based on 50MHz PTP clock ++ * 50MHz => 20 nsec ++ */ ++#define XGBE_TSTAMP_SSINC 20 ++#define XGBE_TSTAMP_SNSINC 0 ++ ++/* Driver PMT macros */ ++#define XGMAC_DRIVER_CONTEXT 1 ++#define XGMAC_IOCTL_CONTEXT 2 ++ ++#define XGBE_FIFO_MAX 81920 ++#define XGBE_FIFO_SIZE_B(x) (x) ++#define XGBE_FIFO_SIZE_KB(x) (x * 1024) ++ ++#define XGBE_TC_MIN_QUANTUM 10 ++ ++/* Helper macro for descriptor handling ++ * Always use XGBE_GET_DESC_DATA to access the descriptor data ++ * since the index is free-running and needs to be and-ed ++ * with the descriptor count value of the ring to index to ++ * the proper descriptor data. ++ */ ++#define XGBE_GET_DESC_DATA(_ring, _idx) \ ++ ((_ring)->rdata + \ ++ ((_idx) & ((_ring)->rdesc_count - 1))) ++ ++/* Default coalescing parameters */ ++#define XGMAC_INIT_DMA_TX_USECS 50 ++#define XGMAC_INIT_DMA_TX_FRAMES 25 ++ ++#define XGMAC_MAX_DMA_RIWT 0xff ++#define XGMAC_INIT_DMA_RX_USECS 30 ++#define XGMAC_INIT_DMA_RX_FRAMES 25 ++ ++/* Flow control queue count */ ++#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 ++ ++/* Maximum MAC address hash table size (256 bits = 8 bytes) */ ++#define XGBE_MAC_HASH_TABLE_SIZE 8 ++ ++/* Receive Side Scaling */ ++#define XGBE_RSS_HASH_KEY_SIZE 40 ++#define XGBE_RSS_MAX_TABLE_SIZE 256 ++#define XGBE_RSS_LOOKUP_TABLE_TYPE 0 ++#define XGBE_RSS_HASH_KEY_TYPE 1 ++ ++struct xgbe_prv_data; ++ ++struct xgbe_packet_data { ++ struct sk_buff *skb; ++ ++ unsigned int attributes; ++ ++ unsigned int errors; ++ ++ unsigned int rdesc_count; ++ unsigned int length; ++ ++ unsigned int header_len; ++ unsigned int tcp_header_len; ++ unsigned int tcp_payload_len; ++ unsigned short mss; ++ ++ unsigned short vlan_ctag; ++ ++ u64 rx_tstamp; ++ ++ u32 rss_hash; ++ enum pkt_hash_types rss_hash_type; ++ ++ unsigned int tx_packets; ++ unsigned int tx_bytes; ++}; ++ ++/* Common Rx and Tx descriptor mapping */ ++struct xgbe_ring_desc { ++ __le32 desc0; ++ __le32 desc1; ++ __le32 desc2; ++ __le32 desc3; ++}; ++ ++/* Page allocation related values */ ++struct xgbe_page_alloc { ++ struct page *pages; ++ unsigned int pages_len; ++ unsigned int pages_offset; ++ ++ dma_addr_t pages_dma; ++}; ++ ++/* Ring entry buffer data */ ++struct xgbe_buffer_data { ++ struct xgbe_page_alloc pa; ++ struct xgbe_page_alloc pa_unmap; ++ ++ dma_addr_t dma; ++ unsigned int dma_len; ++}; ++ ++/* Tx-related ring data */ ++struct xgbe_tx_ring_data { ++ unsigned int packets; /* BQL packet count */ ++ unsigned int bytes; /* BQL byte count */ ++}; ++ ++/* Rx-related ring data */ ++struct xgbe_rx_ring_data { ++ struct xgbe_buffer_data hdr; /* Header locations */ ++ struct xgbe_buffer_data buf; /* Payload locations */ ++ ++ unsigned short hdr_len; /* Length of received header */ ++ unsigned short len; /* Length of received packet */ ++}; ++ ++/* Structure used to hold information related to the descriptor ++ * and the packet associated with the descriptor (always use ++ * use the XGBE_GET_DESC_DATA macro to access this data from the ring) ++ */ ++struct xgbe_ring_data { ++ struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ ++ dma_addr_t rdesc_dma; /* DMA address of descriptor */ ++ ++ struct sk_buff *skb; /* Virtual address of SKB */ ++ dma_addr_t skb_dma; /* DMA address of SKB data */ ++ unsigned int skb_dma_len; /* Length of SKB DMA area */ ++ ++ struct xgbe_tx_ring_data tx; /* Tx-related data */ ++ struct xgbe_rx_ring_data rx; /* Rx-related data */ ++ ++ unsigned int interrupt; /* Interrupt indicator */ ++ ++ unsigned int mapped_as_page; ++ ++ /* Incomplete receive save location. If the budget is exhausted ++ * or the last descriptor (last normal descriptor or a following ++ * context descriptor) has not been DMA'd yet the current state ++ * of the receive processing needs to be saved. ++ */ ++ unsigned int state_saved; ++ struct { ++ unsigned int incomplete; ++ unsigned int context_next; ++ struct sk_buff *skb; ++ unsigned int len; ++ unsigned int error; ++ } state; ++}; ++ ++struct xgbe_ring { ++ /* Ring lock - used just for TX rings at the moment */ ++ spinlock_t lock; ++ ++ /* Per packet related information */ ++ struct xgbe_packet_data packet_data; ++ ++ /* Virtual/DMA addresses and count of allocated descriptor memory */ ++ struct xgbe_ring_desc *rdesc; ++ dma_addr_t rdesc_dma; ++ unsigned int rdesc_count; ++ ++ /* Array of descriptor data corresponding the descriptor memory ++ * (always use the XGBE_GET_DESC_DATA macro to access this data) ++ */ ++ struct xgbe_ring_data *rdata; ++ ++ /* Page allocation for RX buffers */ ++ struct xgbe_page_alloc rx_hdr_pa; ++ struct xgbe_page_alloc rx_buf_pa; ++ ++ /* Ring index values ++ * cur - Tx: index of descriptor to be used for current transfer ++ * Rx: index of descriptor to check for packet availability ++ * dirty - Tx: index of descriptor to check for transfer complete ++ * Rx: index of descriptor to check for buffer reallocation ++ */ ++ unsigned int cur; ++ unsigned int dirty; ++ ++ /* Coalesce frame count used for interrupt bit setting */ ++ unsigned int coalesce_count; ++ ++ union { ++ struct { ++ unsigned int queue_stopped; ++ unsigned int xmit_more; ++ unsigned short cur_mss; ++ unsigned short cur_vlan_ctag; ++ } tx; ++ }; ++} ____cacheline_aligned; ++ ++/* Structure used to describe the descriptor rings associated with ++ * a DMA channel. ++ */ ++struct xgbe_channel { ++ char name[16]; ++ ++ /* Address of private data area for device */ ++ struct xgbe_prv_data *pdata; ++ ++ /* Queue index and base address of queue's DMA registers */ ++ unsigned int queue_index; ++ void __iomem *dma_regs; ++ ++ /* Per channel interrupt irq number */ ++ int dma_irq; ++ char dma_irq_name[IFNAMSIZ + 32]; ++ ++ /* Netdev related settings */ ++ struct napi_struct napi; ++ ++ unsigned int saved_ier; ++ ++ unsigned int tx_timer_active; ++ struct hrtimer tx_timer; ++ ++ struct xgbe_ring *tx_ring; ++ struct xgbe_ring *rx_ring; ++} ____cacheline_aligned; ++ ++enum xgbe_int { ++ XGMAC_INT_DMA_CH_SR_TI, ++ XGMAC_INT_DMA_CH_SR_TPS, ++ XGMAC_INT_DMA_CH_SR_TBU, ++ XGMAC_INT_DMA_CH_SR_RI, ++ XGMAC_INT_DMA_CH_SR_RBU, ++ XGMAC_INT_DMA_CH_SR_RPS, ++ XGMAC_INT_DMA_CH_SR_TI_RI, ++ XGMAC_INT_DMA_CH_SR_FBE, ++ XGMAC_INT_DMA_ALL, ++}; ++ ++enum xgbe_int_state { ++ XGMAC_INT_STATE_SAVE, ++ XGMAC_INT_STATE_RESTORE, ++}; ++ ++enum xgbe_mtl_fifo_size { ++ XGMAC_MTL_FIFO_SIZE_256 = 0x00, ++ XGMAC_MTL_FIFO_SIZE_512 = 0x01, ++ XGMAC_MTL_FIFO_SIZE_1K = 0x03, ++ XGMAC_MTL_FIFO_SIZE_2K = 0x07, ++ XGMAC_MTL_FIFO_SIZE_4K = 0x0f, ++ XGMAC_MTL_FIFO_SIZE_8K = 0x1f, ++ XGMAC_MTL_FIFO_SIZE_16K = 0x3f, ++ XGMAC_MTL_FIFO_SIZE_32K = 0x7f, ++ XGMAC_MTL_FIFO_SIZE_64K = 0xff, ++ XGMAC_MTL_FIFO_SIZE_128K = 0x1ff, ++ XGMAC_MTL_FIFO_SIZE_256K = 0x3ff, ++}; ++ ++struct xgbe_mmc_stats { ++ /* Tx Stats */ ++ u64 txoctetcount_gb; ++ u64 txframecount_gb; ++ u64 txbroadcastframes_g; ++ u64 txmulticastframes_g; ++ u64 tx64octets_gb; ++ u64 tx65to127octets_gb; ++ u64 tx128to255octets_gb; ++ u64 tx256to511octets_gb; ++ u64 tx512to1023octets_gb; ++ u64 tx1024tomaxoctets_gb; ++ u64 txunicastframes_gb; ++ u64 txmulticastframes_gb; ++ u64 txbroadcastframes_gb; ++ u64 txunderflowerror; ++ u64 txoctetcount_g; ++ u64 txframecount_g; ++ u64 txpauseframes; ++ u64 txvlanframes_g; ++ ++ /* Rx Stats */ ++ u64 rxframecount_gb; ++ u64 rxoctetcount_gb; ++ u64 rxoctetcount_g; ++ u64 rxbroadcastframes_g; ++ u64 rxmulticastframes_g; ++ u64 rxcrcerror; ++ u64 rxrunterror; ++ u64 rxjabbererror; ++ u64 rxundersize_g; ++ u64 rxoversize_g; ++ u64 rx64octets_gb; ++ u64 rx65to127octets_gb; ++ u64 rx128to255octets_gb; ++ u64 rx256to511octets_gb; ++ u64 rx512to1023octets_gb; ++ u64 rx1024tomaxoctets_gb; ++ u64 rxunicastframes_g; ++ u64 rxlengtherror; ++ u64 rxoutofrangetype; ++ u64 rxpauseframes; ++ u64 rxfifooverflow; ++ u64 rxvlanframes_gb; ++ u64 rxwatchdogerror; ++}; ++ ++struct xgbe_hw_if { ++ int (*tx_complete)(struct xgbe_ring_desc *); ++ ++ int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int); ++ int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int); ++ int (*add_mac_addresses)(struct xgbe_prv_data *); ++ int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); ++ ++ int (*enable_rx_csum)(struct xgbe_prv_data *); ++ int (*disable_rx_csum)(struct xgbe_prv_data *); ++ ++ int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); ++ int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); ++ int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); ++ int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); ++ int (*update_vlan_hash_table)(struct xgbe_prv_data *); ++ ++ int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); ++ void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); ++ int (*set_gmii_speed)(struct xgbe_prv_data *); ++ int (*set_gmii_2500_speed)(struct xgbe_prv_data *); ++ int (*set_xgmii_speed)(struct xgbe_prv_data *); ++ ++ void (*enable_tx)(struct xgbe_prv_data *); ++ void (*disable_tx)(struct xgbe_prv_data *); ++ void (*enable_rx)(struct xgbe_prv_data *); ++ void (*disable_rx)(struct xgbe_prv_data *); ++ ++ void (*powerup_tx)(struct xgbe_prv_data *); ++ void (*powerdown_tx)(struct xgbe_prv_data *); ++ void (*powerup_rx)(struct xgbe_prv_data *); ++ void (*powerdown_rx)(struct xgbe_prv_data *); ++ ++ int (*init)(struct xgbe_prv_data *); ++ int (*exit)(struct xgbe_prv_data *); ++ ++ int (*enable_int)(struct xgbe_channel *, enum xgbe_int); ++ int (*disable_int)(struct xgbe_channel *, enum xgbe_int); ++ void (*dev_xmit)(struct xgbe_channel *); ++ int (*dev_read)(struct xgbe_channel *); ++ void (*tx_desc_init)(struct xgbe_channel *); ++ void (*rx_desc_init)(struct xgbe_channel *); ++ void (*rx_desc_reset)(struct xgbe_ring_data *); ++ void (*tx_desc_reset)(struct xgbe_ring_data *); ++ int (*is_last_desc)(struct xgbe_ring_desc *); ++ int (*is_context_desc)(struct xgbe_ring_desc *); ++ void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); ++ ++ /* For FLOW ctrl */ ++ int (*config_tx_flow_control)(struct xgbe_prv_data *); ++ int (*config_rx_flow_control)(struct xgbe_prv_data *); ++ ++ /* For RX coalescing */ ++ int (*config_rx_coalesce)(struct xgbe_prv_data *); ++ int (*config_tx_coalesce)(struct xgbe_prv_data *); ++ unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); ++ unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); ++ ++ /* For RX and TX threshold config */ ++ int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); ++ int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); ++ ++ /* For RX and TX Store and Forward Mode config */ ++ int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); ++ int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); ++ ++ /* For TX DMA Operate on Second Frame config */ ++ int (*config_osp_mode)(struct xgbe_prv_data *); ++ ++ /* For RX and TX PBL config */ ++ int (*config_rx_pbl_val)(struct xgbe_prv_data *); ++ int (*get_rx_pbl_val)(struct xgbe_prv_data *); ++ int (*config_tx_pbl_val)(struct xgbe_prv_data *); ++ int (*get_tx_pbl_val)(struct xgbe_prv_data *); ++ int (*config_pblx8)(struct xgbe_prv_data *); ++ ++ /* For MMC statistics */ ++ void (*rx_mmc_int)(struct xgbe_prv_data *); ++ void (*tx_mmc_int)(struct xgbe_prv_data *); ++ void (*read_mmc_stats)(struct xgbe_prv_data *); ++ ++ /* For Timestamp config */ ++ int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); ++ void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); ++ void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, ++ unsigned int nsec); ++ u64 (*get_tstamp_time)(struct xgbe_prv_data *); ++ u64 (*get_tx_tstamp)(struct xgbe_prv_data *); ++ ++ /* For Data Center Bridging config */ ++ void (*config_dcb_tc)(struct xgbe_prv_data *); ++ void (*config_dcb_pfc)(struct xgbe_prv_data *); ++ ++ /* For Receive Side Scaling */ ++ int (*enable_rss)(struct xgbe_prv_data *); ++ int (*disable_rss)(struct xgbe_prv_data *); ++ int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); ++ int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); ++}; ++ ++struct xgbe_desc_if { ++ int (*alloc_ring_resources)(struct xgbe_prv_data *); ++ void (*free_ring_resources)(struct xgbe_prv_data *); ++ int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); ++ int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, ++ struct xgbe_ring_data *); ++ void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); ++ void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); ++ void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); ++}; ++ ++/* This structure contains flags that indicate what hardware features ++ * or configurations are present in the device. ++ */ ++struct xgbe_hw_features { ++ /* HW Version */ ++ unsigned int version; ++ ++ /* HW Feature Register0 */ ++ unsigned int gmii; /* 1000 Mbps support */ ++ unsigned int vlhash; /* VLAN Hash Filter */ ++ unsigned int sma; /* SMA(MDIO) Interface */ ++ unsigned int rwk; /* PMT remote wake-up packet */ ++ unsigned int mgk; /* PMT magic packet */ ++ unsigned int mmc; /* RMON module */ ++ unsigned int aoe; /* ARP Offload */ ++ unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */ ++ unsigned int eee; /* Energy Efficient Ethernet */ ++ unsigned int tx_coe; /* Tx Checksum Offload */ ++ unsigned int rx_coe; /* Rx Checksum Offload */ ++ unsigned int addn_mac; /* Additional MAC Addresses */ ++ unsigned int ts_src; /* Timestamp Source */ ++ unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ ++ ++ /* HW Feature Register1 */ ++ unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ ++ unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ ++ unsigned int adv_ts_hi; /* Advance Timestamping High Word */ ++ unsigned int dcb; /* DCB Feature */ ++ unsigned int sph; /* Split Header Feature */ ++ unsigned int tso; /* TCP Segmentation Offload */ ++ unsigned int dma_debug; /* DMA Debug Registers */ ++ unsigned int rss; /* Receive Side Scaling */ ++ unsigned int tc_cnt; /* Number of Traffic Classes */ ++ unsigned int hash_table_size; /* Hash Table Size */ ++ unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ ++ ++ /* HW Feature Register2 */ ++ unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ ++ unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ ++ unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ ++ unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ ++ unsigned int pps_out_num; /* Number of PPS outputs */ ++ unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ ++}; ++ ++struct xgbe_prv_data { ++ struct net_device *netdev; ++ struct platform_device *pdev; ++ struct acpi_device *adev; ++ struct device *dev; ++ ++ /* ACPI or DT flag */ ++ unsigned int use_acpi; ++ ++ /* XGMAC/XPCS related mmio registers */ ++ void __iomem *xgmac_regs; /* XGMAC CSRs */ ++ void __iomem *xpcs_regs; /* XPCS MMD registers */ ++ ++ /* Overall device lock */ ++ spinlock_t lock; ++ ++ /* XPCS indirect addressing mutex */ ++ struct mutex xpcs_mutex; ++ ++ /* RSS addressing mutex */ ++ struct mutex rss_mutex; ++ ++ int dev_irq; ++ unsigned int per_channel_irq; ++ ++ struct xgbe_hw_if hw_if; ++ struct xgbe_desc_if desc_if; ++ ++ /* AXI DMA settings */ ++ unsigned int coherent; ++ unsigned int axdomain; ++ unsigned int arcache; ++ unsigned int awcache; ++ ++ /* Rings for Tx/Rx on a DMA channel */ ++ struct xgbe_channel *channel; ++ unsigned int channel_count; ++ unsigned int tx_ring_count; ++ unsigned int tx_desc_count; ++ unsigned int rx_ring_count; ++ unsigned int rx_desc_count; ++ ++ unsigned int tx_q_count; ++ unsigned int rx_q_count; ++ ++ /* Tx/Rx common settings */ ++ unsigned int pblx8; ++ ++ /* Tx settings */ ++ unsigned int tx_sf_mode; ++ unsigned int tx_threshold; ++ unsigned int tx_pbl; ++ unsigned int tx_osp_mode; ++ ++ /* Rx settings */ ++ unsigned int rx_sf_mode; ++ unsigned int rx_threshold; ++ unsigned int rx_pbl; ++ ++ /* Tx coalescing settings */ ++ unsigned int tx_usecs; ++ unsigned int tx_frames; ++ ++ /* Rx coalescing settings */ ++ unsigned int rx_riwt; ++ unsigned int rx_frames; ++ ++ /* Current Rx buffer size */ ++ unsigned int rx_buf_size; ++ ++ /* Flow control settings */ ++ unsigned int pause_autoneg; ++ unsigned int tx_pause; ++ unsigned int rx_pause; ++ ++ /* Receive Side Scaling settings */ ++ u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; ++ u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; ++ u32 rss_options; ++ ++ /* MDIO settings */ ++ struct module *phy_module; ++ char *mii_bus_id; ++ struct mii_bus *mii; ++ int mdio_mmd; ++ struct phy_device *phydev; ++ int default_autoneg; ++ int default_speed; ++ ++ /* Current PHY settings */ ++ phy_interface_t phy_mode; ++ int phy_link; ++ int phy_speed; ++ unsigned int phy_tx_pause; ++ unsigned int phy_rx_pause; ++ ++ /* Netdev related settings */ ++ unsigned char mac_addr[ETH_ALEN]; ++ netdev_features_t netdev_features; ++ struct napi_struct napi; ++ struct xgbe_mmc_stats mmc_stats; ++ ++ /* Filtering support */ ++ unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; ++ ++ /* Device clocks */ ++ struct clk *sysclk; ++ unsigned long sysclk_rate; ++ struct clk *ptpclk; ++ unsigned long ptpclk_rate; ++ ++ /* Timestamp support */ ++ spinlock_t tstamp_lock; ++ struct ptp_clock_info ptp_clock_info; ++ struct ptp_clock *ptp_clock; ++ struct hwtstamp_config tstamp_config; ++ struct cyclecounter tstamp_cc; ++ struct timecounter tstamp_tc; ++ unsigned int tstamp_addend; ++ struct work_struct tx_tstamp_work; ++ struct sk_buff *tx_tstamp_skb; ++ u64 tx_tstamp; ++ ++ /* DCB support */ ++ struct ieee_ets *ets; ++ struct ieee_pfc *pfc; ++ unsigned int q2tc_map[XGBE_MAX_QUEUES]; ++ unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; ++ ++ /* Hardware features of the device */ ++ struct xgbe_hw_features hw_feat; ++ ++ /* Device restart work structure */ ++ struct work_struct restart_work; ++ ++ /* Keeps track of power mode */ ++ unsigned int power_down; ++ ++#ifdef CONFIG_DEBUG_FS ++ struct dentry *xgbe_debugfs; ++ ++ unsigned int debugfs_xgmac_reg; ++ ++ unsigned int debugfs_xpcs_mmd; ++ unsigned int debugfs_xpcs_reg; ++#endif ++}; ++ ++/* Function prototypes*/ ++ ++void xgbe_a0_init_function_ptrs_dev(struct xgbe_hw_if *); ++void xgbe_a0_init_function_ptrs_desc(struct xgbe_desc_if *); ++struct net_device_ops *xgbe_a0_get_netdev_ops(void); ++struct ethtool_ops *xgbe_a0_get_ethtool_ops(void); ++#ifdef CONFIG_AMD_XGBE_DCB ++const struct dcbnl_rtnl_ops *xgbe_a0_get_dcbnl_ops(void); ++#endif ++ ++int xgbe_a0_mdio_register(struct xgbe_prv_data *); ++void xgbe_a0_mdio_unregister(struct xgbe_prv_data *); ++void xgbe_a0_dump_phy_registers(struct xgbe_prv_data *); ++void xgbe_a0_ptp_register(struct xgbe_prv_data *); ++void xgbe_a0_ptp_unregister(struct xgbe_prv_data *); ++void xgbe_a0_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int, ++ unsigned int); ++void xgbe_a0_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *, ++ unsigned int); ++void xgbe_a0_print_pkt(struct net_device *, struct sk_buff *, bool); ++void xgbe_a0_get_all_hw_features(struct xgbe_prv_data *); ++int xgbe_a0_powerup(struct net_device *, unsigned int); ++int xgbe_a0_powerdown(struct net_device *, unsigned int); ++void xgbe_a0_init_rx_coalesce(struct xgbe_prv_data *); ++void xgbe_a0_init_tx_coalesce(struct xgbe_prv_data *); ++ ++#ifdef CONFIG_DEBUG_FS ++void xgbe_a0_debugfs_init(struct xgbe_prv_data *); ++void xgbe_a0_debugfs_exit(struct xgbe_prv_data *); ++#else ++static inline void xgbe_a0_debugfs_init(struct xgbe_prv_data *pdata) {} ++static inline void xgbe_a0_debugfs_exit(struct xgbe_prv_data *pdata) {} ++#endif /* CONFIG_DEBUG_FS */ ++ ++/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */ ++#if 0 ++#define XGMAC_ENABLE_TX_DESC_DUMP ++#define XGMAC_ENABLE_RX_DESC_DUMP ++#endif ++ ++/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */ ++#if 0 ++#define XGMAC_ENABLE_TX_PKT_DUMP ++#define XGMAC_ENABLE_RX_PKT_DUMP ++#endif ++ ++/* NOTE: Uncomment for function trace log messages in KERNEL LOG */ ++#if 0 ++#define YDEBUG ++#define YDEBUG_MDIO ++#endif ++ ++/* For debug prints */ ++#ifdef YDEBUG ++#define DBGPR(x...) pr_alert(x) ++#define DBGPHY_REGS(x...) xgbe_a0_dump_phy_registers(x) ++#else ++#define DBGPR(x...) do { } while (0) ++#define DBGPHY_REGS(x...) do { } while (0) ++#endif ++ ++#ifdef YDEBUG_MDIO ++#define DBGPR_MDIO(x...) pr_alert(x) ++#else ++#define DBGPR_MDIO(x...) do { } while (0) ++#endif ++ ++#endif +-- +2.5.3 + diff --git a/core/linux-armv8-rc/0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch b/core/linux-armv8-rc/0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch new file mode 100644 index 000000000..8ac71f5d4 --- /dev/null +++ b/core/linux-armv8-rc/0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch @@ -0,0 +1,1870 @@ +From 3cc72dc1310f5dd00d38f6dcac4e18a1a136622e Mon Sep 17 00:00:00 2001 +From: Tom Lendacky +Date: Tue, 17 Mar 2015 10:58:38 -0500 +Subject: [PATCH 2/4] amd-xgbe-phy-a0: Add support for XGBE PHY on A0 + +Add XGBE phy driver support for A0 hardware. + +Signed-off-by: Tom Lendacky +[Add back AMD_XGBE_PHY removed upstream for B0 driver] +Signed-off-by: Mark Salter +--- + drivers/net/phy/Kconfig | 7 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/amd-xgbe-phy-a0.c | 1814 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 1822 insertions(+) + create mode 100644 drivers/net/phy/amd-xgbe-phy-a0.c + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index cb86d7a..a3138b1 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -24,6 +24,13 @@ config AMD_PHY + ---help--- + Currently supports the am79c874 + ++config AMD_XGBE_PHY ++ tristate "Driver for the AMD 10GbE (amd-xgbe) PHYs" ++ depends on (OF || ACPI) && HAS_IOMEM ++ depends on ARM64 || COMPILE_TEST ++ ---help--- ++ Currently supports the AMD 10GbE PHY ++ + config MARVELL_PHY + tristate "Drivers for Marvell PHYs" + ---help--- +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index fcc25a0..6ebb9ba 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o + obj-$(CONFIG_AMD_PHY) += amd.o ++obj-$(CONFIG_AMD_XGBE_PHY) += amd-xgbe-phy-a0.o + obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o + obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o + obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o +diff --git a/drivers/net/phy/amd-xgbe-phy-a0.c b/drivers/net/phy/amd-xgbe-phy-a0.c +new file mode 100644 +index 0000000..c352d5c +--- /dev/null ++++ b/drivers/net/phy/amd-xgbe-phy-a0.c +@@ -0,0 +1,1814 @@ ++/* ++ * AMD 10Gb Ethernet PHY driver ++ * ++ * This file is available to you under your choice of the following two ++ * licenses: ++ * ++ * License 1: GPLv2 ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * ++ * This file is free software; you may copy, redistribute and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ * ++ * License 2: Modified BSD ++ * ++ * Copyright (c) 2014 Advanced Micro Devices, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Advanced Micro Devices, Inc. nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++MODULE_AUTHOR("Tom Lendacky "); ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_VERSION("0.0.0-a"); ++MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); ++ ++#define XGBE_PHY_ID 0x7996ced0 ++#define XGBE_PHY_MASK 0xfffffff0 ++ ++#define XGBE_PHY_SERDES_RETRY 32 ++#define XGBE_PHY_CHANNEL_PROPERTY "amd,serdes-channel" ++#define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set" ++#define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc" ++#define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" ++#define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" ++#define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp" ++ ++#define XGBE_PHY_SPEEDS 3 ++#define XGBE_PHY_SPEED_1000 0 ++#define XGBE_PHY_SPEED_2500 1 ++#define XGBE_PHY_SPEED_10000 2 ++ ++#define XGBE_AN_INT_CMPLT 0x01 ++#define XGBE_AN_INC_LINK 0x02 ++#define XGBE_AN_PG_RCV 0x04 ++#define XGBE_AN_INT_MASK 0x07 ++ ++#define XNP_MCF_NULL_MESSAGE 0x001 ++#define XNP_ACK_PROCESSED BIT(12) ++#define XNP_MP_FORMATTED BIT(13) ++#define XNP_NP_EXCHANGE BIT(15) ++ ++#define XGBE_PHY_RATECHANGE_COUNT 500 ++ ++#define XGBE_PHY_KR_TRAINING_START 0x01 ++#define XGBE_PHY_KR_TRAINING_ENABLE 0x02 ++ ++#define XGBE_PHY_FEC_ENABLE 0x01 ++#define XGBE_PHY_FEC_FORWARD 0x02 ++#define XGBE_PHY_FEC_MASK 0x03 ++ ++#ifndef MDIO_PMA_10GBR_PMD_CTRL ++#define MDIO_PMA_10GBR_PMD_CTRL 0x0096 ++#endif ++ ++#ifndef MDIO_PMA_10GBR_FEC_ABILITY ++#define MDIO_PMA_10GBR_FEC_ABILITY 0x00aa ++#endif ++ ++#ifndef MDIO_PMA_10GBR_FEC_CTRL ++#define MDIO_PMA_10GBR_FEC_CTRL 0x00ab ++#endif ++ ++#ifndef MDIO_AN_XNP ++#define MDIO_AN_XNP 0x0016 ++#endif ++ ++#ifndef MDIO_AN_LPX ++#define MDIO_AN_LPX 0x0019 ++#endif ++ ++#ifndef MDIO_AN_INTMASK ++#define MDIO_AN_INTMASK 0x8001 ++#endif ++ ++#ifndef MDIO_AN_INT ++#define MDIO_AN_INT 0x8002 ++#endif ++ ++#ifndef MDIO_AN_KR_CTRL ++#define MDIO_AN_KR_CTRL 0x8003 ++#endif ++ ++#ifndef MDIO_CTRL1_SPEED1G ++#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) ++#endif ++ ++#ifndef MDIO_KR_CTRL_PDETECT ++#define MDIO_KR_CTRL_PDETECT 0x01 ++#endif ++ ++#define GET_BITS(_var, _index, _width) \ ++ (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) ++ ++#define SET_BITS(_var, _index, _width, _val) \ ++do { \ ++ (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ ++ (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ ++} while (0) ++ ++#define XCMU_IOREAD(_priv, _reg) \ ++ ioread16((_priv)->cmu_regs + _reg) ++ ++#define XCMU_IOWRITE(_priv, _reg, _val) \ ++ iowrite16((_val), (_priv)->cmu_regs + _reg) ++ ++#define XRXTX_IOREAD(_priv, _reg) \ ++ ioread16((_priv)->rxtx_regs + _reg) ++ ++#define XRXTX_IOREAD_BITS(_priv, _reg, _field) \ ++ GET_BITS(XRXTX_IOREAD((_priv), _reg), \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH) ++ ++#define XRXTX_IOWRITE(_priv, _reg, _val) \ ++ iowrite16((_val), (_priv)->rxtx_regs + _reg) ++ ++#define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \ ++do { \ ++ u16 reg_val = XRXTX_IOREAD((_priv), _reg); \ ++ SET_BITS(reg_val, \ ++ _reg##_##_field##_INDEX, \ ++ _reg##_##_field##_WIDTH, (_val)); \ ++ XRXTX_IOWRITE((_priv), _reg, reg_val); \ ++} while (0) ++ ++/* SerDes CMU register offsets */ ++#define CMU_REG15 0x003c ++#define CMU_REG16 0x0040 ++ ++/* SerDes CMU register entry bit positions and sizes */ ++#define CMU_REG16_TX_RATE_CHANGE_BASE 15 ++#define CMU_REG16_RX_RATE_CHANGE_BASE 14 ++#define CMU_REG16_RATE_CHANGE_DECR 2 ++ ++/* SerDes RxTx register offsets */ ++#define RXTX_REG2 0x0008 ++#define RXTX_REG3 0x000c ++#define RXTX_REG5 0x0014 ++#define RXTX_REG6 0x0018 ++#define RXTX_REG20 0x0050 ++#define RXTX_REG53 0x00d4 ++#define RXTX_REG114 0x01c8 ++#define RXTX_REG115 0x01cc ++#define RXTX_REG142 0x0238 ++ ++/* SerDes RxTx register entry bit positions and sizes */ ++#define RXTX_REG2_RESETB_INDEX 15 ++#define RXTX_REG2_RESETB_WIDTH 1 ++#define RXTX_REG3_TX_DATA_RATE_INDEX 14 ++#define RXTX_REG3_TX_DATA_RATE_WIDTH 2 ++#define RXTX_REG3_TX_WORD_MODE_INDEX 11 ++#define RXTX_REG3_TX_WORD_MODE_WIDTH 3 ++#define RXTX_REG5_TXAMP_CNTL_INDEX 7 ++#define RXTX_REG5_TXAMP_CNTL_WIDTH 4 ++#define RXTX_REG6_RX_DATA_RATE_INDEX 9 ++#define RXTX_REG6_RX_DATA_RATE_WIDTH 2 ++#define RXTX_REG6_RX_WORD_MODE_INDEX 11 ++#define RXTX_REG6_RX_WORD_MODE_WIDTH 3 ++#define RXTX_REG20_BLWC_ENA_INDEX 2 ++#define RXTX_REG20_BLWC_ENA_WIDTH 1 ++#define RXTX_REG53_RX_PLLSELECT_INDEX 15 ++#define RXTX_REG53_RX_PLLSELECT_WIDTH 1 ++#define RXTX_REG53_TX_PLLSELECT_INDEX 14 ++#define RXTX_REG53_TX_PLLSELECT_WIDTH 1 ++#define RXTX_REG53_PI_SPD_SEL_CDR_INDEX 10 ++#define RXTX_REG53_PI_SPD_SEL_CDR_WIDTH 4 ++#define RXTX_REG114_PQ_REG_INDEX 9 ++#define RXTX_REG114_PQ_REG_WIDTH 7 ++#define RXTX_REG115_FORCE_LAT_CAL_START_INDEX 2 ++#define RXTX_REG115_FORCE_LAT_CAL_START_WIDTH 1 ++#define RXTX_REG115_FORCE_SUM_CAL_START_INDEX 1 ++#define RXTX_REG115_FORCE_SUM_CAL_START_WIDTH 1 ++#define RXTX_REG142_SUM_CALIB_DONE_INDEX 15 ++#define RXTX_REG142_SUM_CALIB_DONE_WIDTH 1 ++#define RXTX_REG142_SUM_CALIB_ERR_INDEX 14 ++#define RXTX_REG142_SUM_CALIB_ERR_WIDTH 1 ++#define RXTX_REG142_LAT_CALIB_DONE_INDEX 11 ++#define RXTX_REG142_LAT_CALIB_DONE_WIDTH 1 ++ ++#define RXTX_FULL_RATE 0x0 ++#define RXTX_HALF_RATE 0x1 ++#define RXTX_FIFTH_RATE 0x3 ++#define RXTX_66BIT_WORD 0x7 ++#define RXTX_10BIT_WORD 0x1 ++#define RXTX_10G_BLWC 0x0 ++#define RXTX_1G_BLWC 0x1 ++#define RXTX_10G_TX_AMP 0xa ++#define RXTX_1G_TX_AMP 0xf ++#define RXTX_10G_CDR 0x7 ++#define RXTX_1G_CDR 0x2 ++#define RXTX_10G_PLL 0x1 ++#define RXTX_1G_PLL 0x0 ++#define RXTX_10G_PQ 0x1e ++#define RXTX_1G_PQ 0xa ++ ++DEFINE_SPINLOCK(cmu_lock); ++ ++static const u32 amd_xgbe_phy_serdes_blwc[] = { ++ RXTX_1G_BLWC, ++ RXTX_1G_BLWC, ++ RXTX_10G_BLWC, ++}; ++ ++static const u32 amd_xgbe_phy_serdes_cdr_rate[] = { ++ RXTX_1G_CDR, ++ RXTX_1G_CDR, ++ RXTX_10G_CDR, ++}; ++ ++static const u32 amd_xgbe_phy_serdes_pq_skew[] = { ++ RXTX_1G_PQ, ++ RXTX_1G_PQ, ++ RXTX_10G_PQ, ++}; ++ ++static const u32 amd_xgbe_phy_serdes_tx_amp[] = { ++ RXTX_1G_TX_AMP, ++ RXTX_1G_TX_AMP, ++ RXTX_10G_TX_AMP, ++}; ++ ++enum amd_xgbe_phy_an { ++ AMD_XGBE_AN_READY = 0, ++ AMD_XGBE_AN_PAGE_RECEIVED, ++ AMD_XGBE_AN_INCOMPAT_LINK, ++ AMD_XGBE_AN_COMPLETE, ++ AMD_XGBE_AN_NO_LINK, ++ AMD_XGBE_AN_ERROR, ++}; ++ ++enum amd_xgbe_phy_rx { ++ AMD_XGBE_RX_BPA = 0, ++ AMD_XGBE_RX_XNP, ++ AMD_XGBE_RX_COMPLETE, ++ AMD_XGBE_RX_ERROR, ++}; ++ ++enum amd_xgbe_phy_mode { ++ AMD_XGBE_MODE_KR, ++ AMD_XGBE_MODE_KX, ++}; ++ ++enum amd_xgbe_phy_speedset { ++ AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0, ++ AMD_XGBE_PHY_SPEEDSET_2500_10000, ++}; ++ ++struct amd_xgbe_phy_priv { ++ struct platform_device *pdev; ++ struct acpi_device *adev; ++ struct device *dev; ++ ++ struct phy_device *phydev; ++ ++ /* SerDes related mmio resources */ ++ struct resource *rxtx_res; ++ struct resource *cmu_res; ++ ++ /* SerDes related mmio registers */ ++ void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ ++ void __iomem *cmu_regs; /* SerDes CMU CSRs */ ++ ++ int an_irq; ++ char an_irq_name[IFNAMSIZ + 32]; ++ struct work_struct an_irq_work; ++ unsigned int an_irq_allocated; ++ ++ unsigned int serdes_channel; ++ unsigned int speed_set; ++ ++ /* Maintain link status for re-starting auto-negotiation */ ++ unsigned int link; ++ ++ /* SerDes UEFI configurable settings. ++ * Switching between modes/speeds requires new values for some ++ * SerDes settings. The values can be supplied as device ++ * properties in array format. The first array entry is for ++ * 1GbE, second for 2.5GbE and third for 10GbE ++ */ ++ u32 serdes_blwc[XGBE_PHY_SPEEDS]; ++ u32 serdes_cdr_rate[XGBE_PHY_SPEEDS]; ++ u32 serdes_pq_skew[XGBE_PHY_SPEEDS]; ++ u32 serdes_tx_amp[XGBE_PHY_SPEEDS]; ++ ++ /* Auto-negotiation state machine support */ ++ struct mutex an_mutex; ++ enum amd_xgbe_phy_an an_result; ++ enum amd_xgbe_phy_an an_state; ++ enum amd_xgbe_phy_rx kr_state; ++ enum amd_xgbe_phy_rx kx_state; ++ struct work_struct an_work; ++ struct workqueue_struct *an_workqueue; ++ unsigned int an_supported; ++ unsigned int parallel_detect; ++ unsigned int fec_ability; ++ ++ unsigned int lpm_ctrl; /* CTRL1 for resume */ ++}; ++ ++static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~XGBE_PHY_KR_TRAINING_ENABLE; ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret |= MDIO_CTRL1_LPOWER; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ usleep_range(75, 100); ++ ++ ret &= ~MDIO_CTRL1_LPOWER; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ return 0; ++} ++ ++static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u16 val, mask; ++ ++ /* Assert Rx and Tx ratechange in CMU_reg16 */ ++ val = XCMU_IOREAD(priv, CMU_REG16); ++ ++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) | ++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))); ++ val |= mask; ++ ++ XCMU_IOWRITE(priv, CMU_REG16, val); ++} ++ ++static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u16 val, mask; ++ unsigned int wait; ++ ++ /* Release Rx and Tx ratechange for proper channel in CMU_reg16 */ ++ val = XCMU_IOREAD(priv, CMU_REG16); ++ ++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) | ++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))); ++ val &= ~mask; ++ ++ XCMU_IOWRITE(priv, CMU_REG16, val); ++ ++ /* Wait for Rx and Tx ready in CMU_reg15 */ ++ mask = (1 << priv->serdes_channel) | ++ (1 << (priv->serdes_channel + 8)); ++ wait = XGBE_PHY_RATECHANGE_COUNT; ++ while (wait--) { ++ udelay(50); ++ ++ val = XCMU_IOREAD(priv, CMU_REG15); ++ if ((val & mask) == mask) ++ return; ++ } ++ ++ netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n", ++ val); ++} ++ ++static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Disable KR training */ ++ ret = amd_xgbe_an_disable_kr_training(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set PCS to KR/10G speed */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_PCS_CTRL2_TYPE; ++ ret |= MDIO_PCS_CTRL2_10GBR; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_CTRL1_SPEEDSEL; ++ ret |= MDIO_CTRL1_SPEED10G; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ ret = amd_xgbe_phy_pcs_power_cycle(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set SerDes to 10G speed */ ++ spin_lock(&cmu_lock); ++ ++ amd_xgbe_phy_serdes_start_ratechange(phydev); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FULL_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_66BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, ++ priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FULL_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_66BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, ++ priv->serdes_blwc[XGBE_PHY_SPEED_10000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_10G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_10G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, ++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, ++ priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]); ++ ++ amd_xgbe_phy_serdes_complete_ratechange(phydev); ++ ++ spin_unlock(&cmu_lock); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Disable KR training */ ++ ret = amd_xgbe_an_disable_kr_training(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set PCS to KX/1G speed */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_PCS_CTRL2_TYPE; ++ ret |= MDIO_PCS_CTRL2_10GBX; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_CTRL1_SPEEDSEL; ++ ret |= MDIO_CTRL1_SPEED1G; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ ret = amd_xgbe_phy_pcs_power_cycle(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set SerDes to 2.5G speed */ ++ spin_lock(&cmu_lock); ++ ++ amd_xgbe_phy_serdes_start_ratechange(phydev); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_HALF_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, ++ priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_HALF_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, ++ priv->serdes_blwc[XGBE_PHY_SPEED_2500]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, ++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, ++ priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]); ++ ++ amd_xgbe_phy_serdes_complete_ratechange(phydev); ++ ++ spin_unlock(&cmu_lock); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Disable KR training */ ++ ret = amd_xgbe_an_disable_kr_training(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set PCS to KX/1G speed */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_PCS_CTRL2_TYPE; ++ ret |= MDIO_PCS_CTRL2_10GBX; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_CTRL1_SPEEDSEL; ++ ret |= MDIO_CTRL1_SPEED1G; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ ret = amd_xgbe_phy_pcs_power_cycle(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Set SerDes to 1G speed */ ++ spin_lock(&cmu_lock); ++ ++ amd_xgbe_phy_serdes_start_ratechange(phydev); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FIFTH_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, ++ priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FIFTH_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, ++ priv->serdes_blwc[XGBE_PHY_SPEED_1000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, ++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]); ++ ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, ++ priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]); ++ ++ amd_xgbe_phy_serdes_complete_ratechange(phydev); ++ ++ spin_unlock(&cmu_lock); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_cur_mode(struct phy_device *phydev, ++ enum amd_xgbe_phy_mode *mode) ++{ ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); ++ if (ret < 0) ++ return ret; ++ ++ if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) ++ *mode = AMD_XGBE_MODE_KR; ++ else ++ *mode = AMD_XGBE_MODE_KX; ++ ++ return 0; ++} ++ ++static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev) ++{ ++ enum amd_xgbe_phy_mode mode; ++ ++ if (amd_xgbe_phy_cur_mode(phydev, &mode)) ++ return false; ++ ++ return (mode == AMD_XGBE_MODE_KR); ++} ++ ++static int amd_xgbe_phy_switch_mode(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ /* If we are in KR switch to KX, and vice-versa */ ++ if (amd_xgbe_phy_in_kr_mode(phydev)) { ++ if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000) ++ ret = amd_xgbe_phy_gmii_mode(phydev); ++ else ++ ret = amd_xgbe_phy_gmii_2500_mode(phydev); ++ } else { ++ ret = amd_xgbe_phy_xgmii_mode(phydev); ++ } ++ ++ return ret; ++} ++ ++static int amd_xgbe_phy_set_mode(struct phy_device *phydev, ++ enum amd_xgbe_phy_mode mode) ++{ ++ enum amd_xgbe_phy_mode cur_mode; ++ int ret; ++ ++ ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode); ++ if (ret) ++ return ret; ++ ++ if (mode != cur_mode) ++ ret = amd_xgbe_phy_switch_mode(phydev); ++ ++ return ret; ++} ++ ++static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable, ++ bool restart) ++{ ++ int ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret &= ~MDIO_AN_CTRL1_ENABLE; ++ ++ if (enable) ++ ret |= MDIO_AN_CTRL1_ENABLE; ++ ++ if (restart) ++ ret |= MDIO_AN_CTRL1_RESTART; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_restart_an(struct phy_device *phydev) ++{ ++ return amd_xgbe_phy_set_an(phydev, true, true); ++} ++ ++static int amd_xgbe_phy_disable_an(struct phy_device *phydev) ++{ ++ return amd_xgbe_phy_set_an(phydev, false, false); ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev, ++ enum amd_xgbe_phy_rx *state) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ad_reg, lp_reg, ret; ++ ++ *state = AMD_XGBE_RX_COMPLETE; ++ ++ /* If we're not in KR mode then we're done */ ++ if (!amd_xgbe_phy_in_kr_mode(phydev)) ++ return AMD_XGBE_AN_PAGE_RECEIVED; ++ ++ /* Enable/Disable FEC */ ++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); ++ if (ad_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2); ++ if (lp_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL); ++ if (ret < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ ret &= ~XGBE_PHY_FEC_MASK; ++ if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) ++ ret |= priv->fec_ability; ++ ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret); ++ ++ /* Start KR training */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); ++ if (ret < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ if (ret & XGBE_PHY_KR_TRAINING_ENABLE) { ++ ret |= XGBE_PHY_KR_TRAINING_START; ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ++ ret); ++ } ++ ++ return AMD_XGBE_AN_PAGE_RECEIVED; ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev, ++ enum amd_xgbe_phy_rx *state) ++{ ++ u16 msg; ++ ++ *state = AMD_XGBE_RX_XNP; ++ ++ msg = XNP_MCF_NULL_MESSAGE; ++ msg |= XNP_MP_FORMATTED; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg); ++ ++ return AMD_XGBE_AN_PAGE_RECEIVED; ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev, ++ enum amd_xgbe_phy_rx *state) ++{ ++ unsigned int link_support; ++ int ret, ad_reg, lp_reg; ++ ++ /* Read Base Ability register 2 first */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); ++ if (ret < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ /* Check for a supported mode, otherwise restart in a different one */ ++ link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20; ++ if (!(ret & link_support)) ++ return AMD_XGBE_AN_INCOMPAT_LINK; ++ ++ /* Check Extended Next Page support */ ++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); ++ if (ad_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); ++ if (lp_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ? ++ amd_xgbe_an_tx_xnp(phydev, state) : ++ amd_xgbe_an_tx_training(phydev, state); ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev, ++ enum amd_xgbe_phy_rx *state) ++{ ++ int ad_reg, lp_reg; ++ ++ /* Check Extended Next Page support */ ++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP); ++ if (ad_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX); ++ if (lp_reg < 0) ++ return AMD_XGBE_AN_ERROR; ++ ++ return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ? ++ amd_xgbe_an_tx_xnp(phydev, state) : ++ amd_xgbe_an_tx_training(phydev, state); ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ enum amd_xgbe_phy_rx *state; ++ int ret; ++ ++ state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state ++ : &priv->kx_state; ++ ++ switch (*state) { ++ case AMD_XGBE_RX_BPA: ++ ret = amd_xgbe_an_rx_bpa(phydev, state); ++ break; ++ ++ case AMD_XGBE_RX_XNP: ++ ret = amd_xgbe_an_rx_xnp(phydev, state); ++ break; ++ ++ default: ++ ret = AMD_XGBE_AN_ERROR; ++ } ++ ++ return ret; ++} ++ ++static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ /* Be sure we aren't looping trying to negotiate */ ++ if (amd_xgbe_phy_in_kr_mode(phydev)) { ++ priv->kr_state = AMD_XGBE_RX_ERROR; ++ ++ if (!(phydev->supported & SUPPORTED_1000baseKX_Full) && ++ !(phydev->supported & SUPPORTED_2500baseX_Full)) ++ return AMD_XGBE_AN_NO_LINK; ++ ++ if (priv->kx_state != AMD_XGBE_RX_BPA) ++ return AMD_XGBE_AN_NO_LINK; ++ } else { ++ priv->kx_state = AMD_XGBE_RX_ERROR; ++ ++ if (!(phydev->supported & SUPPORTED_10000baseKR_Full)) ++ return AMD_XGBE_AN_NO_LINK; ++ ++ if (priv->kr_state != AMD_XGBE_RX_BPA) ++ return AMD_XGBE_AN_NO_LINK; ++ } ++ ++ ret = amd_xgbe_phy_disable_an(phydev); ++ if (ret) ++ return AMD_XGBE_AN_ERROR; ++ ++ ret = amd_xgbe_phy_switch_mode(phydev); ++ if (ret) ++ return AMD_XGBE_AN_ERROR; ++ ++ ret = amd_xgbe_phy_restart_an(phydev); ++ if (ret) ++ return AMD_XGBE_AN_ERROR; ++ ++ return AMD_XGBE_AN_INCOMPAT_LINK; ++} ++ ++static irqreturn_t amd_xgbe_an_isr(int irq, void *data) ++{ ++ struct amd_xgbe_phy_priv *priv = (struct amd_xgbe_phy_priv *)data; ++ ++ /* Interrupt reason must be read and cleared outside of IRQ context */ ++ disable_irq_nosync(priv->an_irq); ++ ++ queue_work(priv->an_workqueue, &priv->an_irq_work); ++ ++ return IRQ_HANDLED; ++} ++ ++static void amd_xgbe_an_irq_work(struct work_struct *work) ++{ ++ struct amd_xgbe_phy_priv *priv = container_of(work, ++ struct amd_xgbe_phy_priv, ++ an_irq_work); ++ ++ /* Avoid a race between enabling the IRQ and exiting the work by ++ * waiting for the work to finish and then queueing it ++ */ ++ flush_work(&priv->an_work); ++ queue_work(priv->an_workqueue, &priv->an_work); ++} ++ ++static void amd_xgbe_an_state_machine(struct work_struct *work) ++{ ++ struct amd_xgbe_phy_priv *priv = container_of(work, ++ struct amd_xgbe_phy_priv, ++ an_work); ++ struct phy_device *phydev = priv->phydev; ++ enum amd_xgbe_phy_an cur_state = priv->an_state; ++ int int_reg, int_mask; ++ ++ mutex_lock(&priv->an_mutex); ++ ++ /* Read the interrupt */ ++ int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT); ++ if (!int_reg) ++ goto out; ++ ++next_int: ++ if (int_reg < 0) { ++ priv->an_state = AMD_XGBE_AN_ERROR; ++ int_mask = XGBE_AN_INT_MASK; ++ } else if (int_reg & XGBE_AN_PG_RCV) { ++ priv->an_state = AMD_XGBE_AN_PAGE_RECEIVED; ++ int_mask = XGBE_AN_PG_RCV; ++ } else if (int_reg & XGBE_AN_INC_LINK) { ++ priv->an_state = AMD_XGBE_AN_INCOMPAT_LINK; ++ int_mask = XGBE_AN_INC_LINK; ++ } else if (int_reg & XGBE_AN_INT_CMPLT) { ++ priv->an_state = AMD_XGBE_AN_COMPLETE; ++ int_mask = XGBE_AN_INT_CMPLT; ++ } else { ++ priv->an_state = AMD_XGBE_AN_ERROR; ++ int_mask = 0; ++ } ++ ++ /* Clear the interrupt to be processed */ ++ int_reg &= ~int_mask; ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg); ++ ++ priv->an_result = priv->an_state; ++ ++again: ++ cur_state = priv->an_state; ++ ++ switch (priv->an_state) { ++ case AMD_XGBE_AN_READY: ++ priv->an_supported = 0; ++ break; ++ ++ case AMD_XGBE_AN_PAGE_RECEIVED: ++ priv->an_state = amd_xgbe_an_page_received(phydev); ++ priv->an_supported++; ++ break; ++ ++ case AMD_XGBE_AN_INCOMPAT_LINK: ++ priv->an_supported = 0; ++ priv->parallel_detect = 0; ++ priv->an_state = amd_xgbe_an_incompat_link(phydev); ++ break; ++ ++ case AMD_XGBE_AN_COMPLETE: ++ priv->parallel_detect = priv->an_supported ? 0 : 1; ++ netdev_dbg(phydev->attached_dev, "%s successful\n", ++ priv->an_supported ? "Auto negotiation" ++ : "Parallel detection"); ++ break; ++ ++ case AMD_XGBE_AN_NO_LINK: ++ break; ++ ++ default: ++ priv->an_state = AMD_XGBE_AN_ERROR; ++ } ++ ++ if (priv->an_state == AMD_XGBE_AN_NO_LINK) { ++ /* Disable auto-negotiation for now - it will be ++ * re-enabled once a link is established ++ */ ++ amd_xgbe_phy_disable_an(phydev); ++ ++ int_reg = 0; ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); ++ } else if (priv->an_state == AMD_XGBE_AN_ERROR) { ++ netdev_err(phydev->attached_dev, ++ "error during auto-negotiation, state=%u\n", ++ cur_state); ++ ++ int_reg = 0; ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); ++ } ++ ++ if (priv->an_state >= AMD_XGBE_AN_COMPLETE) { ++ priv->an_result = priv->an_state; ++ priv->an_state = AMD_XGBE_AN_READY; ++ priv->kr_state = AMD_XGBE_RX_BPA; ++ priv->kx_state = AMD_XGBE_RX_BPA; ++ } ++ ++ if (cur_state != priv->an_state) ++ goto again; ++ ++ if (int_reg) ++ goto next_int; ++ ++out: ++ enable_irq(priv->an_irq); ++ ++ mutex_unlock(&priv->an_mutex); ++} ++ ++static int amd_xgbe_an_init(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Set up Advertisement register 3 first */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->supported & SUPPORTED_10000baseR_FEC) ++ ret |= 0xc000; ++ else ++ ret &= ~0xc000; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret); ++ ++ /* Set up Advertisement register 2 next */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->supported & SUPPORTED_10000baseKR_Full) ++ ret |= 0x80; ++ else ++ ret &= ~0x80; ++ ++ if ((phydev->supported & SUPPORTED_1000baseKX_Full) || ++ (phydev->supported & SUPPORTED_2500baseX_Full)) ++ ret |= 0x20; ++ else ++ ret &= ~0x20; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret); ++ ++ /* Set up Advertisement register 1 last */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); ++ if (ret < 0) ++ return ret; ++ ++ if (phydev->supported & SUPPORTED_Pause) ++ ret |= 0x400; ++ else ++ ret &= ~0x400; ++ ++ if (phydev->supported & SUPPORTED_Asym_Pause) ++ ret |= 0x800; ++ else ++ ret &= ~0x800; ++ ++ /* We don't intend to perform XNP */ ++ ret &= ~XNP_NP_EXCHANGE; ++ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_soft_reset(struct phy_device *phydev) ++{ ++ int count, ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ ++ ret |= MDIO_CTRL1_RESET; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ count = 50; ++ do { ++ msleep(20); ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ return ret; ++ } while ((ret & MDIO_CTRL1_RESET) && --count); ++ ++ if (ret & MDIO_CTRL1_RESET) ++ return -ETIMEDOUT; ++ ++ /* Disable auto-negotiation for now */ ++ ret = amd_xgbe_phy_disable_an(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Clear auto-negotiation interrupts */ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_config_init(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ struct net_device *netdev = phydev->attached_dev; ++ int ret; ++ ++ if (!priv->an_irq_allocated) { ++ /* Allocate the auto-negotiation workqueue and interrupt */ ++ snprintf(priv->an_irq_name, sizeof(priv->an_irq_name) - 1, ++ "%s-pcs", netdev_name(netdev)); ++ ++ priv->an_workqueue = ++ create_singlethread_workqueue(priv->an_irq_name); ++ if (!priv->an_workqueue) { ++ netdev_err(netdev, "phy workqueue creation failed\n"); ++ return -ENOMEM; ++ } ++ ++ ret = devm_request_irq(priv->dev, priv->an_irq, ++ amd_xgbe_an_isr, 0, priv->an_irq_name, ++ priv); ++ if (ret) { ++ netdev_err(netdev, "phy irq request failed\n"); ++ destroy_workqueue(priv->an_workqueue); ++ return ret; ++ } ++ ++ priv->an_irq_allocated = 1; ++ } ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY); ++ if (ret < 0) ++ return ret; ++ priv->fec_ability = ret & XGBE_PHY_FEC_MASK; ++ ++ /* Initialize supported features */ ++ phydev->supported = SUPPORTED_Autoneg; ++ phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; ++ phydev->supported |= SUPPORTED_Backplane; ++ phydev->supported |= SUPPORTED_10000baseKR_Full; ++ switch (priv->speed_set) { ++ case AMD_XGBE_PHY_SPEEDSET_1000_10000: ++ phydev->supported |= SUPPORTED_1000baseKX_Full; ++ break; ++ case AMD_XGBE_PHY_SPEEDSET_2500_10000: ++ phydev->supported |= SUPPORTED_2500baseX_Full; ++ break; ++ } ++ ++ if (priv->fec_ability & XGBE_PHY_FEC_ENABLE) ++ phydev->supported |= SUPPORTED_10000baseR_FEC; ++ ++ phydev->advertising = phydev->supported; ++ ++ /* Set initial mode - call the mode setting routines ++ * directly to insure we are properly configured ++ */ ++ if (phydev->supported & SUPPORTED_10000baseKR_Full) ++ ret = amd_xgbe_phy_xgmii_mode(phydev); ++ else if (phydev->supported & SUPPORTED_1000baseKX_Full) ++ ret = amd_xgbe_phy_gmii_mode(phydev); ++ else if (phydev->supported & SUPPORTED_2500baseX_Full) ++ ret = amd_xgbe_phy_gmii_2500_mode(phydev); ++ else ++ ret = -EINVAL; ++ if (ret < 0) ++ return ret; ++ ++ /* Set up advertisement registers based on current settings */ ++ ret = amd_xgbe_an_init(phydev); ++ if (ret) ++ return ret; ++ ++ /* Enable auto-negotiation interrupts */ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_setup_forced(struct phy_device *phydev) ++{ ++ int ret; ++ ++ /* Disable auto-negotiation */ ++ ret = amd_xgbe_phy_disable_an(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Validate/Set specified speed */ ++ switch (phydev->speed) { ++ case SPEED_10000: ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); ++ break; ++ ++ case SPEED_2500: ++ case SPEED_1000: ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ } ++ ++ if (ret < 0) ++ return ret; ++ ++ /* Validate duplex mode */ ++ if (phydev->duplex != DUPLEX_FULL) ++ return -EINVAL; ++ ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ ++ return 0; ++} ++ ++static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u32 mmd_mask = phydev->c45_ids.devices_in_package; ++ int ret; ++ ++ if (phydev->autoneg != AUTONEG_ENABLE) ++ return amd_xgbe_phy_setup_forced(phydev); ++ ++ /* Make sure we have the AN MMD present */ ++ if (!(mmd_mask & MDIO_DEVS_AN)) ++ return -EINVAL; ++ ++ /* Disable auto-negotiation interrupt */ ++ disable_irq(priv->an_irq); ++ ++ /* Start auto-negotiation in a supported mode */ ++ if (phydev->supported & SUPPORTED_10000baseKR_Full) ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); ++ else if ((phydev->supported & SUPPORTED_1000baseKX_Full) || ++ (phydev->supported & SUPPORTED_2500baseX_Full)) ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); ++ else ++ ret = -EINVAL; ++ if (ret < 0) { ++ enable_irq(priv->an_irq); ++ return ret; ++ } ++ ++ /* Disable and stop any in progress auto-negotiation */ ++ ret = amd_xgbe_phy_disable_an(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* Clear any auto-negotitation interrupts */ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); ++ ++ priv->an_result = AMD_XGBE_AN_READY; ++ priv->an_state = AMD_XGBE_AN_READY; ++ priv->kr_state = AMD_XGBE_RX_BPA; ++ priv->kx_state = AMD_XGBE_RX_BPA; ++ ++ /* Re-enable auto-negotiation interrupt */ ++ enable_irq(priv->an_irq); ++ ++ /* Set up advertisement registers based on current settings */ ++ ret = amd_xgbe_an_init(phydev); ++ if (ret) ++ return ret; ++ ++ /* Enable and start auto-negotiation */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL); ++ if (ret < 0) ++ return ret; ++ ++ ret |= MDIO_KR_CTRL_PDETECT; ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret); ++ ++ return amd_xgbe_phy_restart_an(phydev); ++} ++ ++static int amd_xgbe_phy_config_aneg(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ mutex_lock(&priv->an_mutex); ++ ++ ret = __amd_xgbe_phy_config_aneg(phydev); ++ ++ mutex_unlock(&priv->an_mutex); ++ ++ return ret; ++} ++ ++static int amd_xgbe_phy_aneg_done(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ ++ return (priv->an_result == AMD_XGBE_AN_COMPLETE); ++} ++ ++static int amd_xgbe_phy_update_link(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ unsigned int check_again, autoneg; ++ int ret; ++ ++ /* If we're doing auto-negotiation don't report link down */ ++ if (priv->an_state != AMD_XGBE_AN_READY) { ++ phydev->link = 1; ++ return 0; ++ } ++ ++ /* Since the device can be in the wrong mode when a link is ++ * (re-)established (cable connected after the interface is ++ * up, etc.), the link status may report no link. If there ++ * is no link, try switching modes and checking the status ++ * again if auto negotiation is enabled. ++ */ ++ check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0; ++again: ++ /* Link status is latched low, so read once to clear ++ * and then read again to get current state ++ */ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); ++ if (ret < 0) ++ return ret; ++ ++ phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0; ++ ++ if (!phydev->link) { ++ if (check_again) { ++ ret = amd_xgbe_phy_switch_mode(phydev); ++ if (ret < 0) ++ return ret; ++ check_again = 0; ++ goto again; ++ } ++ } ++ ++ autoneg = (phydev->link && !priv->link) ? 1 : 0; ++ priv->link = phydev->link; ++ if (autoneg) { ++ /* Link is (back) up, re-start auto-negotiation */ ++ ret = amd_xgbe_phy_config_aneg(phydev); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_read_status(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u32 mmd_mask = phydev->c45_ids.devices_in_package; ++ int ret, ad_ret, lp_ret; ++ ++ ret = amd_xgbe_phy_update_link(phydev); ++ if (ret) ++ return ret; ++ ++ if ((phydev->autoneg == AUTONEG_ENABLE) && ++ !priv->parallel_detect) { ++ if (!(mmd_mask & MDIO_DEVS_AN)) ++ return -EINVAL; ++ ++ if (!amd_xgbe_phy_aneg_done(phydev)) ++ return 0; ++ ++ /* Compare Advertisement and Link Partner register 1 */ ++ ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); ++ if (ad_ret < 0) ++ return ad_ret; ++ lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); ++ if (lp_ret < 0) ++ return lp_ret; ++ ++ ad_ret &= lp_ret; ++ phydev->pause = (ad_ret & 0x400) ? 1 : 0; ++ phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0; ++ ++ /* Compare Advertisement and Link Partner register 2 */ ++ ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, ++ MDIO_AN_ADVERTISE + 1); ++ if (ad_ret < 0) ++ return ad_ret; ++ lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); ++ if (lp_ret < 0) ++ return lp_ret; ++ ++ ad_ret &= lp_ret; ++ if (ad_ret & 0x80) { ++ phydev->speed = SPEED_10000; ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); ++ if (ret) ++ return ret; ++ } else { ++ switch (priv->speed_set) { ++ case AMD_XGBE_PHY_SPEEDSET_1000_10000: ++ phydev->speed = SPEED_1000; ++ break; ++ ++ case AMD_XGBE_PHY_SPEEDSET_2500_10000: ++ phydev->speed = SPEED_2500; ++ break; ++ } ++ ++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); ++ if (ret) ++ return ret; ++ } ++ ++ phydev->duplex = DUPLEX_FULL; ++ } else { ++ if (amd_xgbe_phy_in_kr_mode(phydev)) { ++ phydev->speed = SPEED_10000; ++ } else { ++ switch (priv->speed_set) { ++ case AMD_XGBE_PHY_SPEEDSET_1000_10000: ++ phydev->speed = SPEED_1000; ++ break; ++ ++ case AMD_XGBE_PHY_SPEEDSET_2500_10000: ++ phydev->speed = SPEED_2500; ++ break; ++ } ++ } ++ phydev->duplex = DUPLEX_FULL; ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ } ++ ++ return 0; ++} ++ ++static int amd_xgbe_phy_suspend(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ int ret; ++ ++ mutex_lock(&phydev->lock); ++ ++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); ++ if (ret < 0) ++ goto unlock; ++ ++ priv->lpm_ctrl = ret; ++ ++ ret |= MDIO_CTRL1_LPOWER; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); ++ ++ ret = 0; ++ ++unlock: ++ mutex_unlock(&phydev->lock); ++ ++ return ret; ++} ++ ++static int amd_xgbe_phy_resume(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ ++ mutex_lock(&phydev->lock); ++ ++ priv->lpm_ctrl &= ~MDIO_CTRL1_LPOWER; ++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl); ++ ++ mutex_unlock(&phydev->lock); ++ ++ return 0; ++} ++ ++static unsigned int amd_xgbe_phy_resource_count(struct platform_device *pdev, ++ unsigned int type) ++{ ++ unsigned int count; ++ int i; ++ ++ for (i = 0, count = 0; i < pdev->num_resources; i++) { ++ struct resource *r = &pdev->resource[i]; ++ ++ if (type == resource_type(r)) ++ count++; ++ } ++ ++ return count; ++} ++ ++static int amd_xgbe_phy_probe(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv; ++ struct platform_device *phy_pdev; ++ struct device *dev, *phy_dev; ++ unsigned int phy_resnum, phy_irqnum; ++ int ret; ++ ++ if (!phydev->bus || !phydev->bus->parent) ++ return -EINVAL; ++ ++ dev = phydev->bus->parent; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->pdev = to_platform_device(dev); ++ priv->adev = ACPI_COMPANION(dev); ++ priv->dev = dev; ++ priv->phydev = phydev; ++ mutex_init(&priv->an_mutex); ++ INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work); ++ INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine); ++ ++ if (!priv->adev || acpi_disabled) { ++ struct device_node *bus_node; ++ struct device_node *phy_node; ++ ++ bus_node = priv->dev->of_node; ++ phy_node = of_parse_phandle(bus_node, "phy-handle", 0); ++ if (!phy_node) { ++ dev_err(dev, "unable to parse phy-handle\n"); ++ ret = -EINVAL; ++ goto err_priv; ++ } ++ ++ phy_pdev = of_find_device_by_node(phy_node); ++ of_node_put(phy_node); ++ ++ if (!phy_pdev) { ++ dev_err(dev, "unable to obtain phy device\n"); ++ ret = -EINVAL; ++ goto err_priv; ++ } ++ ++ phy_resnum = 0; ++ phy_irqnum = 0; ++ } else { ++ /* In ACPI, the XGBE and PHY resources are the grouped ++ * together with the PHY resources at the end ++ */ ++ phy_pdev = priv->pdev; ++ phy_resnum = amd_xgbe_phy_resource_count(phy_pdev, ++ IORESOURCE_MEM) - 2; ++ phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev, ++ IORESOURCE_IRQ) - 1; ++ } ++ phy_dev = &phy_pdev->dev; ++ ++ /* Get the device mmio areas */ ++ priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, ++ phy_resnum++); ++ priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res); ++ if (IS_ERR(priv->rxtx_regs)) { ++ dev_err(dev, "rxtx ioremap failed\n"); ++ ret = PTR_ERR(priv->rxtx_regs); ++ goto err_put; ++ } ++ ++ /* All xgbe phy devices share the CMU registers so retrieve ++ * the resource and do the ioremap directly rather than ++ * the devm_ioremap_resource call ++ */ ++ priv->cmu_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, ++ phy_resnum++); ++ if (!priv->cmu_res) { ++ dev_err(dev, "cmu invalid resource\n"); ++ ret = -EINVAL; ++ goto err_rxtx; ++ } ++ priv->cmu_regs = devm_ioremap_nocache(dev, priv->cmu_res->start, ++ resource_size(priv->cmu_res)); ++ if (!priv->cmu_regs) { ++ dev_err(dev, "cmu ioremap failed\n"); ++ ret = -ENOMEM; ++ goto err_rxtx; ++ } ++ ++ /* Get the auto-negotiation interrupt */ ++ ret = platform_get_irq(phy_pdev, phy_irqnum); ++ if (ret < 0) { ++ dev_err(dev, "platform_get_irq failed\n"); ++ goto err_cmu; ++ } ++ if (priv->adev && !acpi_disabled && !phy_irqnum) { ++ struct irq_data *d = irq_get_irq_data(ret); ++ if (!d) { ++ dev_err(dev, "unable to set AN interrupt\n"); ++ ret = -EINVAL; ++ goto err_cmu; ++ } ++ ++#ifdef CONFIG_ACPI ++ ret = acpi_register_gsi(dev, d->hwirq - 2, ++ ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); ++#else ++ ret = -EINVAL; ++#endif ++ if (ret < 0) { ++ dev_err(dev, "unable to set AN interrupt\n"); ++ goto err_cmu; ++ } ++ } ++ priv->an_irq = ret; ++ ++ /* Get the device serdes channel property */ ++ ret = device_property_read_u32(phy_dev, XGBE_PHY_CHANNEL_PROPERTY, ++ &priv->serdes_channel); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_CHANNEL_PROPERTY); ++ goto err_cmu; ++ } ++ ++ /* Get the device speed set property */ ++ ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY, ++ &priv->speed_set); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_SPEEDSET_PROPERTY); ++ goto err_cmu; ++ } ++ ++ switch (priv->speed_set) { ++ case AMD_XGBE_PHY_SPEEDSET_1000_10000: ++ case AMD_XGBE_PHY_SPEEDSET_2500_10000: ++ break; ++ default: ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_SPEEDSET_PROPERTY); ++ ret = -EINVAL; ++ goto err_cmu; ++ } ++ ++ if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) { ++ ret = device_property_read_u32_array(phy_dev, ++ XGBE_PHY_BLWC_PROPERTY, ++ priv->serdes_blwc, ++ XGBE_PHY_SPEEDS); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_BLWC_PROPERTY); ++ goto err_cmu; ++ } ++ } else { ++ memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc, ++ sizeof(priv->serdes_blwc)); ++ } ++ ++ if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) { ++ ret = device_property_read_u32_array(phy_dev, ++ XGBE_PHY_CDR_RATE_PROPERTY, ++ priv->serdes_cdr_rate, ++ XGBE_PHY_SPEEDS); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_CDR_RATE_PROPERTY); ++ goto err_cmu; ++ } ++ } else { ++ memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate, ++ sizeof(priv->serdes_cdr_rate)); ++ } ++ ++ if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) { ++ ret = device_property_read_u32_array(phy_dev, ++ XGBE_PHY_PQ_SKEW_PROPERTY, ++ priv->serdes_pq_skew, ++ XGBE_PHY_SPEEDS); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_PQ_SKEW_PROPERTY); ++ goto err_cmu; ++ } ++ } else { ++ memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew, ++ sizeof(priv->serdes_pq_skew)); ++ } ++ ++ if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) { ++ ret = device_property_read_u32_array(phy_dev, ++ XGBE_PHY_TX_AMP_PROPERTY, ++ priv->serdes_tx_amp, ++ XGBE_PHY_SPEEDS); ++ if (ret) { ++ dev_err(dev, "invalid %s property\n", ++ XGBE_PHY_TX_AMP_PROPERTY); ++ goto err_cmu; ++ } ++ } else { ++ memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp, ++ sizeof(priv->serdes_tx_amp)); ++ } ++ ++ priv->link = 1; ++ ++ phydev->priv = priv; ++ ++ if (!priv->adev || acpi_disabled) ++ platform_device_put(phy_pdev); ++ ++ return 0; ++ ++err_cmu: ++ devm_iounmap(dev, priv->cmu_regs); ++ ++err_rxtx: ++ devm_iounmap(dev, priv->rxtx_regs); ++ devm_release_mem_region(dev, priv->rxtx_res->start, ++ resource_size(priv->rxtx_res)); ++ ++err_put: ++ if (!priv->adev || acpi_disabled) ++ platform_device_put(phy_pdev); ++ ++err_priv: ++ devm_kfree(dev, priv); ++ ++ return ret; ++} ++ ++static void amd_xgbe_phy_remove(struct phy_device *phydev) ++{ ++ struct amd_xgbe_phy_priv *priv = phydev->priv; ++ struct device *dev = priv->dev; ++ ++ if (priv->an_irq_allocated) { ++ devm_free_irq(dev, priv->an_irq, priv); ++ ++ flush_workqueue(priv->an_workqueue); ++ destroy_workqueue(priv->an_workqueue); ++ } ++ ++ devm_iounmap(dev, priv->cmu_regs); ++ ++ devm_iounmap(dev, priv->rxtx_regs); ++ devm_release_mem_region(dev, priv->rxtx_res->start, ++ resource_size(priv->rxtx_res)); ++ ++ devm_kfree(dev, priv); ++} ++ ++static int amd_xgbe_match_phy_device(struct phy_device *phydev) ++{ ++ return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID; ++} ++ ++static struct phy_driver amd_xgbe_phy_a0_driver[] = { ++ { ++ .phy_id = XGBE_PHY_ID, ++ .phy_id_mask = XGBE_PHY_MASK, ++ .name = "AMD XGBE PHY A0", ++ .features = 0, ++ .probe = amd_xgbe_phy_probe, ++ .remove = amd_xgbe_phy_remove, ++ .soft_reset = amd_xgbe_phy_soft_reset, ++ .config_init = amd_xgbe_phy_config_init, ++ .suspend = amd_xgbe_phy_suspend, ++ .resume = amd_xgbe_phy_resume, ++ .config_aneg = amd_xgbe_phy_config_aneg, ++ .aneg_done = amd_xgbe_phy_aneg_done, ++ .read_status = amd_xgbe_phy_read_status, ++ .match_phy_device = amd_xgbe_match_phy_device, ++ .driver = { ++ .owner = THIS_MODULE, ++ }, ++ }, ++}; ++ ++module_phy_driver(amd_xgbe_phy_a0_driver); ++ ++static struct mdio_device_id __maybe_unused amd_xgbe_phy_a0_ids[] = { ++ { XGBE_PHY_ID, XGBE_PHY_MASK }, ++ { } ++}; ++MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_a0_ids); +-- +2.5.3 + diff --git a/core/linux-armv8-rc/0003-arm64-acpi-drop-expert-patch.patch b/core/linux-armv8-rc/0003-arm64-acpi-drop-expert-patch.patch new file mode 100644 index 000000000..f9cf7cae6 --- /dev/null +++ b/core/linux-armv8-rc/0003-arm64-acpi-drop-expert-patch.patch @@ -0,0 +1,25 @@ +From 4d105425bac75a6341c2536e4617f144e529ddbb Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sun, 3 May 2015 18:35:23 +0100 +Subject: [PATCH 3/4] arm64: acpi drop expert patch + +--- + drivers/acpi/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig +index 114cf48..70ba3ef 100644 +--- a/drivers/acpi/Kconfig ++++ b/drivers/acpi/Kconfig +@@ -5,7 +5,7 @@ + menuconfig ACPI + bool "ACPI (Advanced Configuration and Power Interface) Support" + depends on !IA64_HP_SIM +- depends on IA64 || X86 || (ARM64 && EXPERT) ++ depends on IA64 || X86 || ARM64 + depends on PCI + select PNP + default y +-- +2.5.3 + diff --git a/core/linux-armv8-rc/0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch b/core/linux-armv8-rc/0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch new file mode 100644 index 000000000..c09a127ca --- /dev/null +++ b/core/linux-armv8-rc/0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch @@ -0,0 +1,44 @@ +From 5c695c47800d6066d5650637d719284e837414a1 Mon Sep 17 00:00:00 2001 +From: Mark Langsdorf +Date: Wed, 25 Mar 2015 14:12:51 -0400 +Subject: [PATCH 4/4] usb: make xhci platform driver use 64 bit or 32 bit DMA + +The xhci platform driver needs to work on systems that either only +support 64-bit DMA or only support 32-bit DMA. Attempt to set a +coherent dma mask for 64-bit DMA, and attempt again with 32-bit +DMA if that fails. + +Signed-off-by: Mark Langsdorf +--- + drivers/usb/host/xhci-plat.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 890ad9d..122b1fb 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -93,14 +93,13 @@ static int xhci_plat_probe(struct platform_device *pdev) + if (irq < 0) + return -ENODEV; + +- /* Initialize dma_mask and coherent_dma_mask to 32-bits */ +- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); +- if (ret) +- return ret; +- if (!pdev->dev.dma_mask) +- pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; +- else +- dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ /* Try setting the coherent_dma_mask to 64 bits, then try 32 bits */ ++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); ++ if (ret) { ++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) ++ return ret; ++ } + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) +-- +2.5.3 + diff --git a/core/linux-armv8-rc/PKGBUILD b/core/linux-armv8-rc/PKGBUILD new file mode 100644 index 000000000..3f4c2e33c --- /dev/null +++ b/core/linux-armv8-rc/PKGBUILD @@ -0,0 +1,266 @@ +# ARMv8 multi-platform +# Maintainer: Kevin Mihelich + +buildarch=8 + +_rcver=4.3 +_rcrel=5 + +pkgbase=linux-armv8-rc +_srcname=linux-4.$((${_rcver##*.}-1)) +_kernelname=${pkgbase#linux} +_desc="ARMv8 multi-platform" +pkgver=${_rcver}.rc${_rcrel} +pkgrel=1 +arch=('armv7h') +url="http://www.kernel.org/" +license=('GPL2') +makedepends=('xmlto' 'docbook-xsl' 'kmod' 'inetutils' 'bc' 'git') +options=('!strip') +source=("http://www.kernel.org/pub/linux/kernel/v4.x/${_srcname}.tar.xz" + "https://www.kernel.org/pub/linux/kernel/v4.x/testing/patch-${_rcver}-rc${_rcrel}.xz" + '0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch' + '0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch' + '0003-arm64-acpi-drop-expert-patch.patch' + '0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch' + 'config' + 'linux.preset') +md5sums=('3d5ea06d767e2f35c999eeadafc76523' + 'c1a84a849d2167b30808ce39bda6305b' + '36d2311875f32f694282b10d4237c243' + '49674599c92ee328463f4b6c83b15612' + 'f5e39c9f752c1accd7267dea3f0e7a36' + '31e279e23056ddb39b1c5353de5d477a' + 'a283b4e6ab16e1a9ae03712234575e7b' + 'c1b17ea11a6c9ca95a26881db1376e8e') + +prepare() { + cd "${srcdir}/${_srcname}" + + # add upstream patch + git apply --whitespace=nowarn ../patch-${_rcver}-rc${_rcrel} + + # ALARM patches + git apply ../0001-amd-xgbe-a0-Add-support-for-XGBE-on-A0.patch + git apply ../0002-amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch + git apply ../0003-arm64-acpi-drop-expert-patch.patch + git apply ../0004-usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch + + cat "${srcdir}/config" > ./.config + + # add pkgrel to extraversion + sed -ri "s|^(EXTRAVERSION =)(.*)|\1 \2-${pkgrel}|" Makefile + + # don't run depmod on 'make install'. We'll do this ourselves in packaging + sed -i '2iexit 0' scripts/depmod.sh +} + +build() { + cd "${srcdir}/${_srcname}" + + # get kernel version + make prepare + + # load configuration + # Configure the kernel. Replace the line below with one of your choice. + #make menuconfig # CLI menu for configuration + #make nconfig # new CLI menu for configuration + #make xconfig # X-based configuration + #make oldconfig # using old config from previous kernel version + # ... or manually edit .config + + # Copy back our configuration (use with new kernel version) + #cp ./.config ../${pkgbase}.config + + #################### + # stop here + # this is useful to configure the kernel + #msg "Stopping build" + #return 1 + #################### + + #yes "" | make config + + # build! + unset LDFLAGS + make ${MAKEFLAGS} Image modules dtbs +} + +_package() { + pkgdesc="The Linux Kernel and modules - ${_desc}" + depends=('coreutils' 'linux-firmware' 'kmod' 'mkinitcpio>=0.7') + optdepends=('crda: to set the correct wireless channels of your country') + provides=('kernel26' "linux=${pkgver}") + conflicts=('linux') + backup=("etc/mkinitcpio.d/${pkgbase}.preset") + install=${pkgname}.install + + cd "${srcdir}/${_srcname}" + + KARCH=arm64 + + # get kernel version + _kernver="$(make kernelrelease)" + _basekernel=${_kernver%%-*} + _basekernel=${_basekernel%.*} + + mkdir -p "${pkgdir}"/{lib/modules,lib/firmware} + make INSTALL_MOD_PATH="${pkgdir}" modules_install + make INSTALL_DTBS_PATH="${pkgdir}/boot/dtb-${pkgbase}" dtbs_install + cp arch/$KARCH/boot/Image "${pkgdir}/boot/vmlinuz-${pkgbase}" + + # set correct depmod command for install + sed \ + -e "s/KERNEL_NAME=.*/KERNEL_NAME=${_kernelname}/g" \ + -e "s/KERNEL_VERSION=.*/KERNEL_VERSION=${_kernver}/g" \ + -i "${startdir}/${pkgname}.install" + + # install mkinitcpio preset file for kernel + install -D -m644 "${srcdir}/linux.preset" "${pkgdir}/etc/mkinitcpio.d/${pkgbase}.preset" + sed \ + -e "1s|'linux.*'|'${pkgbase}'|" \ + -e "s|ALL_kver=.*|ALL_kver=\"${_kernver}\"|" \ + -i "${pkgdir}/etc/mkinitcpio.d/${pkgbase}.preset" + + # remove build and source links + rm -f "${pkgdir}"/lib/modules/${_kernver}/{source,build} + # remove the firmware + rm -rf "${pkgdir}/lib/firmware" + # gzip -9 all modules to save 100MB of space + find "${pkgdir}" -name '*.ko' |xargs -P 2 -n 1 gzip -9 + # make room for external modules + ln -s "../extramodules-${_basekernel}-${_kernelname:-ARCH}" "${pkgdir}/lib/modules/${_kernver}/extramodules" + # add real version for building modules and running depmod from post_install/upgrade + mkdir -p "${pkgdir}/lib/modules/extramodules-${_basekernel}-${_kernelname:-ARCH}" + echo "${_kernver}" > "${pkgdir}/lib/modules/extramodules-${_basekernel}-${_kernelname:-ARCH}/version" + + # Now we call depmod... + depmod -b "$pkgdir" -F System.map "$_kernver" + + # move module tree /lib -> /usr/lib + mkdir -p "${pkgdir}/usr" + mv "$pkgdir/lib" "$pkgdir/usr" + + # add vmlinux + install -D -m644 vmlinux "${pkgdir}/usr/lib/modules/${_kernver}/build/vmlinux" +} + +_package-headers() { + pkgdesc="Header files and scripts for building modules for linux kernel - ${_desc}" + provides=("linux-headers=${pkgver}") + conflicts=('linux-headers') + + install -dm755 "${pkgdir}/usr/lib/modules/${_kernver}" + + cd "${srcdir}/${_srcname}" + install -D -m644 Makefile \ + "${pkgdir}/usr/lib/modules/${_kernver}/build/Makefile" + install -D -m644 kernel/Makefile \ + "${pkgdir}/usr/lib/modules/${_kernver}/build/kernel/Makefile" + install -D -m644 .config \ + "${pkgdir}/usr/lib/modules/${_kernver}/build/.config" + + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/include" + + for i in acpi asm-generic config crypto drm generated keys linux math-emu \ + media net pcmcia scsi sound trace uapi video xen; do + cp -a include/${i} "${pkgdir}/usr/lib/modules/${_kernver}/build/include/" + done + + # copy arch includes for external modules + mkdir -p ${pkgdir}/usr/lib/modules/${_kernver}/build/arch/$KARCH + cp -a arch/$KARCH/include ${pkgdir}/usr/lib/modules/${_kernver}/build/arch/$KARCH/ + + # copy files necessary for later builds, like nvidia and vmware + cp Module.symvers "${pkgdir}/usr/lib/modules/${_kernver}/build" + cp -a scripts "${pkgdir}/usr/lib/modules/${_kernver}/build" + + # fix permissions on scripts dir + chmod og-w -R "${pkgdir}/usr/lib/modules/${_kernver}/build/scripts" + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/.tmp_versions" + + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/arch/${KARCH}/kernel" + + cp arch/${KARCH}/Makefile "${pkgdir}/usr/lib/modules/${_kernver}/build/arch/${KARCH}/" + + cp arch/${KARCH}/kernel/asm-offsets.s "${pkgdir}/usr/lib/modules/${_kernver}/build/arch/${KARCH}/kernel/" + + # add docbook makefile + install -D -m644 Documentation/DocBook/Makefile \ + "${pkgdir}/usr/lib/modules/${_kernver}/build/Documentation/DocBook/Makefile" + + # add dm headers + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/md" + cp drivers/md/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/md" + + # add inotify.h + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/include/linux" + cp include/linux/inotify.h "${pkgdir}/usr/lib/modules/${_kernver}/build/include/linux/" + + # add wireless headers + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/net/mac80211/" + cp net/mac80211/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/net/mac80211/" + + # add dvb headers for external modules + # in reference to: + # http://bugs.archlinux.org/task/9912 + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-core" + cp drivers/media/dvb-core/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-core/" + # and... + # http://bugs.archlinux.org/task/11194 + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/include/config/dvb/" + cp include/config/dvb/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/include/config/dvb/" + + # add dvb headers for http://mcentral.de/hg/~mrec/em28xx-new + # in reference to: + # http://bugs.archlinux.org/task/13146 + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-frontends/" + cp drivers/media/dvb-frontends/lgdt330x.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-frontends/" + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/i2c/" + cp drivers/media/i2c/msp3400-driver.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/i2c/" + + # add dvb headers + # in reference to: + # http://bugs.archlinux.org/task/20402 + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/usb/dvb-usb" + cp drivers/media/usb/dvb-usb/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/usb/dvb-usb/" + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-frontends" + cp drivers/media/dvb-frontends/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/dvb-frontends/" + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/tuners" + cp drivers/media/tuners/*.h "${pkgdir}/usr/lib/modules/${_kernver}/build/drivers/media/tuners/" + + # add xfs and shmem for aufs building + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/fs/xfs" + mkdir -p "${pkgdir}/usr/lib/modules/${_kernver}/build/mm" + + # copy in Kconfig files + for i in $(find . -name "Kconfig*"); do + mkdir -p "${pkgdir}"/usr/lib/modules/${_kernver}/build/`echo ${i} | sed 's|/Kconfig.*||'` + cp ${i} "${pkgdir}/usr/lib/modules/${_kernver}/build/${i}" + done + + chown -R root.root "${pkgdir}/usr/lib/modules/${_kernver}/build" + find "${pkgdir}/usr/lib/modules/${_kernver}/build" -type d -exec chmod 755 {} \; + + # strip scripts directory + find "${pkgdir}/usr/lib/modules/${_kernver}/build/scripts" -type f -perm -u+w 2>/dev/null | while read binary ; do + case "$(file -bi "${binary}")" in + *application/x-sharedlib*) # Libraries (.so) + /usr/bin/strip ${STRIP_SHARED} "${binary}";; + *application/x-archive*) # Libraries (.a) + /usr/bin/strip ${STRIP_STATIC} "${binary}";; + *application/x-executable*) # Binaries + /usr/bin/strip ${STRIP_BINARIES} "${binary}";; + esac + done + + # remove unneeded architectures + rm -rf "${pkgdir}"/usr/lib/modules/${_kernver}/build/arch/{alpha,arc,arm,arm26,avr32,blackfin,c6x,cris,frv,h8300,hexagon,ia64,m32r,m68k,m68knommu,metag,mips,microblaze,mn10300,openrisc,parisc,powerpc,ppc,s390,score,sh,sh64,sparc,sparc64,tile,unicore32,um,v850,x86,xtensa} +} + +pkgname=("${pkgbase}" "${pkgbase}-headers") +for _p in ${pkgname[@]}; do + eval "package_${_p}() { + _package${_p#${pkgbase}} + }" +done diff --git a/core/linux-armv8-rc/config b/core/linux-armv8-rc/config new file mode 100644 index 000000000..fb05f7fd7 --- /dev/null +++ b/core/linux-armv8-rc/config @@ -0,0 +1,6038 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 4.3.0-rc4-1 Kernel Configuration +# +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_HAVE_GENERIC_RCU_GUP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_SMP=y +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-ARCH" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_FHANDLE=y +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TASKS_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_BUILD_BIN2C=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +# CONFIG_CGROUP_HUGETLB is not set +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_CGROUP_WRITEBACK=y +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +# CONFIG_EXPERT is not set +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_BPF_SYSCALL=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_PCI_QUIRKS=y +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_CLONE_BACKWARDS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=m +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# Platform selection +# +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_EXYNOS7 is not set +# CONFIG_ARCH_FSL_LS2085A is not set +CONFIG_ARCH_HISI=y +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_ROCKCHIP is not set +CONFIG_ARCH_SEATTLE=y +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_XGENE=y +# CONFIG_ARCH_ZYNQMP is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_ATS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y + +# +# PCI host controller drivers +# +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCI_XGENE_MSI=y +# CONFIG_PCIE_IPROC is not set +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIE_ECRC=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +# CONFIG_ARM64_4K_PAGES is not set +CONFIG_ARM64_64K_PAGES=y +CONFIG_ARM64_VA_BITS_42=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=42 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_TRANSPARENT_HUGEPAGE is not set +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_AREAS=7 +CONFIG_ZSWAP=y +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +CONFIG_ZSMALLOC=y +# CONFIG_PGTABLE_MAPPING is not set +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FRAME_VECTOR=y +CONFIG_SECCOMP=y +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_LSE_ATOMICS is not set + +# +# Boot options +# +CONFIG_CMDLINE="console=ttyAMA0" +# CONFIG_CMDLINE_FORCE is not set +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# CPU Power Management +# + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=m +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# CPU frequency scaling drivers +# +# CONFIG_CPUFREQ_DT is not set +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_NET=y +CONFIG_NET_INGRESS=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETLABEL=y +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_QUEUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=m +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=m +CONFIG_NF_TABLES_NETDEV=m +CONFIG_NFT_EXTHDR=m +CONFIG_NFT_META=m +CONFIG_NFT_CT=m +CONFIG_NFT_RBTREE=m +CONFIG_NFT_HASH=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +CONFIG_NF_TABLES_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NF_TABLES_ARP=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_IPV4=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NF_NAT_MASQUERADE_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_NF_TABLES_IPV6=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_NAT_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m +CONFIG_NF_NAT_MASQUERADE_IPV6=m +CONFIG_NFT_MASQ_IPV6=m +CONFIG_NFT_REDIR_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_HAVE_NET_DSA=y +CONFIG_NET_DSA=m +CONFIG_NET_DSA_HWMON=y +CONFIG_NET_DSA_TAG_BRCM=y +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +# CONFIG_MPLS_IPTUNNEL is not set +# CONFIG_HSR is not set +CONFIG_NET_SWITCHDEV=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_DEV=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_LEDS=y +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_XILINXCAN is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m + +# +# CAN USB interfaces +# +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +CONFIG_DONGLE=y +CONFIG_ESI_DONGLE=m +CONFIG_ACTISYS_DONGLE=m +CONFIG_TEKRAM_DONGLE=m +CONFIG_TOIM3232_DONGLE=m +CONFIG_LITELINK_DONGLE=m +CONFIG_MA600_DONGLE=m +CONFIG_GIRBIL_DONGLE=m +CONFIG_MCP2120_DONGLE=m +CONFIG_OLD_BELKIN_DONGLE=m +CONFIG_ACT200L_DONGLE=m +CONFIG_KINGSUN_DONGLE=m +CONFIG_KSDAZZLE_DONGLE=m +CONFIG_KS959_DONGLE=m + +# +# FIR device drivers +# +CONFIG_USB_IRDA=m +CONFIG_SIGMATEL_FIR=m +CONFIG_VLSI_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_6LOWPAN=m +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_DEBUGFS is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_DEBUGFS=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +# CONFIG_MAC80211_RC_MINSTREL_VHT is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_UART is not set +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +CONFIG_NFC_PN533=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +# CONFIG_NFC_ST_NCI is not set +# CONFIG_NFC_NXP_NCI is not set +# CONFIG_NFC_S3FWRN5_I2C is not set +CONFIG_LWTUNNEL=y +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +# CONFIG_TEGRA_AHB is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +CONFIG_DEBUG_DEVRES=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_FENCE_TRACE is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 + +# +# Bus devices +# +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI_PMU=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PMU=y +CONFIG_ARM_CCI500_PMU=y +CONFIG_ARM_CCN=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=m +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_SPI_NOR is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +# CONFIG_PARPORT is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_ZRAM=m +# CONFIG_ZRAM_LZ4_COMPRESS is not set +CONFIG_BLK_CPQ_CISS_DA=m +CONFIG_CISS_SCSI_TAPE=y +# CONFIG_BLK_DEV_DAC960 is not set +CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NVME=m +CONFIG_BLK_DEV_SKD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_SX8=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +# CONFIG_ICS932S401 is not set +CONFIG_ENCLOSURE_SERVICES=m +# CONFIG_HP_ILO is not set +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +# CONFIG_SENSORS_BH1780 is not set +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_SRAM is not set +CONFIG_VEXPRESS_SYSCFG=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +CONFIG_SENSORS_LIS3_I2C=m + +# +# Altera FPGA firmware download module +# +CONFIG_ALTERA_STAPL=m + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# +# CONFIG_GENWQE is not set +CONFIG_ECHO=m +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_KERNEL_API is not set +# CONFIG_CXL_EEH is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_SCSI_HPSA=m +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +# CONFIG_SCSI_ADVANSYS is not set +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFSHCD_PLATFORM is not set +CONFIG_SCSI_HPTIOP=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_CEVA is not set +CONFIG_AHCI_XGENE=y +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +# CONFIG_PATA_RADISYS is not set +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_PATA_ACPI is not set +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +# CONFIG_MD_CLUSTER is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_MQ_DEFAULT is not set +CONFIG_DM_DEBUG=y +CONFIG_DM_BUFIO=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_MQ=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_CACHE_CLEANER=m +# CONFIG_DM_ERA is not set +CONFIG_DM_MIRROR=y +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=y +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_DELAY=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_NOSY=m +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +# CONFIG_ARCNET is not set +# CONFIG_ATM_DRIVERS is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y +CONFIG_NET_DSA_MV88E6131=m +CONFIG_NET_DSA_MV88E6123_61_65=m +CONFIG_NET_DSA_MV88E6171=m +CONFIG_NET_DSA_MV88E6352=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_ETHERNET=y +CONFIG_MDIO=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_ALTERA_TSE=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_AMD_XGBE=m +# CONFIG_AMD_XGBE_DCB is not set +CONFIG_NET_XGENE=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_ARC_EMAC_CORE=m +CONFIG_ARC_EMAC=m +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_CADENCE=y +CONFIG_MACB=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +# CONFIG_BNX2X_VXLAN is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +CONFIG_DNET=m +# CONFIG_NET_VENDOR_DEC is not set +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBE=m +CONFIG_IXGBE_VXLAN=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBEVF=m +CONFIG_I40E=m +CONFIG_I40E_VXLAN=y +# CONFIG_I40E_DCB is not set +# CONFIG_I40E_FCOE is not set +CONFIG_I40EVF=m +CONFIG_FM10K=m +# CONFIG_FM10K_VXLAN is not set +# CONFIG_NET_VENDOR_I825XX is not set +# CONFIG_IP1000 is not set +CONFIG_JME=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_EN_VXLAN=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +# CONFIG_MLX5_CORE is not set +# CONFIG_MLXSW_CORE is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_8390=y +CONFIG_NE2K_PCI=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_PACKET_ENGINE=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +# CONFIG_SFC is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_SMC91X=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +# CONFIG_SMSC911X_ARCH_HOOKS is not set +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +# CONFIG_NET_VENDOR_SUN is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_NET_SB1000=y +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AQUANTIA_PHY is not set +CONFIG_AT803X_PHY=m +CONFIG_AMD_PHY=m +CONFIG_AMD_XGBE_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +# CONFIG_TERANETICS_PHY is not set +CONFIG_SMSC_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_STE10XP=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_MICROCHIP_PHY is not set +CONFIG_FIXED_PHY=y +CONFIG_MDIO_BITBANG=m +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +CONFIG_AT76C50X_USB=m +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +# CONFIG_ADM8211 is not set +CONFIG_MAC80211_HWSIM=m +CONFIG_MWL8K=m +CONFIG_ATH_COMMON=m +CONFIG_ATH_CARDS=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_DEBUGFS=y +# CONFIG_ATH9K_STATION_STATISTICS is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH9K_RFKILL=y +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +# CONFIG_CARL9170_HWRNG is not set +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_ATH6KL_DEBUG=y +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +# CONFIG_WIL6210_TRACING is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_DEBUG is not set +CONFIG_ATH10K_DEBUGFS=y +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +CONFIG_B43_DEBUG=y +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +CONFIG_B43LEGACY_DEBUG=y +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y +# CONFIG_IWLWIFI_BCAST_FILTERING is not set +# CONFIG_IWLWIFI_UAPSD is not set + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE is not set +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +CONFIG_IWLEGACY_DEBUG=y +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +# CONFIG_TMD_HERMES is not set +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_P54_LEDS=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_DEBUGFS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WL_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +# CONFIG_WL_TI is not set +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_RSI_91X=m +CONFIG_RSI_DEBUGFS=y +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_ATUSB=m +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_POLLDEV=m +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +# CONFIG_JOYSTICK_AS5011 is not set +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_FUJITSU=m +# CONFIG_TOUCHSCREEN_GOODIX is not set +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +# CONFIG_TOUCHSCREEN_MAX11801 is not set +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MTOUCH=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_PIXCIR=m +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_ST1232=m +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MPU3050=m +CONFIG_INPUT_GP2A=m +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m +# CONFIG_INPUT_PCF8574 is not set +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_SOC_BUTTON_ARRAY=m +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_AMBAKMI=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_APBPS2 is not set +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_ROCKETPORT=m +CONFIG_CYCLADES=m +# CONFIG_CYZ_INTR is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +CONFIG_SYNCLINKMP=m +CONFIG_SYNCLINK_GT=m +CONFIG_NOZOMI=m +# CONFIG_ISI is not set +CONFIG_N_HDLC=m +CONFIG_N_GSM=m +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_INGENIC is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_HVC_DRIVER=y +CONFIG_VIRTIO_CONSOLE=m +CONFIG_IPMI_HANDLER=y +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +# CONFIG_IPMI_SI_PROBE_DEFAULTS is not set +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_TPM=m +CONFIG_HW_RANDOM_XGENE=m +CONFIG_R3964=m +# CONFIG_APPLICOM is not set + +# +# PCMCIA character devices +# +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_HPET is not set +CONFIG_TCG_TPM=m +# CONFIG_TCG_TIS_I2C_ATMEL is not set +# CONFIG_TCG_TIS_I2C_INFINEON is not set +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +CONFIG_TCG_ATMEL=m +# CONFIG_TCG_INFINEON is not set +# CONFIG_TCG_TIS_ST33ZP24 is not set +CONFIG_DEVPORT=y +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_REG is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +CONFIG_I2C_SCMI=y + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=m +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_VERSATILE=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_XGENE_SLIMPRO=m +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=m +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=m +CONFIG_DP83640_PHY=m +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_DWAPB is not set +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_GRGPIO is not set +CONFIG_GPIO_PL061=y +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_VX855 is not set +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_XGENE_SB=m + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set + +# +# MFD GPIO expanders +# + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_MATROX is not set +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_BQ27000=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_HISI=y +# CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_XGENE=y +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_IT87=m +# CONFIG_SENSORS_JC42 is not set +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +# CONFIG_SENSORS_HTU21 is not set +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_MAX16064=m +# CONFIG_SENSORS_MAX20751 is not set +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +# CONFIG_SENSORS_SMM665 is not set +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS1015=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_VEXPRESS=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m + +# +# ACPI drivers +# +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_HISI_THERMAL=y +# CONFIG_IMX_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_GPIO_WATCHDOG=m +# CONFIG_XILINX_WATCHDOG is not set +CONFIG_ARM_SP805_WATCHDOG=m +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +CONFIG_MFD_VIPERBOARD=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RTSX_PCI=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RTSX_USB=m +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +CONFIG_MFD_VX855=m +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_VEXPRESS_SYSREG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=m + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=m +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_PCI_SKELETON is not set +CONFIG_VIDEO_TUNER=m +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DVB=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +CONFIG_DVB_CORE=m +CONFIG_DVB_NET=y +CONFIG_TTPCI_EEPROM=m +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y + +# +# Media drivers +# +CONFIG_RC_CORE=m +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_LIRC=m +CONFIG_IR_LIRC_CODEC=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +# CONFIG_IR_ENE is not set +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +# CONFIG_IR_ITE_CIR is not set +# CONFIG_IR_FINTEK is not set +# CONFIG_IR_NUVOTON is not set +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m + +# +# Analog TV USB devices +# +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160_AC97=y +CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +# CONFIG_VIDEO_AU0828_RC is not set +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_FRIIO=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_SMS_USB_DRV=m +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_SOLO6X10=m +# CONFIG_VIDEO_TW68 is not set + +# +# Media capture/analog TV support +# +CONFIG_VIDEO_IVTV=m +# CONFIG_VIDEO_IVTV_ALSA is not set +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m +# CONFIG_VIDEO_DT3155 is not set + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +# CONFIG_VIDEO_CX25821 is not set +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7164=m + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_PT1=m +# CONFIG_DVB_PT3 is not set +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_SMIPCIE=m +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_SH_VEU is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_RADIO_SI4713=m +# CONFIG_USB_SI4713 is not set +# CONFIG_PLATFORM_SI4713 is not set +# CONFIG_I2C_SI4713 is not set +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_USB_KEENE=m +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_MA901=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RADIO_WL1273=m + +# +# Texas Instruments WL128x FM driver (ST based) +# +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_VIDEO_IR_I2C=m + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_VP27SMPX=m + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_CX25840=m + +# +# Video encoders +# +CONFIG_VIDEO_SAA7127=m + +# +# Camera sensor devices +# +CONFIG_VIDEO_MT9V011=m + +# +# Flash devices +# + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_M52790=m + +# +# Sensors used on soc_camera driver +# +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_SI2168=m +# CONFIG_DVB_AS102_FE is not set + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_SP2=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=m +CONFIG_DRM_KMS_HELPER=m +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_TTM=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_RADEON_UMS is not set +CONFIG_DRM_AMDGPU=m +# CONFIG_DRM_AMDGPU_CIK is not set +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_DRM_NOUVEAU=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_MGA is not set +CONFIG_DRM_VIA=m +# CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_VGEM=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_QXL=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set + +# +# Frame buffer Devices +# +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CMDLINE=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +CONFIG_FB_ARMCLCD=y +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SM501 is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +CONFIG_FB_VIRTUAL=m +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +# CONFIG_FB_SM712 is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_PLATFORM=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_RAWMIDI_SEQ=m +CONFIG_SND_OPL3_LIB_SEQ=m +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +CONFIG_SND_EMU10K1_SEQ=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +# CONFIG_SND_AW2 is not set +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_PREALLOC_SIZE=4096 +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +# CONFIG_SND_BCD2000 is not set +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CP2112=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# I2C HID support +# +CONFIG_I2C_HID=m +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_FSM is not set +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_MON=y +CONFIG_USB_WUSB=m +CONFIG_USB_WUSB_CBAF=m +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_HCD_PLATFORM=m +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_ISP1362_HCD=m +CONFIG_USB_FUSBH200_HCD=m +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +CONFIG_USB_HWA_HCD=m +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +# CONFIG_USBIP_DEBUG is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_DWC3_HOST=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC2=m +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +# CONFIG_USB_SERIAL_F81232 is not set +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +# CONFIG_USB_RIO500 is not set +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_LINK_LAYER_TEST is not set +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ATM=m +# CONFIG_USB_SPEEDTOUCH is not set +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +CONFIG_USB_LED_TRIG=y +CONFIG_UWB=m +CONFIG_UWB_HWA=m +CONFIG_UWB_WHCI=m +CONFIG_UWB_I1480U=m +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_ARMMMCI=m +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_PLTFM=m +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_PLTFM=m +# CONFIG_MMC_DW_EXYNOS is not set +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m + +# +# LED drivers +# +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_LP3944=m +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_INTEL_SS4200=m +CONFIG_LEDS_LT3593=m +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_KTD2692 is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +# CONFIG_LEDS_SYSCON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=m +CONFIG_EDAC_XGENE=m +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_SYSTOHC is not set +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS3232=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12057 is not set +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_S35390A is not set +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3029C2=m + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DS1685_PROC_REGS is not set +CONFIG_RTC_DS1685_SYSFS_REGS=y +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_BQ4802=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_V3020=m +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +CONFIG_RTC_DRV_PL031=y +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_XGENE=m + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +CONFIG_DMA_OF=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_IDMA64 is not set +CONFIG_PL330_DMA=m +CONFIG_XGENE_DMA=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_HSU_DMA_PCI is not set + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set +CONFIG_DMA_ENGINE_RAID=y +CONFIG_AUXDISPLAY=y +CONFIG_UIO=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_DMEM_GENIRQ is not set +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_MF624 is not set +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_VIRQFD=m +CONFIG_VFIO=m +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PLATFORM=m +CONFIG_VFIO_AMBA=m +# CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=m + +# +# Virtio drivers +# +CONFIG_VIRTIO_PCI=m +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTL8192U is not set +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_R8712U=m +# CONFIG_R8188EU is not set +CONFIG_R8723AU=m +# CONFIG_8723AU_AP_MODE is not set +# CONFIG_8723AU_BT_COEXIST is not set +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# + +# +# Analog to digital converters +# +# CONFIG_AD7606 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# + +# +# Digital gyroscope sensors +# + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843_I2C is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# + +# +# Triggers - standalone +# +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_FB_SM750 is not set +# CONFIG_FB_XGI is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +CONFIG_STAGING_MEDIA=y +# CONFIG_I2C_BCM2048 is not set +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set +CONFIG_LIRC_STAGING=y +CONFIG_LIRC_BT829=m +CONFIG_LIRC_IMON=m +CONFIG_LIRC_SASEM=m +CONFIG_LIRC_SERIAL=m +CONFIG_LIRC_SERIAL_TRANSMITTER=y +CONFIG_LIRC_SIR=m +CONFIG_LIRC_ZILOG=m + +# +# Android +# +# CONFIG_STAGING_BOARD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_DGNC is not set +# CONFIG_DGAP is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_FSL_MC_BUS is not set +# CONFIG_MOST is not set +CONFIG_CHROME_PLATFORMS=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_VERSATILE=y +CONFIG_CLK_SP810=y +CONFIG_CLK_VEXPRESS_OSC=y +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +CONFIG_COMMON_CLK_XGENE=y +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_HI6220 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_TIMER_SP804=y +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=m +# CONFIG_PL320_MBOX is not set +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_OF_IOMMU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_EXTCON=m + +# +# Extcon Device Drivers +# +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +CONFIG_EXTCON_USB_GPIO=m +# CONFIG_MEMORY is not set +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 + +# +# Accelerometers +# +# CONFIG_BMA180 is not set +CONFIG_BMC150_ACCEL=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_KXCJK1013=m +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD799X is not set +# CONFIG_MAX1363 is not set +# CONFIG_MCP3422 is not set +# CONFIG_NAU7802 is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set + +# +# Amplifiers +# + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m + +# +# SSP Sensor Common +# +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5446 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# + +# +# Digital gyroscope sensors +# +# CONFIG_BMG160 is not set +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +# CONFIG_ITG3200 is not set + +# +# Humidity sensors +# +# CONFIG_DHT11 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set + +# +# Inertial measurement units +# +# CONFIG_KMX61 is not set +# CONFIG_INV_MPU6050_IIO is not set + +# +# Light sensors +# +# CONFIG_ACPI_ALS is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_BH1750=m +CONFIG_CM32181=m +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +# CONFIG_HID_SENSOR_PROX is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +CONFIG_STK3310=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL4531 is not set +# CONFIG_VCNL4000 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +# CONFIG_BMC150_MAGN is not set + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m + +# +# Triggers - standalone +# +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m + +# +# Pressure sensors +# +# CONFIG_BMP280 is not set +# CONFIG_HID_SENSOR_PRESS is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set + +# +# Lightning sensors +# + +# +# Proximity sensors +# +# CONFIG_SX9500 is not set + +# +# Temperature sensors +# +# CONFIG_MLX90614 is not set +# CONFIG_TMP006 is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_FMC=m +CONFIG_FMC_FAKEDEV=m +CONFIG_FMC_TRIVIAL=m +CONFIG_FMC_WRITE_EEPROM=m +CONFIG_FMC_CHARDEV=m + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +CONFIG_PHY_XGENE=y +# CONFIG_PHY_TUSB1210 is not set +CONFIG_POWERCAP=y +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RAS=y +# CONFIG_THUNDERBOLT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +CONFIG_LIBNVDIMM=y +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_BLK=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +# CONFIG_NVMEM is not set + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_DMIID=y +CONFIG_DMI_SYSFS=y + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_ARMSTUB=y +CONFIG_ACPI=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_CCA_REQUIRED=y +CONFIG_ACPI_EC_DEBUGFS=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_FAN=y +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_IPMI=m +# CONFIG_ACPI_CUSTOM_DSDT is not set +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_CUSTOM_METHOD=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_PMIC_OPREGION=y + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +# CONFIG_OCFS2_FS_STATS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FS_ENCRYPTION is not set +# CONFIG_F2FS_IO_TRACE is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_FSCACHE_OBJECT_LIST=y +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_HFSPLUS_FS_POSIX_ACL=y +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=m +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +# CONFIG_EXOFS_FS is not set +CONFIG_ORE=m +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y +CONFIG_PNFS_OBJLAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_SUNRPC_DEBUG=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_ACL=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SMB2=y +# CONFIG_CIFS_SMB311 is not set +CONFIG_CIFS_FSCACHE=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_SMALLDOS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_KVM_VFIO=y +CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_KVM_ARM_HOST=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +CONFIG_UNUSED_SYMBOLS=y +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +CONFIG_HEADERS_CHECK=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_VMACACHE is not set +# CONFIG_DEBUG_VM_RB is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_TIMER_STATS=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +CONFIG_SPARSE_RCU_POINTER=y +CONFIG_TORTURE_TEST=m +CONFIG_RCU_TORTURE_TEST=m +# CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT is not set +# CONFIG_RCU_TORTURE_TEST_SLOW_INIT is not set +# CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +# CONFIG_FUNCTION_GRAPH_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_STACK_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_PROBE_EVENTS is not set +CONFIG_DYNAMIC_FTRACE=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_ASYNC_RAID6_TEST=m +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +CONFIG_TEST_KSTRTOX=y +# CONFIG_TEST_RHASHTABLE is not set +CONFIG_BUILD_DOCSRC=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +CONFIG_KGDB_TESTS=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +# CONFIG_KGDB_KDB is not set +# CONFIG_ARM64_PTDUMP is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_BIG_KEYS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_INTEGRITY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +# CONFIG_CRYPTO_MCRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ABLK_HELPER=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_DD=m +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=m +CONFIG_CRYPTO_SHA2_ARM64_CE=m +CONFIG_CRYPTO_GHASH_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=m +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m +CONFIG_CRYPTO_CRC32_ARM64=m +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_CRC8=m +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=m +CONFIG_842_DECOMPRESS=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_CORDIC=m +# CONFIG_DDR is not set +CONFIG_MPILIB=m +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_SG_SPLIT is not set +CONFIG_ARCH_HAS_SG_CHAIN=y diff --git a/core/linux-armv8-rc/linux-armv8-rc.install b/core/linux-armv8-rc/linux-armv8-rc.install new file mode 100644 index 000000000..776af08bf --- /dev/null +++ b/core/linux-armv8-rc/linux-armv8-rc.install @@ -0,0 +1,31 @@ +# arg 1: the new package version +# arg 2: the old package version + +KERNEL_NAME=-armv8-rc +KERNEL_VERSION=4.3.rc5-1-ARCH + +post_install () { + # updating module dependencies + echo ">>> Updating module dependencies. Please wait ..." + depmod ${KERNEL_VERSION} + echo ">>> Generating initial ramdisk, using mkinitcpio. Please wait..." + mkinitcpio -p linux${KERNEL_NAME} +} + +post_upgrade() { + if findmnt --fstab -uno SOURCE /boot &>/dev/null && ! mountpoint -q /boot; then + echo "WARNING: /boot appears to be a separate partition but is not mounted." + fi + + # updating module dependencies + echo ">>> Updating module dependencies. Please wait ..." + depmod ${KERNEL_VERSION} + echo ">>> Generating initial ramdisk, using mkinitcpio. Please wait..." + mkinitcpio -p linux${KERNEL_NAME} +} + +post_remove() { + # also remove the compat symlinks + rm -f boot/initramfs-linux${KERNEL_NAME}.img + rm -f boot/initramfs-linux${KERNEL_NAME}-fallback.img +} diff --git a/core/linux-armv8-rc/linux.preset b/core/linux-armv8-rc/linux.preset new file mode 100644 index 000000000..24a16e2e7 --- /dev/null +++ b/core/linux-armv8-rc/linux.preset @@ -0,0 +1,14 @@ +# mkinitcpio preset file for the 'linux-armv8' package + +ALL_config="/etc/mkinitcpio.conf" +ALL_kver="4.2.0-1-ARCH" + +PRESETS=('default' 'fallback') + +#default_config="/etc/mkinitcpio.conf" +default_image="/boot/initramfs-linux.img" +#default_options="" + +#fallback_config="/etc/mkinitcpio.conf" +fallback_image="/boot/initramfs-linux-fallback.img" +fallback_options="-S autodetect"