From a6e0e494f7213d914963b2aea8e3ff0e9a0e978a Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 1 Jul 2017 15:16:35 +0100 Subject: [PATCH 02/11] ARM64: dts: marvell: armada37xx: Enable memory-mapped GIC CPU interface The Cortex-A53s that power the Armada-37xx SoCs are equipped with a GIC CPU interface that gets enabled when coupled with a GICv3 interrupt controller, such as the GIC-500 on the this SoC. Advertise the MMIO ranges provided by the CPUs, which enables (among other things) GICv2 guests to run under a hypervisor such as KVM. Signed-off-by: Marc Zyngier --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 592e95e5f633..fd26d31d2846 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -311,7 +311,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x1d00000 0x10000>, /* GICD */ - <0x1d40000 0x40000>; /* GICR */ + <0x1d40000 0x40000>, /* GICR */ + <0x1d80000 0x2000>, /* GICC */ + <0x1d90000 0x2000>, /* GICH */ + <0x1da0000 0x20000>; /* GICV */ interrupts = ; }; }; -- 2.13.3