From bea2c36629ed9c4c2ca35977331dc3479396aee7 Mon Sep 17 00:00:00 2001 From: Ashokkumar G <0xfee1dead.sa@gmail.com> Date: Mon, 26 Jan 2015 11:03:08 -0700 Subject: [PATCH 1/9] clk:mmp: Adding clocks of pxa168 peripherals for gplugd 1. Adding peripherals register address information 2. Changing clock names for sd driver reference sdhci-pxav2 3. Changing clock names for Display (LCD) controller Signed-off-by: Ashokkumar G <0xfee1dead.sa@gmail.com> --- drivers/clk/mmp/clk-pxa168.c | 241 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 191 insertions(+), 50 deletions(-) diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 014396b028a2..39a80fb2aefa 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -20,30 +20,137 @@ #include "clk.h" -#define APBC_RTC 0x28 -#define APBC_TWSI0 0x2c -#define APBC_KPC 0x30 -#define APBC_UART0 0x0 -#define APBC_UART1 0x4 -#define APBC_GPIO 0x8 -#define APBC_PWM0 0xc -#define APBC_PWM1 0x10 -#define APBC_PWM2 0x14 -#define APBC_PWM3 0x18 -#define APBC_SSP0 0x81c -#define APBC_SSP1 0x820 -#define APBC_SSP2 0x84c -#define APBC_SSP3 0x858 -#define APBC_SSP4 0x85c -#define APBC_TWSI1 0x6c -#define APBC_UART2 0x70 -#define APMU_SDH0 0x54 -#define APMU_SDH1 0x58 -#define APMU_USB 0x5c -#define APMU_DISP0 0x4c -#define APMU_CCIC0 0x50 -#define APMU_DFC 0x60 -#define MPMU_UART_PLL 0x14 +#define APBC_UART0 0x0000 +#define APBC_UART1 0x0004 +#define APBC_GPIO 0x0008 +#define APBC_PWM0 0x000c +#define APBC_PWM1 0x0010 +#define APBC_PWM2 0x0014 +#define APBC_PWM3 0x0018 +#define APBC_RTC 0x0028 +#define APBC_TWSI0 0x002c +#define APBC_KPC 0x0030 +#define APBC_TWSI1 0x006c +#define APBC_UART2 0x0070 +#define APBC_SSP0 0x081c +#define APBC_SSP1 0x0820 +#define APBC_SSP2 0x084c +#define APBC_SSP3 0x0858 +#define APBC_SSP4 0x085c + +#define APBC_UART1_CLK_RST 0x0000 /*UART1 Clock/Reset Control*/ +#define APBC_UART2_CLK_RST 0x0004 /*UART2 Clock/Reset Control*/ +#define APBC_GPIO_CLK_RST 0x0008 /*GPIO Clock/Reset Control*/ +#define APBC_PWM1_CLK_RST 0x000C /*PWM1 Clock/Reset Control*/ +#define APBC_PWM2_CLK_RST 0x0010 /*PWM2 Clock/Reset Control*/ +#define APBC_PWM3_CLK_RST 0x0014 /*PWM3 Clock/Reset Control*/ +#define APBC_PWM4_CLK_RST 0x0018 /*PWM4 Clock/Reset Control*/ +#define APBC_RTC_CLK_RST 0x0028 /*RTC Clock/Reset Control*/ +#define APBC_TWSI0_CLK_RST 0x002C /*TWSI0 Clock/Reset Control*/ +#define APBC_KPC_CLK_RST 0x0030 /*Keypad Controller Clock/Reset + Control*/ +#define APBC_TIMERS_CLK_RST 0x0034 /*Timers Clock/Reset Control*/ +#define APBC_AIB_CLK_RST 0x003C /*AIB Clock/Reset Control*/ +#define APBC_SW_JTAG_CLK_RST 0x0040 /*Software emulated JTAG + Clock/Reset Control*/ +#define APBC_ONEWIRE_CLK_RST 0x0048 /*OneWire Clock/Reset + Control*/ +#define APBC_PWR_TWSI_CLK_RST 0x006C /*PWR_TWSI Clock/Reset + Control*/ +#define APBC_UART3_CLK_RST 0x0070 /*UART3 Clock/Reset Control*/ +#define APBC_AC97_CLK_RST 0x0084 /*AC97 Clock/Reset Control*/ + +#define APBC_SSP0_CLK_RST 0x081C /*SSP1 Clock/Reset Control*/ +#define APBC_SSP1_CLK_RST 0x0820 /*SSP2 Clock/Reset Control*/ +#define APBC_SSP2_CLK_RST 0x084C /*SSP3 Clock/Reset Control*/ +#define APBC_SSP3_CLK_RST 0x0858 /*SSP4 Clock/Reset Control*/ +#define APBC_SSP4_CLK_RST 0x085C /*SSP5 Clock/Reset Control*/ + +#define MPMU_UART_PLL 0x0014 + +#define APMU_CCIC_GATE 0x0028 +#define APMU_IRE 0x0048 +#define APMU_DISP0 0x004c +#define APMU_CCIC0 0x0050 +#define APMU_SDH0 0x0054 +#define APMU_SDH1 0x0058 +#define APMU_USB 0x005c +#define APMU_DFC 0x0060 +#define APMU_DMA 0x0064 +#define APMU_GEU 0x0068 +#define APMU_BUS 0x006c +#define APMU_WAKE_CLR 0x007c +#define APMU_CCIC_DBG 0x0088 +#define APMU_GC 0x00cc +#define APMU_GC_PD 0x00d0 +#define APMU_SMC 0x00d4 +#define APMU_SDH2 0x00e0 +#define APMU_SDH3 0x00e4 +#define APMU_CF 0x00f0 +#define APMU_ICR 0x00f8 +#define APMU_ETH 0x00fc + +#define APMU_PCR 0x0000 +#define APMU_CCR 0x0004 +#define APMU_CCSR 0x000c +#define APMU_FC_TIMER 0x0010 +#define APMU_CP_IDLE_CFG 0x0014 /*Not listed in PXA16X + Document*/ +#define APMU_IDLE_CFG 0x0018 +#define APMU_LCD_CLK_RES_CTRL 0x004c +#define APMU_CCIC_CLK_RES_CTRL 0x0050 +#define APMU_SDH0_CLK_RES_CTRL 0x0054 /*SD1*/ +#define APMU_SDH1_CLK_RES_CTRL 0x0058 /*SD2*/ +#define APMU_SDH2_CLK_RES_CTRL 0x00e0 /*SD3*/ +#define APMU_SDH3_CLK_RES_CTRL 0x00e4 /*SD4*/ +#define APMU_USB_CLK_RES_CTRL 0x005c +#define APMU_NFC_CLK_RES_CTRL 0x0060 /*NAND Flash Controller + Clock/Reset*/ +#define APMU_DMA_CLK_RES_CTRL 0x0064 /*DMA Clock/Reset Control*/ +#define APMU_BUS_CLK_RES_CTRL 0x006c /*Bus Clock/Reste Control*/ +#define APMU_WAKE_CLK 0x007c /*Wake Clear*/ +#define APMU_PWR_STBL_TIMER 0x0084 /*Not listed in PXA16X + Document*/ +#define APMU_SRAM_PWR_DWN 0x008c /*Not listed in PXA16X + Document*/ +#define APMU_CORE_STATUS 0x0090 /*Core Status*/ +#define APMU_RES_FRM_SLP_CLR 0x0094 /*Resume from Sleep clear*/ +#define APMU_IMR 0x0098 /*PMU Interrupt Mask*/ +#define APMU_IRWC 0x009c /*Interrupt RD/WR Clear*/ +#define APMU_ISR 0x00a0 /*Interrupt Status*/ +#define APMU_DX8_CLK_RES_CTRL 0x00a4 /*Not listed in PXA16X + Document*/ +#define APMU_DTC_CLK_RES_CTRL 0x00ac /*Not listed in PXA16X + Document*/ +#define APMU_MC_HW_SLP_TYPE 0x00b0 /*Memory Controller Hardware + Sleep Type*/ +#define APMU_MC_SLP_REQ 0x00b4 /*Memory Controller Sleep + Request*/ +#define APMU_MC_SW_SLP_TYPE 0x00c0 /*Memory Controller Software + Sleep Type*/ +#define APMU_PLL_SEL_STATUS 0x00c4 /*PLL Clock select status*/ +#define APMU_SYNC_MODE_BYPASS 0x00c8 /*Sync Mode Bypass*/ +#define APMU_GC_CLK_RES_CTRL 0x00cc /*GC300 2D Graphics Controller + Clock/Reset control*/ +#define APMU_SMC_CLK_RES_CTRL 0x00d4 /*Static Memory controller + Clock/Reset control*/ +#define APMU_XD_CLK_RES_CTRL 0x00dc /*XD Controller clock/reset + control*/ +#define APMU_CF_CLK_RES_CTRL 0x00f0 /*Compact Flash controller + clock/reset control*/ +#define APMU_MSP_CLK_RES_CTRL 0x00f4 /*Memory Stick Pro clock/reset + control*/ +#define APMU_CMU_CLK_RES_CTRL 0x00f8 /*CMU clock/reset control*/ +#define APMU_MFU_CLK_RES_CTRL 0x00fc /*FE(Fast Ethernet) + clock/reset control*/ +#define APMU_PCIe_CLK_RES_CTRL 0x0100 /*PCIe clock/reset control*/ +#define APMU_EPD_CLK_RES_CTRL 0x0104 /*EPD clock/reset control*/ + +#define APMU_GC_156M 0x0 +#define APMU_GC_312M 0x40 +#define APMU_GC_PLL2 0x80 +#define APMU_GC_PLL2_DIV2 0xc0 +#define APMU_GC_624M 0xc0 /* added according to Aspen SW spec v2.8*/ static DEFINE_SPINLOCK(clk_lock); @@ -235,11 +342,11 @@ void __init pxa168_clk_init(void) ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); - clk_register_clkdev(clk, "uart_mux.0", NULL); + clk_register_clkdev(clk, "ssp_mux.0", NULL); clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); + 0, 0, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-ssp.0"); clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, ARRAY_SIZE(ssp_parent), @@ -248,8 +355,8 @@ void __init pxa168_clk_init(void) clk_register_clkdev(clk, "ssp_mux.1", NULL); clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); + 0, 0, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-ssp.1"); clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, ARRAY_SIZE(ssp_parent), @@ -257,9 +364,9 @@ void __init pxa168_clk_init(void) apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.2", NULL); - clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.2"); + clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", apbc_base + APBC_SSP2, + 0, 0, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-ssp.2"); clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, ARRAY_SIZE(ssp_parent), @@ -267,9 +374,9 @@ void __init pxa168_clk_init(void) apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.3", NULL); - clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.3"); + clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", apbc_base + APBC_SSP3, + 0, 0, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-ssp.3"); clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, ARRAY_SIZE(ssp_parent), @@ -277,9 +384,9 @@ void __init pxa168_clk_init(void) apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.4", NULL); - clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, - 10, 0, &clk_lock); - clk_register_clkdev(clk, NULL, "mmp-ssp.4"); + clk = mmp_clk_register_apbc("ssp4", "ssp4_mux", apbc_base + APBC_SSP4, + 0, 0, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-ssp.4"); clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b, &clk_lock); @@ -291,9 +398,9 @@ void __init pxa168_clk_init(void) apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); clk_register_clkdev(clk, "sdh0_mux", NULL); - clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, + clk = mmp_clk_register_apmu("sdh0", "sdh0_mux", apmu_base + APMU_SDH0, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); + clk_register_clkdev(clk, NULL, "sdhci-pxav2.0"); clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, ARRAY_SIZE(sdh_parent), @@ -303,29 +410,59 @@ void __init pxa168_clk_init(void) clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, 0x1b, &clk_lock); - clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); + clk_register_clkdev(clk, NULL, "sdhci-pxav2.1"); - clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, - 0x9, &clk_lock); - clk_register_clkdev(clk, "usb_clk", NULL); + clk = clk_register_mux(NULL, "sdh2_mux", sdh_parent, + ARRAY_SIZE(sdh_parent), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + apmu_base + APMU_SDH2, 6, 1, 0, &clk_lock); + clk_register_clkdev(clk, "sdh2_mux", NULL); + + clk = mmp_clk_register_apmu("sdh2", "sdh2_mux", apmu_base + APMU_SDH2, + 0x1b, &clk_lock); + clk_register_clkdev(clk, NULL, "sdhci-pxav2.2"); + + clk = clk_register_mux(NULL, "sdh3_mux", sdh_parent, + ARRAY_SIZE(sdh_parent), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + apmu_base + APMU_SDH3, 6, 1, 0, &clk_lock); + clk_register_clkdev(clk, "sdh3_mux", NULL); - clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, + clk = mmp_clk_register_apmu("sdh3", "sdh3_mux", apmu_base + APMU_SDH3, + 0x1b, &clk_lock); + clk_register_clkdev(clk, NULL, "sdhci-pxav2.3"); + + clk = mmp_clk_register_apmu("sph", "pxa-sph", apmu_base + APMU_USB, 0x12, &clk_lock); - clk_register_clkdev(clk, "sph_clk", NULL); + clk_register_clkdev(clk, NULL, "pxa-sph"); + + clk = mmp_clk_register_apmu("usb", "pxa-u2oehci", apmu_base + APMU_USB, + 0x09, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa-u2oehci"); - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, + clk = clk_register_mux(NULL, "LCDCLK", disp_parent, + ARRAY_SIZE(disp_parent), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + apmu_base + APMU_DISP0, 0, 7, 0, &clk_lock); + clk_register_clkdev(clk, "LCDCLK", NULL); + + /*clk = clk_register_mux(NULL, "disp0_mux", disp_parent, ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); - clk_register_clkdev(clk, "disp_mux.0", NULL); + clk_register_clkdev(clk, "disp_mux.0", NULL);*/ + + clk = mmp_clk_register_apmu("disp0", "LCDCLK", + apmu_base + APMU_DISP0, 0x7f, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-fb"); - clk = mmp_clk_register_apmu("disp0", "disp0_mux", + /*clk = mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0, 0x1b, &clk_lock); clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", apmu_base + APMU_DISP0, 0x24, &clk_lock); - clk_register_clkdev(clk, "hclk", "mmp-disp.0"); + clk_register_clkdev(clk, "hclk", "mmp-disp.0");*/ clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, ARRAY_SIZE(ccic_parent), @@ -355,4 +492,8 @@ void __init pxa168_clk_init(void) clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", apmu_base + APMU_CCIC0, 0x300, &clk_lock); clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); + + clk = mmp_clk_register_apmu("eth", "pxa168-eth", apmu_base + APMU_ETH, + 0x9, &clk_lock); + clk_register_clkdev(clk, NULL, "pxa168-eth"); } -- 2.14.1