From 61f340e9b751bca4cd9178d34d08cdf04893e156 Mon Sep 17 00:00:00 2001 From: Victor Gu Date: Fri, 24 Mar 2017 20:41:55 +0800 Subject: [PATCH 11/11] fix: pcie: aardvark: correct the default MAX payload size The previous PCIe MAX payload field is set to 7 which is undefined value according to functional specification. The default PICe host controller MAX payload size should be set to 512 bytes according to specification. Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9 Signed-off-by: Victor Gu Reviewed-on: http://vgitil04.il.marvell.com:8080/37926 Tested-by: iSoC Platform CI Reviewed-by: Evan Wang --- drivers/pci/host/pci-aardvark.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c index 0407c8cb89fb..cac1558b8d3b 100644 --- a/drivers/pci/host/pci-aardvark.c +++ b/drivers/pci/host/pci-aardvark.c @@ -30,6 +30,7 @@ #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 #define PCIE_CORE_MPS_UNIT_BYTE 128 @@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* Set PCIe Device Control and Status 1 PF0 register */ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | - (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | + (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); -- 2.13.3