mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2024-12-08 23:03:46 +00:00
49 lines
2 KiB
Diff
49 lines
2 KiB
Diff
From 2c82a1ee1e896cd5e12f971e142282fc98694ca6 Mon Sep 17 00:00:00 2001
|
|
From: Evan Wang <xswang@marvell.com>
|
|
Date: Fri, 8 Sep 2017 11:53:47 +0200
|
|
Subject: [PATCH 7/7] PCI: aardvark: fix PCIe max read request size setting
|
|
|
|
There is an obvious typo issue in the definition of the PCIe maximum
|
|
read request size: a bit shift is directly used as a value, while it
|
|
should be used to shift the correct value.
|
|
|
|
This is part of fixing bug
|
|
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
|
reported as the user to be important to get a Intel 7260 mini-PCIe
|
|
WiFi card working.
|
|
|
|
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
|
Signed-off-by: Evan Wang <xswang@marvell.com>
|
|
Reviewed-by: Victor Gu <xigu@marvell.com>
|
|
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
|
[Thomas: tweak commit log.]
|
|
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
---
|
|
drivers/pci/host/pci-aardvark.c | 4 +++-
|
|
1 file changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
|
|
index 5526d83a0c4d..249a088b463c 100644
|
|
--- a/drivers/pci/host/pci-aardvark.c
|
|
+++ b/drivers/pci/host/pci-aardvark.c
|
|
@@ -33,6 +33,7 @@
|
|
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
|
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
|
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
|
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
|
|
#define PCIE_CORE_MPS_UNIT_BYTE 128
|
|
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
|
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
|
@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
|
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
|
|
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
|
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
|
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
|
|
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
|
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
|
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
|
|
|
/* Program PCIe Control 2 to disable strict ordering */
|
|
--
|
|
2.15.0
|
|
|