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38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From 00e0b98f95698b734a037abe2d3007dbc730c20e Mon Sep 17 00:00:00 2001
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From: Fabio Estevam <fabio.estevam@freescale.com>
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Date: Sun, 5 May 2013 16:11:59 +0000
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Subject: [PATCH 12/15] mxs: Explain why some mx23 DDR registers are not
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configured
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Put an explanation in the source code as to why some DDR registers do not
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need to be configured.
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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---
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arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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index 4ed197b..3902406 100644
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--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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@@ -127,6 +127,15 @@ static void initialize_dram_values(void)
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mxs_adjust_memory_params(dram_vals);
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+ /*
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+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
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+ * per FSL bootlets code.
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+ *
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+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
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+ * "reserved".
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+ * HW_DRAM_CTL8 is setup as the last element.
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+ * So skip the initialization of these HW_DRAM_CTL registers.
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+ */
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
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if (i == 8 || i == 27 || i == 28 || i == 35)
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continue;
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--
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1.8.2.2
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