mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
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106 lines
3 KiB
Diff
106 lines
3 KiB
Diff
From d561d593c0a1352748fc8ae4d04a264d33ca9cbe Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 24 Mar 2017 20:52:30 +0800
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Subject: [PATCH 10/12] pci: aardvard: set host and device to the same MAX
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payload size
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Since the Aardvard does not implement PCIe root bus, the Linux PCIe
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framework will not align the MAX payload size between host and device
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for it.
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This patch sets host and device to the same MAX payload size in Aardvard
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PCIe driver.
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Change-Id: I3979397b3af98911c067f7ad384922aa3f05497f
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/37927
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 56 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 56 insertions(+)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 10154dcf219b..0407c8cb89fb 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -32,6 +32,7 @@
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -886,6 +887,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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return err;
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}
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
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+
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+ return 0;
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+}
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+
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
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+{
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+ int mps;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
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+ pcie_set_mps(dev, mps);
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
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+{
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
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+ u32 reg;
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+
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
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+
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+ /* Configure RC MAX payload size */
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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+
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+ /* Configure device MAX payload size */
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
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+}
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+
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -948,6 +1001,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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+ /* Configure the MAX pay load size */
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+ advk_pcie_configure_mps(bus, pcie);
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+
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pci_bus_add_devices(bus);
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return 0;
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}
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--
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2.13.3
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