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https://github.com/archlinuxarm/PKGBUILDs.git
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42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From fda5a9a782796bd12e295ab77330c5802a4b9190 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:46 +0200
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Subject: [PATCH 10/11] PCI: aardvark: disable LOS state by default
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Some PCIe devices do not support LOS, and will cause timeouts if the
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root complex forces the LOS state. This patch disables the LOS state
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by default.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index d5c2819e17fa..eb0b54506d4e 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -369,8 +369,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_pcie_wait_for_link(pcie);
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- reg = PCIE_CORE_LINK_L0S_ENTRY |
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- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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--
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2.14.2
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