mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2024-12-08 23:03:46 +00:00
1685 lines
53 KiB
Diff
1685 lines
53 KiB
Diff
From 22efc5d711cf5a91a236b3a54f94cbcad0fc7b5e Mon Sep 17 00:00:00 2001
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From: Kevin Mihelich <kevin@archlinuxarm.org>
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Date: Sat, 29 Aug 2015 08:56:32 -0600
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Subject: [PATCH 5/6] chiliboard support
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---
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board/grinn/chiliboard/Makefile | 13 +
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board/grinn/chiliboard/board.c | 447 +++++++++++++++++++
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board/grinn/chiliboard/board.h | 20 +
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board/grinn/chiliboard/mux.c | 99 +++++
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board/grinn/chiliboard/u-boot.lds | 131 ++++++
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boards.cfg | 5 +
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drivers/mtd/nand/omap_gpmc.c | 6 +-
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include/configs/chiliboard.h | 878 ++++++++++++++++++++++++++++++++++++++
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8 files changed, 1597 insertions(+), 2 deletions(-)
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create mode 100644 board/grinn/chiliboard/Makefile
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create mode 100644 board/grinn/chiliboard/board.c
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create mode 100644 board/grinn/chiliboard/board.h
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create mode 100644 board/grinn/chiliboard/mux.c
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create mode 100644 board/grinn/chiliboard/u-boot.lds
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create mode 100644 include/configs/chiliboard.h
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diff --git a/board/grinn/chiliboard/Makefile b/board/grinn/chiliboard/Makefile
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new file mode 100644
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index 0000000..804ac37
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--- /dev/null
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+++ b/board/grinn/chiliboard/Makefile
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@@ -0,0 +1,13 @@
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+#
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+# Makefile
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+#
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+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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+obj-y := mux.o
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+endif
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+
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+obj-y += board.o
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diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
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new file mode 100644
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index 0000000..ed8ab63
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--- /dev/null
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+++ b/board/grinn/chiliboard/board.c
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@@ -0,0 +1,447 @@
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+/*
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+ * board.c
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+ *
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+ * Board functions for Grinn chiliboard, AM335X based boards
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+ *
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+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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+ *
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+ * Copyright (C) 2015, Grinn - http://www.grinn-global.com
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+ * Grzegorz Glomb, g.glomb@grinn-global.com
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <errno.h>
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+#include <spl.h>
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/hardware.h>
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+#include <asm/arch/omap.h>
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+#include <asm/arch/ddr_defs.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/gpio.h>
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+#include <asm/arch/mmc_host_def.h>
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+#include <asm/arch/sys_proto.h>
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+#include <asm/arch/mem.h>
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+#include <asm/io.h>
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+#include <asm/emif.h>
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+#include <asm/gpio.h>
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+#include <i2c.h>
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+#include <miiphy.h>
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+#include <cpsw.h>
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+#include <power/tps65217.h>
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+#include <power/tps65910.h>
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+#include <environment.h>
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+#include <watchdog.h>
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+#include <environment.h>
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+#include "board.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+#define HDR_NAME_LEN 8
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+
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+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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+
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+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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+static const struct ddr_data ddr2_chilisom_gcs1_data = {
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+ .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
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+ (MT47H128M16RT25E_RD_DQS<<20) |
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+ (MT47H128M16RT25E_RD_DQS<<10) |
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+ (MT47H128M16RT25E_RD_DQS<<0)),
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+ .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
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+ (MT47H128M16RT25E_WR_DQS<<20) |
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+ (MT47H128M16RT25E_WR_DQS<<10) |
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+ (MT47H128M16RT25E_WR_DQS<<0)),
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+ .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
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+ (MT47H128M16RT25E_PHY_WRLVL<<20) |
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+ (MT47H128M16RT25E_PHY_WRLVL<<10) |
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+ (MT47H128M16RT25E_PHY_WRLVL<<0)),
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+ .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
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+ (MT47H128M16RT25E_PHY_GATELVL<<20) |
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+ (MT47H128M16RT25E_PHY_GATELVL<<10) |
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+ (MT47H128M16RT25E_PHY_GATELVL<<0)),
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+ .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
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+ (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
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+ (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
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+ (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
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+ .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
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+ (MT47H128M16RT25E_PHY_WR_DATA<<20) |
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+ (MT47H128M16RT25E_PHY_WR_DATA<<10) |
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+ (MT47H128M16RT25E_PHY_WR_DATA<<0)),
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+};
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+
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+static const struct cmd_control ddr2_chilisom_gcs1_cmd_ctrl_data = {
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+ .cmd0csratio = MT47H128M16RT25E_RATIO,
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+ .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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+
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+ .cmd1csratio = MT47H128M16RT25E_RATIO,
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+ .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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+
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+ .cmd2csratio = MT47H128M16RT25E_RATIO,
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+ .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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+};
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+
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+static const struct emif_regs ddr2_chilisom_gcs1_emif_reg_data = {
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+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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+};
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+
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+static const struct ddr_data ddr3_chilisom_gcs2_data = {
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+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
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+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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+};
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+
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+static const struct cmd_control ddr3_chilisom_gcs2_cmd_ctrl_data = {
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+ .cmd0csratio = MT41K256M16HA125E_RATIO,
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+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+
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+ .cmd1csratio = MT41K256M16HA125E_RATIO,
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+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+
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+ .cmd2csratio = MT41K256M16HA125E_RATIO,
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+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+};
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+
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+static struct emif_regs ddr3_chilisom_gcs2_emif_reg_data = {
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+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
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+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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+};
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+
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+#ifdef CONFIG_SPL_OS_BOOT
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+int spl_start_uboot(void)
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+{
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+ /* break into full u-boot on 'c' */
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+ if (serial_tstc() && serial_getc() == 'c')
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+ return 1;
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+
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+#ifdef CONFIG_SPL_ENV_SUPPORT
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+ env_init();
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+ env_relocate_spec();
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+ if (getenv_yesno("boot_os") != 1)
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+ return 1;
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+#endif
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+
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+ return 0;
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+}
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+#endif
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+
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+#define OSC (V_OSCK/1000000)
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+const struct dpll_params dpll_ddr_chilisom_gcs1 = {
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+ 266, OSC-1, 1, -1, -1, -1, -1};
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+const struct dpll_params dpll_ddr_chilisom_gcs2 = {
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+ 400, OSC-1, 1, -1, -1, -1, -1};
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+
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+void am33xx_spl_board_init(void)
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+{
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+ int mpu_vdd;
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+
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+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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+
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+ int usb_cur_lim;
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+
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+ if (i2c_probe(TPS65217_CHIP_PM))
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+ return;
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+
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+ uchar pmic_status_reg;
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+ if (tps65217_reg_read(TPS65217_STATUS, &pmic_status_reg))
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+ return;
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+ if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
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+ puts("No AC power, disabling frequency switch\n");
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+ return;
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+ }
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+
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+ /*
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+ * Increase USB current limit to 1300mA or 1800mA and set
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+ * the MPU voltage controller as needed.
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+ */
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+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
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+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
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+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
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+ } else {
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+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
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+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
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+ }
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+
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+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
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+ TPS65217_POWER_PATH,
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+ usb_cur_lim,
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+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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+ puts("tps65217_reg_write failure\n");
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+
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+ /* Set DCDC3 (CORE) voltage to 1.125V */
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+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
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+ puts("tps65217_voltage_update failure\n");
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+ return;
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+ }
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+
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+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
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+ puts("tps65217_voltage_update failure\n");
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+ return;
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+ }
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+
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+ /* Set LDO3, LDO4 output voltage to 3.3V for GCS1.
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+ * Set LDO3 to 1.8V and LDO4 to 3.3V for GCS2. */
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+
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+ #ifdef CONFIG_CHILISOM_GCS2
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+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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+ TPS65217_DEFLS1,
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+ TPS65217_LDO_VOLTAGE_OUT_1_8,
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+ TPS65217_LDO_MASK))
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+ puts("tps65217_reg_write failure\n");
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+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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+ TPS65217_DEFLS2,
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+ TPS65217_LDO_VOLTAGE_OUT_3_3,
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+ TPS65217_LDO_MASK))
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+ puts("tps65217_reg_write failure\n");
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+ #else
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+
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+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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+ TPS65217_DEFLS1,
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+ TPS65217_LDO_VOLTAGE_OUT_3_3,
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+ TPS65217_LDO_MASK))
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+ puts("tps65217_reg_write failure\n");
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+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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+ TPS65217_DEFLS2,
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+ TPS65217_LDO_VOLTAGE_OUT_3_3,
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+ TPS65217_LDO_MASK))
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+ puts("tps65217_reg_write failure\n");
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+ #endif
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+
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+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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+}
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+
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+const struct dpll_params *get_dpll_ddr_params(void)
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+{
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+ enable_i2c0_pin_mux();
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+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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+
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+#ifndef CONFIG_CHILISOM_GCS2
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+ return &dpll_ddr_chilisom_gcs1;
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+#else
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+ return &dpll_ddr_chilisom_gcs2;
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+#endif
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+}
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+
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+void set_uart_mux_conf(void)
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+{
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+#ifdef CONFIG_SERIAL1
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+ enable_uart0_pin_mux();
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+#endif /* CONFIG_SERIAL1 */
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+}
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+
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+void set_mux_conf_regs(void)
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+{
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+ enable_board_pin_mux();
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+}
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+
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+const struct ctrl_ioregs ioregs_chilisom_gcs1 = {
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+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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+};
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+
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+const struct ctrl_ioregs ioregs_chilisom_gcs2 = {
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+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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+};
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+
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+void sdram_init(void)
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+{
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+#ifndef CONFIG_CHILISOM_GCS2
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+ config_ddr(266, &ioregs_chilisom_gcs1,
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+ &ddr2_chilisom_gcs1_data,
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+ &ddr2_chilisom_gcs1_cmd_ctrl_data,
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+ &ddr2_chilisom_gcs1_emif_reg_data, 0);
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+#else
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+ config_ddr(400, &ioregs_chilisom_gcs2,
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+ &ddr3_chilisom_gcs2_data,
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+ &ddr3_chilisom_gcs2_cmd_ctrl_data,
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+ &ddr3_chilisom_gcs2_emif_reg_data, 0);
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+#endif
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+}
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+#endif
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+
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+/*
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+ * Basic board specific setup. Pinmux has been handled already.
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+ */
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+int board_init(void)
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+{
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+#if defined(CONFIG_HW_WATCHDOG)
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+ hw_watchdog_init();
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+#endif
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+
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+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
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+ gpmc_init();
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+#endif
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+ return 0;
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+}
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+
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+#ifdef CONFIG_BOARD_LATE_INIT
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+int board_late_init(void)
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+{
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+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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+ char safe_string[HDR_NAME_LEN + 1];
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+
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+ /* Now set variables based on the header. */
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+ strncpy(safe_string, (char *)"CHILISOM", 8);
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+ safe_string[8] = 0;
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+ setenv("board_name", safe_string);
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+
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+#ifndef CONFIG_CHILISOM_GCS2
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+ strncpy(safe_string, (char *)"1.1", 3);
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+ safe_string[3] = 0;
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+ setenv("board_rev", safe_string);
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+#else
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+ strncpy(safe_string, (char *)"2.2", 3);
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+ safe_string[3] = 0;
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+ setenv("board_rev", safe_string);
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+#endif
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+#endif
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+ return 0;
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+}
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+#endif
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+
|
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+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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+static void cpsw_control(int enabled)
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+{
|
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+ /* VTP can be added here */
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+
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+ return;
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+}
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+
|
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+static struct cpsw_slave_data cpsw_slaves[] = {
|
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+ {
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+ .slave_reg_ofs = 0x208,
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+ .sliver_reg_ofs = 0xd80,
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+ .phy_addr = 0,
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+ },
|
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+ {
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+ .slave_reg_ofs = 0x308,
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+ .sliver_reg_ofs = 0xdc0,
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+ .phy_addr = 1,
|
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+ },
|
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+};
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+
|
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+static struct cpsw_platform_data cpsw_data = {
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+ .mdio_base = CPSW_MDIO_BASE,
|
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+ .cpsw_base = CPSW_BASE,
|
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+ .mdio_div = 0xff,
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+ .channels = 8,
|
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+ .cpdma_reg_ofs = 0x800,
|
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+ .slaves = 1,
|
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+ .slave_data = cpsw_slaves,
|
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+ .ale_reg_ofs = 0xd00,
|
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+ .ale_entries = 1024,
|
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+ .host_port_reg_ofs = 0x108,
|
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+ .hw_stats_reg_ofs = 0x900,
|
|
+ .bd_ram_ofs = 0x2000,
|
|
+ .mac_control = (1 << 5),
|
|
+ .control = cpsw_control,
|
|
+ .host_port_num = 0,
|
|
+ .version = CPSW_CTRL_VERSION_2,
|
|
+};
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * This function will:
|
|
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
|
|
+ * in the environment
|
|
+ * Perform fixups to the PHY present on certain boards. We only need this
|
|
+ * function in:
|
|
+ * - SPL with either CPSW or USB ethernet support
|
|
+ * - Full U-Boot, with either CPSW or USB ethernet
|
|
+ * Build in only these cases to avoid warnings about unused variables
|
|
+ * when we build an SPL that has neither option but full U-Boot will.
|
|
+ */
|
|
+
|
|
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
|
|
+ && defined(CONFIG_SPL_BUILD)) || \
|
|
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
|
|
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
|
|
+ !defined(CONFIG_SPL_BUILD))
|
|
+int board_eth_init(bd_t *bis)
|
|
+{
|
|
+ int rv, n = 0;
|
|
+ uint8_t mac_addr[6];
|
|
+ uint32_t mac_hi, mac_lo;
|
|
+
|
|
+ /* try reading mac address from efuse */
|
|
+ mac_lo = readl(&cdev->macid0l);
|
|
+ mac_hi = readl(&cdev->macid0h);
|
|
+ mac_addr[0] = mac_hi & 0xFF;
|
|
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
|
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
|
+ mac_addr[4] = mac_lo & 0xFF;
|
|
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
|
+
|
|
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
|
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
|
+ if (!getenv("ethaddr")) {
|
|
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
|
+
|
|
+ if (is_valid_ether_addr(mac_addr))
|
|
+ eth_setenv_enetaddr("ethaddr", mac_addr);
|
|
+ }
|
|
+
|
|
+#ifdef CONFIG_DRIVER_TI_CPSW
|
|
+
|
|
+ mac_lo = readl(&cdev->macid1l);
|
|
+ mac_hi = readl(&cdev->macid1h);
|
|
+ mac_addr[0] = mac_hi & 0xFF;
|
|
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
|
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
|
+ mac_addr[4] = mac_lo & 0xFF;
|
|
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
|
+
|
|
+ if (!getenv("eth1addr")) {
|
|
+ if (is_valid_ether_addr(mac_addr))
|
|
+ eth_setenv_enetaddr("eth1addr", mac_addr);
|
|
+ }
|
|
+
|
|
+ /* writel(MII_MODE_ENABLE, &cdev->miisel); */
|
|
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
|
|
+
|
|
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
|
|
+
|
|
+ rv = cpsw_register(&cpsw_data);
|
|
+ if (rv < 0)
|
|
+ printf("Error %d registering CPSW switch\n", rv);
|
|
+ else
|
|
+ n += rv;
|
|
+#endif
|
|
+#endif
|
|
+#if defined(CONFIG_USB_ETHER) && \
|
|
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
|
|
+ if (is_valid_ether_addr(mac_addr))
|
|
+ eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
|
|
+
|
|
+ rv = usb_eth_initialize(bis);
|
|
+ if (rv < 0)
|
|
+ printf("Error %d registering USB_ETHER\n", rv);
|
|
+ else
|
|
+ n += rv;
|
|
+#endif
|
|
+ return n;
|
|
+}
|
|
+#endif
|
|
diff --git a/board/grinn/chiliboard/board.h b/board/grinn/chiliboard/board.h
|
|
new file mode 100644
|
|
index 0000000..6753e74
|
|
--- /dev/null
|
|
+++ b/board/grinn/chiliboard/board.h
|
|
@@ -0,0 +1,20 @@
|
|
+/*
|
|
+ * board.h
|
|
+ *
|
|
+ * Grinn AM335x boards information header
|
|
+ *
|
|
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
|
+ *
|
|
+ * Copyright (C) 2015, Grinn - http://www.grinn-global.com
|
|
+ * Grzegorz Glomb, g.glomb@grinn-global.com
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#ifndef _BOARD_H_
|
|
+#define _BOARD_H_
|
|
+
|
|
+void enable_uart0_pin_mux(void);
|
|
+void enable_i2c0_pin_mux(void);
|
|
+void enable_board_pin_mux(void);
|
|
+#endif
|
|
diff --git a/board/grinn/chiliboard/mux.c b/board/grinn/chiliboard/mux.c
|
|
new file mode 100644
|
|
index 0000000..644f211
|
|
--- /dev/null
|
|
+++ b/board/grinn/chiliboard/mux.c
|
|
@@ -0,0 +1,99 @@
|
|
+/*
|
|
+ * mux.c
|
|
+ *
|
|
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
|
+ *
|
|
+ * Copyright (C) 2015, Grinn - http://www.grinn-global.com
|
|
+ * Grzegorz Glomb, g.glomb@grinn-global.com
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <asm/arch/sys_proto.h>
|
|
+#include <asm/arch/hardware.h>
|
|
+#include <asm/arch/mux.h>
|
|
+#include <asm/io.h>
|
|
+#include <i2c.h>
|
|
+#include "board.h"
|
|
+
|
|
+static struct module_pin_mux uart0_pin_mux[] = {
|
|
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
|
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
|
+ {-1},
|
|
+};
|
|
+
|
|
+static struct module_pin_mux mmc0_pin_mux[] = {
|
|
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
|
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
|
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
|
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
|
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
|
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
|
+ {-1},
|
|
+};
|
|
+
|
|
+static struct module_pin_mux i2c0_pin_mux[] = {
|
|
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
|
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
|
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
|
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
|
+ {-1},
|
|
+};
|
|
+
|
|
+static struct module_pin_mux rmii1_pin_mux[] = {
|
|
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
|
|
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
|
|
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
|
|
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
|
|
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
|
|
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
|
|
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
|
|
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
|
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
|
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
|
|
+ {-1},
|
|
+};
|
|
+
|
|
+static struct module_pin_mux nand_pin_mux[] = {
|
|
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
|
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
|
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
|
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
|
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
|
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
|
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
|
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
|
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
|
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
|
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
|
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
|
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
|
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
|
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
|
+ {-1},
|
|
+};
|
|
+
|
|
+void enable_uart0_pin_mux(void)
|
|
+{
|
|
+ configure_module_pin_mux(uart0_pin_mux);
|
|
+}
|
|
+
|
|
+void enable_i2c0_pin_mux(void)
|
|
+{
|
|
+ configure_module_pin_mux(i2c0_pin_mux);
|
|
+}
|
|
+
|
|
+void enable_board_pin_mux(void)
|
|
+{
|
|
+ /* chiliboard pinmux */
|
|
+ configure_module_pin_mux(rmii1_pin_mux);
|
|
+ configure_module_pin_mux(nand_pin_mux);
|
|
+ configure_module_pin_mux(mmc0_pin_mux);
|
|
+
|
|
+#ifndef CONFIG_CHILISOM_GCS2
|
|
+ puts("Configuration for Chilisom GCS1\n");
|
|
+#else
|
|
+ puts("Configuration for Chilisom GCS2\n");
|
|
+#endif
|
|
+}
|
|
diff --git a/board/grinn/chiliboard/u-boot.lds b/board/grinn/chiliboard/u-boot.lds
|
|
new file mode 100644
|
|
index 0000000..bf70d88
|
|
--- /dev/null
|
|
+++ b/board/grinn/chiliboard/u-boot.lds
|
|
@@ -0,0 +1,131 @@
|
|
+/*
|
|
+ * Copyright (c) 2004-2008 Texas Instruments
|
|
+ *
|
|
+ * (C) Copyright 2002
|
|
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
|
+ *
|
|
+ * Copyright (C) 2015, Grinn - http://www.grinn-global.com
|
|
+ * Grzegorz Glomb, g.glomb@grinn-global.com
|
|
+ *
|
|
+ * See file CREDITS for list of people who contributed to this
|
|
+ * project.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
+ * MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
|
+OUTPUT_ARCH(arm)
|
|
+ENTRY(_start)
|
|
+SECTIONS
|
|
+{
|
|
+ . = 0x00000000;
|
|
+
|
|
+ . = ALIGN(4);
|
|
+ .text :
|
|
+ {
|
|
+ *(.__image_copy_start)
|
|
+ *(.vectors)
|
|
+ CPUDIR/start.o (.text*)
|
|
+ board/grinn/chiliboard/built-in.o (.text*)
|
|
+ *(.text*)
|
|
+ }
|
|
+
|
|
+ . = ALIGN(4);
|
|
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
|
+
|
|
+ . = ALIGN(4);
|
|
+ .data : {
|
|
+ *(.data*)
|
|
+ }
|
|
+
|
|
+ . = ALIGN(4);
|
|
+
|
|
+ . = .;
|
|
+
|
|
+ . = ALIGN(4);
|
|
+ .u_boot_list : {
|
|
+ KEEP(*(SORT(.u_boot_list*)));
|
|
+ }
|
|
+
|
|
+ . = ALIGN(4);
|
|
+
|
|
+ .image_copy_end :
|
|
+ {
|
|
+ *(.__image_copy_end)
|
|
+ }
|
|
+
|
|
+ .rel_dyn_start :
|
|
+ {
|
|
+ *(.__rel_dyn_start)
|
|
+ }
|
|
+
|
|
+ .rel.dyn : {
|
|
+ *(.rel*)
|
|
+ }
|
|
+
|
|
+ .rel_dyn_end :
|
|
+ {
|
|
+ *(.__rel_dyn_end)
|
|
+ }
|
|
+
|
|
+ .hash : { *(.hash*) }
|
|
+
|
|
+ .end :
|
|
+ {
|
|
+ *(.__end)
|
|
+ }
|
|
+
|
|
+ _image_binary_end = .;
|
|
+
|
|
+ /*
|
|
+ * Deprecated: this MMU section is used by pxa at present but
|
|
+ * should not be used by new boards/CPUs.
|
|
+ */
|
|
+ . = ALIGN(4096);
|
|
+ .mmutable : {
|
|
+ *(.mmutable)
|
|
+ }
|
|
+
|
|
+/*
|
|
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
|
|
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
|
|
+ */
|
|
+
|
|
+ .bss_start __rel_dyn_start (OVERLAY) : {
|
|
+ KEEP(*(.__bss_start));
|
|
+ __bss_base = .;
|
|
+ }
|
|
+
|
|
+ .bss __bss_base (OVERLAY) : {
|
|
+ *(.bss*)
|
|
+ . = ALIGN(4);
|
|
+ __bss_limit = .;
|
|
+ }
|
|
+
|
|
+ .bss_end __bss_limit (OVERLAY) : {
|
|
+ KEEP(*(.__bss_end));
|
|
+ }
|
|
+
|
|
+ .dynsym _image_binary_end : { *(.dynsym) }
|
|
+ .dynbss : { *(.dynbss) }
|
|
+ .dynstr : { *(.dynstr*) }
|
|
+ .dynamic : { *(.dynamic*) }
|
|
+ .gnu.hash : { *(.gnu.hash) }
|
|
+ .plt : { *(.plt*) }
|
|
+ .interp : { *(.interp*) }
|
|
+ .gnu : { *(.gnu*) }
|
|
+ .ARM.exidx : { *(.ARM.exidx*) }
|
|
+}
|
|
diff --git a/boards.cfg b/boards.cfg
|
|
index 1ba2081..b432704 100644
|
|
--- a/boards.cfg
|
|
+++ b/boards.cfg
|
|
@@ -258,6 +258,11 @@ Active arm armv7 am33xx BuR tseries
|
|
Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
|
|
Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
|
|
Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
|
|
+Active arm armv7 am33xx grinn chiliboard chiliboard_ram128m chiliboard:CHILISOM_GCS2,NAND,RAM128MB Grzegorz Glomb <g.glomb@grinn-global.com>
|
|
+Active arm armv7 am33xx grinn chiliboard chiliboard_nand0m_ram128m chiliboard:CHILISOM_GCS2,RAM128MB Grzegorz Glomb <g.glomb@grinn-global.com>
|
|
+Active arm armv7 am33xx grinn chiliboard chiliboard_nand512m chiliboard:CHILISOM_GCS2,NAND,NAND512MB Grzegorz Glomb <g.glomb@grinn-global.com>
|
|
+Active arm armv7 am33xx grinn chiliboard chiliboard_nand0m chiliboard:CHILISOM_GCS2 Grzegorz Glomb <g.glomb@grinn-global.com>
|
|
+Active arm armv7 am33xx grinn chiliboard chiliboard chiliboard:CHILISOM_GCS2,NAND Grzegorz Glomb <g.glomb@grinn-global.com>
|
|
Active arm armv7 am33xx gumstix pepper pepper - Ash Charles <ash@gumstix.com>
|
|
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
|
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
|
|
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
|
|
index 1acf06b..0c9cde3 100644
|
|
--- a/drivers/mtd/nand/omap_gpmc.c
|
|
+++ b/drivers/mtd/nand/omap_gpmc.c
|
|
@@ -478,11 +478,13 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
|
|
oob += eccbytes) {
|
|
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
|
/* read data */
|
|
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
|
|
+ /* chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page); */
|
|
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
|
|
chip->read_buf(mtd, p, eccsize);
|
|
|
|
/* read respective ecc from oob area */
|
|
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
|
|
+ /* chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page); */
|
|
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
|
|
chip->read_buf(mtd, oob, eccbytes);
|
|
/* read syndrome */
|
|
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
|
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
|
|
new file mode 100644
|
|
index 0000000..eacc9af
|
|
--- /dev/null
|
|
+++ b/include/configs/chiliboard.h
|
|
@@ -0,0 +1,878 @@
|
|
+/*
|
|
+ * chiliboard.h
|
|
+ *
|
|
+ * Grinn chiliboard configuration header
|
|
+ *
|
|
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
|
+ *
|
|
+ * Copyright (C) 2015, Grinn - http://www.grinn-global.com
|
|
+ * Grzegorz Glomb, g.glomb@grinn-global.com
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#ifndef __CONFIG_CHILIBOARD_H
|
|
+#define __CONFIG_CHILIBOARD_H
|
|
+
|
|
+#define CONFIG_AM33XX
|
|
+#define CONFIG_ARCH_CPU_INIT
|
|
+#define CONFIG_SYS_CACHELINE_SIZE 64
|
|
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
|
|
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
|
|
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
|
|
+
|
|
+#include <asm/arch/omap.h>
|
|
+
|
|
+/* NS16550 Configuration */
|
|
+#define CONFIG_SYS_NS16550
|
|
+#define CONFIG_SYS_NS16550_SERIAL
|
|
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
|
+#define CONFIG_SYS_NS16550_CLK 48000000
|
|
+
|
|
+/* Network defines. */
|
|
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
|
|
+#define CONFIG_CMD_DHCP
|
|
+#define CONFIG_CMD_MII
|
|
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
|
|
+#define CONFIG_BOOTP_DNS2
|
|
+#define CONFIG_BOOTP_SEND_HOSTNAME
|
|
+#define CONFIG_BOOTP_GATEWAY
|
|
+#define CONFIG_BOOTP_SUBNETMASK
|
|
+#define CONFIG_NET_RETRY_COUNT 10
|
|
+#define CONFIG_CMD_PING
|
|
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
|
|
+#define CONFIG_MII /* Required in net/eth.c */
|
|
+
|
|
+/*
|
|
+ * RTC related defines. To use bootcount you must set bootlimit in the
|
|
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
|
|
+ * in the board config.
|
|
+ */
|
|
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
|
|
+
|
|
+/* Enable the HW watchdog, since we can use this with bootcount */
|
|
+#define CONFIG_HW_WATCHDOG
|
|
+#define CONFIG_OMAP_WATCHDOG
|
|
+
|
|
+/*
|
|
+ * SPL related defines. The Public RAM memory map the ROM defines the
|
|
+ * area between 0x402F0400 and 0x4030B800 as a download area and
|
|
+ * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
|
|
+ * supports X-MODEM loading via UART, and we leverage this and then use
|
|
+ * Y-MODEM to load u-boot.img, when booted over UART.
|
|
+ */
|
|
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
|
+#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
|
|
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
|
|
+ (128 << 20))
|
|
+
|
|
+/* Enable the watchdog inside of SPL */
|
|
+#define CONFIG_SPL_WATCHDOG_SUPPORT
|
|
+
|
|
+/*
|
|
+ * Since SPL did pll and ddr initialization for us,
|
|
+ * we don't need to do it twice.
|
|
+ */
|
|
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
|
|
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * When building U-Boot such that there is no previous loader
|
|
+ * we need to call board_early_init_f. This is taken care of in
|
|
+ * s_init when we have SPL used.
|
|
+ */
|
|
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
|
|
+#define CONFIG_BOARD_EARLY_INIT_F
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
|
|
+#endif
|
|
+
|
|
+/* Common define for many platforms. */
|
|
+#define CONFIG_OMAP
|
|
+#define CONFIG_OMAP_COMMON
|
|
+#define CONFIG_SYS_GENERIC_BOARD
|
|
+
|
|
+/*
|
|
+ * We typically do not contain NOR flash. In the cases where we do, we
|
|
+ * undefine this later.
|
|
+ */
|
|
+#define CONFIG_SYS_NO_FLASH
|
|
+
|
|
+/* Support both device trees and ATAGs. */
|
|
+#define CONFIG_OF_LIBFDT
|
|
+#define CONFIG_CMDLINE_TAG
|
|
+#define CONFIG_SETUP_MEMORY_TAGS
|
|
+#define CONFIG_INITRD_TAG
|
|
+
|
|
+/*
|
|
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
|
|
+ * relocated itself to higher in memory by the time this value is used.
|
|
+ * However, set this to a 32MB offset to allow for easier Linux kernel
|
|
+ * booting as the default is often used as the kernel load address.
|
|
+ */
|
|
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
|
|
+
|
|
+/*
|
|
+ * We setup defaults based on constraints from the Linux kernel, which should
|
|
+ * also be safe elsewhere. We have the default load at 32MB into DDR (for
|
|
+ * the kernel), FDT above 128MB (the maximum location for the end of the
|
|
+ * kernel), and the ramdisk 512KB above that (allowing for hopefully never
|
|
+ * seen large trees). We say all of this must be within the first 256MB
|
|
+ * as that will normally be within the kernel lowmem and thus visible via
|
|
+ * bootm_size and we only run on platforms with 256MB or more of memory.
|
|
+ */
|
|
+#ifdef CONFIG_RAM128MB
|
|
+#define DEFAULT_LINUX_BOOT_ENV \
|
|
+ "loadaddr=0x82000000\0" \
|
|
+ "kernel_addr_r=0x82000000\0" \
|
|
+ "fdtaddr=0x84000000\0" \
|
|
+ "fdt_addr_r=0x84000000\0" \
|
|
+ "rdaddr=0x84080000\0" \
|
|
+ "ramdisk_addr_r=0x84080000\0" \
|
|
+ "bootm_size=0x8000000\0"
|
|
+#else
|
|
+#define DEFAULT_LINUX_BOOT_ENV \
|
|
+ "loadaddr=0x82000000\0" \
|
|
+ "kernel_addr_r=0x82000000\0" \
|
|
+ "fdtaddr=0x88000000\0" \
|
|
+ "fdt_addr_r=0x88000000\0" \
|
|
+ "rdaddr=0x88080000\0" \
|
|
+ "ramdisk_addr_r=0x88080000\0" \
|
|
+ "bootm_size=0x10000000\0"
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * Default to a quick boot delay.
|
|
+ */
|
|
+#define CONFIG_BOOTDELAY 1
|
|
+
|
|
+/*
|
|
+ * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
|
|
+ * we say (for simplicity) that we have 1 bank, always, even when
|
|
+ * we have more. We always start at 0x80000000, and we place the
|
|
+ * initial stack pointer in our SRAM. Otherwise, we can define
|
|
+ * CONFIG_NR_DRAM_BANKS before including this file.
|
|
+ */
|
|
+#ifndef CONFIG_NR_DRAM_BANKS
|
|
+#define CONFIG_NR_DRAM_BANKS 1
|
|
+#endif
|
|
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
|
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
|
|
+ GENERATED_GBL_DATA_SIZE)
|
|
+
|
|
+/* Timer information. */
|
|
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
|
+
|
|
+/* I2C IP block */
|
|
+#define CONFIG_I2C
|
|
+#define CONFIG_CMD_I2C
|
|
+#define CONFIG_SYS_I2C
|
|
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
|
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
|
+#define CONFIG_SYS_I2C_OMAP24XX
|
|
+
|
|
+/* MMC/SD IP block */
|
|
+#define CONFIG_MMC
|
|
+#define CONFIG_GENERIC_MMC
|
|
+#define CONFIG_OMAP_HSMMC
|
|
+#define CONFIG_CMD_MMC
|
|
+
|
|
+/* McSPI IP block */
|
|
+#define CONFIG_SPI
|
|
+#define CONFIG_OMAP3_SPI
|
|
+#define CONFIG_CMD_SPI
|
|
+
|
|
+/* GPIO block */
|
|
+#define CONFIG_OMAP_GPIO
|
|
+#define CONFIG_CMD_GPIO
|
|
+
|
|
+/*
|
|
+ * GPMC NAND block. We support 1 device and the physical address to
|
|
+ * access CS0 at is 0x8000000.
|
|
+ */
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_NAND_OMAP_GPMC
|
|
+#ifndef CONFIG_SYS_NAND_BASE
|
|
+#define CONFIG_SYS_NAND_BASE 0x8000000
|
|
+#endif
|
|
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
+#define CONFIG_CMD_NAND
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * The following are general good-enough settings for U-Boot. We set a
|
|
+ * large malloc pool as we generally have a lot of DDR, and we opt for
|
|
+ * function over binary size in the main portion of U-Boot as this is
|
|
+ * generally easily constrained later if needed. We enable the config
|
|
+ * options that give us information in the environment about what board
|
|
+ * we are on so we do not need to rely on the command prompt. We set a
|
|
+ * console baudrate of 115200 and use the default baud rate table.
|
|
+ */
|
|
+#define CONFIG_SYS_MALLOC_LEN (16 << 20)
|
|
+#define CONFIG_SYS_HUSH_PARSER
|
|
+#define CONFIG_SYS_PROMPT "U-Boot# "
|
|
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
|
+#define CONFIG_BAUDRATE 115200
|
|
+#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */
|
|
+#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
|
|
+
|
|
+/* As stated above, the following choices are optional. */
|
|
+#define CONFIG_SYS_LONGHELP
|
|
+#define CONFIG_AUTO_COMPLETE
|
|
+#define CONFIG_CMDLINE_EDITING
|
|
+#define CONFIG_VERSION_VARIABLE
|
|
+
|
|
+/* We set the max number of command args high to avoid HUSH bugs. */
|
|
+#define CONFIG_SYS_MAXARGS 64
|
|
+
|
|
+/* Console I/O Buffer Size */
|
|
+#define CONFIG_SYS_CBSIZE 512
|
|
+/* Print Buffer Size */
|
|
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
|
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
+/* Boot Argument Buffer Size */
|
|
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
+
|
|
+/*
|
|
+ * When we have SPI, NOR or NAND flash we expect to be making use of
|
|
+ * mtdparts, both for ease of use in U-Boot and for passing information
|
|
+ * on to the Linux kernel.
|
|
+ */
|
|
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND)
|
|
+#define CONFIG_MTD_DEVICE /* Required for mtdparts */
|
|
+#define CONFIG_CMD_MTDPARTS
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * For commands to use, we take the default list and add a few other
|
|
+ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
|
|
+ * prior to this include, in order to skip a few commands. When we do
|
|
+ * have flash, if we expect these commands they must be enabled in that
|
|
+ * config. If desired, a specific list of desired commands can be used
|
|
+ * instead.
|
|
+ */
|
|
+#include <config_cmd_default.h>
|
|
+#define CONFIG_CMD_ASKENV
|
|
+#define CONFIG_CMD_ECHO
|
|
+#define CONFIG_CMD_BOOTZ
|
|
+
|
|
+/*
|
|
+ * Common filesystems support. When we have removable storage we
|
|
+ * enabled a number of useful commands and support.
|
|
+ */
|
|
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
|
|
+#define CONFIG_DOS_PARTITION
|
|
+#define CONFIG_CMD_FAT
|
|
+#define CONFIG_FAT_WRITE
|
|
+#define CONFIG_CMD_EXT2
|
|
+#define CONFIG_CMD_EXT4
|
|
+#define CONFIG_CMD_FS_GENERIC
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * Our platforms make use of SPL to initalize the hardware (primarily
|
|
+ * memory) enough for full U-Boot to be loaded. We also support Falcon
|
|
+ * Mode so that the Linux kernel can be booted directly from SPL
|
|
+ * instead, if desired. We make use of the general SPL framework found
|
|
+ * under common/spl/. Given our generally common memory map, we set a
|
|
+ * number of related defaults and sizes here.
|
|
+ */
|
|
+#if !defined(CONFIG_NOR_BOOT) && \
|
|
+ !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
|
|
+#define CONFIG_SPL
|
|
+#define CONFIG_SPL_FRAMEWORK
|
|
+#define CONFIG_SPL_OS_BOOT
|
|
+
|
|
+/*
|
|
+ * Place the image at the start of the ROM defined image space.
|
|
+ * We limit our size to the ROM-defined downloaded image area, and use the
|
|
+ * rest of the space for stack. We load U-Boot itself into memory at
|
|
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
|
|
+ * have our BSS be placed 1MiB after this, to allow for the default
|
|
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
|
|
+ * We have the SPL malloc pool at the end of the BSS area.
|
|
+ */
|
|
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
|
+#ifndef CONFIG_SYS_TEXT_BASE
|
|
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
|
+#endif
|
|
+#ifndef CONFIG_SPL_BSS_START_ADDR
|
|
+#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
|
|
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
|
+#endif
|
|
+#ifndef CONFIG_SYS_SPL_MALLOC_START
|
|
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
|
+ CONFIG_SPL_BSS_MAX_SIZE)
|
|
+#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
|
|
+#endif
|
|
+
|
|
+/* RAW SD card / eMMC locations. */
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
|
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
|
+
|
|
+/* FAT sd card locations. */
|
|
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
|
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
|
+
|
|
+#ifdef CONFIG_SPL_OS_BOOT
|
|
+/* FAT */
|
|
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
|
|
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
|
|
+
|
|
+/* RAW SD card / eMMC */
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
|
|
+
|
|
+/* NAND */
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
|
|
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
|
|
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
|
|
+#endif
|
|
+
|
|
+/* spl export command */
|
|
+#define CONFIG_CMD_SPL
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_MMC
|
|
+#define CONFIG_SPL_LIBDISK_SUPPORT
|
|
+#define CONFIG_SPL_MMC_SUPPORT
|
|
+#define CONFIG_SPL_FAT_SUPPORT
|
|
+#endif
|
|
+
|
|
+/* General parts of the framework, required. */
|
|
+#define CONFIG_SPL_I2C_SUPPORT
|
|
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
|
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
|
+#define CONFIG_SPL_SERIAL_SUPPORT
|
|
+#define CONFIG_SPL_GPIO_SUPPORT
|
|
+#define CONFIG_SPL_BOARD_INIT
|
|
+
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_SPL_NAND_SUPPORT
|
|
+#define CONFIG_SPL_NAND_BASE
|
|
+#define CONFIG_SPL_NAND_DRIVERS
|
|
+#define CONFIG_SPL_NAND_ECC
|
|
+#define CONFIG_SPL_MTD_SUPPORT
|
|
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
|
+/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */ /* Defined later in this configuration */
|
|
+#endif
|
|
+#endif /* !CONFIG_NOR_BOOT */
|
|
+
|
|
+#ifndef CONFIG_SPL_BUILD
|
|
+# define CONFIG_FIT
|
|
+# define CONFIG_TIMESTAMP
|
|
+# define CONFIG_LZO
|
|
+# ifdef CONFIG_ENABLE_VBOOT
|
|
+# define CONFIG_OF_CONTROL
|
|
+# define CONFIG_OF_SEPARATE
|
|
+# define CONFIG_DEFAULT_DEVICE_TREE am335x-chiliboard
|
|
+# define CONFIG_FIT_SIGNATURE
|
|
+# define CONFIG_RSA
|
|
+# endif
|
|
+#endif
|
|
+
|
|
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
|
|
+
|
|
+#define CONFIG_BOARD_LATE_INIT
|
|
+
|
|
+#define CONFIG_SERIAL1 1
|
|
+#define CONFIG_CONS_INDEX 1
|
|
+
|
|
+/* Clock Defines */
|
|
+#define V_OSCK 24000000 /* Clock output from T2 */
|
|
+#define V_SCLK (V_OSCK)
|
|
+
|
|
+/* Custom script for NOR */
|
|
+#define CONFIG_SYS_LDSCRIPT "board/grinn/chiliboard/u-boot.lds"
|
|
+
|
|
+/* Always 128 KiB env size */
|
|
+#define CONFIG_ENV_SIZE (128 << 10)
|
|
+
|
|
+/* Enhance our eMMC support / experience. */
|
|
+#define CONFIG_CMD_GPT
|
|
+#define CONFIG_EFI_PARTITION
|
|
+#define CONFIG_PARTITION_UUIDS
|
|
+#define CONFIG_CMD_PART
|
|
+
|
|
+#ifdef CONFIG_NAND
|
|
+#ifndef CONFIG_NAND512MB
|
|
+#define NANDARGS \
|
|
+ "mtdids=" MTDIDS_DEFAULT "\0" \
|
|
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
|
|
+ "nandargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=${nandroot} " \
|
|
+ "rootfstype=${nandrootfstype}\0" \
|
|
+ "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
|
|
+ "nandrootfstype=ubifs rootwait=1\0" \
|
|
+ "nandboot=echo Booting from nand ...; " \
|
|
+ "run nandargs; " \
|
|
+ "nand read ${fdtaddr} u-boot-spl-os; " \
|
|
+ "nand read ${loadaddr} kernel; " \
|
|
+ "bootz ${loadaddr} - ${fdtaddr}\0"
|
|
+#else
|
|
+#define NANDARGS \
|
|
+ "mtdids=" MTDIDS_DEFAULT "\0" \
|
|
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
|
|
+ "nandargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=${nandroot} " \
|
|
+ "rootfstype=${nandrootfstype}\0" \
|
|
+ "nandroot=ubi0:rootfs rw ubi.mtd=8,4096\0" \
|
|
+ "nandrootfstype=ubifs rootwait=1\0" \
|
|
+ "nandboot=echo Booting from nand ...; " \
|
|
+ "run nandargs; " \
|
|
+ "nand read ${fdtaddr} u-boot-spl-os; " \
|
|
+ "nand read ${loadaddr} kernel; " \
|
|
+ "bootz ${loadaddr} - ${fdtaddr}\0"
|
|
+#endif
|
|
+#else
|
|
+#define NANDARGS ""
|
|
+#endif
|
|
+
|
|
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
+
|
|
+#ifndef CONFIG_SPL_BUILD
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
+ DEFAULT_LINUX_BOOT_ENV \
|
|
+ "boot_fdt=try\0" \
|
|
+ "bootpart=0:2\0" \
|
|
+ "bootdir=/boot\0" \
|
|
+ "bootfile=zImage\0" \
|
|
+ "fdtfile=undefined\0" \
|
|
+ "console=ttyO0,115200n8\0" \
|
|
+ "partitions=" \
|
|
+ "uuid_disk=${uuid_gpt_disk};" \
|
|
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
|
|
+ "optargs=\0" \
|
|
+ "mmcdev=0\0" \
|
|
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
|
|
+ "mmcrootfstype=ext4 rootwait\0" \
|
|
+ "rootpath=/export/rootfs\0" \
|
|
+ "nfsopts=nolock\0" \
|
|
+ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
|
|
+ "::off\0" \
|
|
+ "ramroot=/dev/ram0 rw\0" \
|
|
+ "ramrootfstype=ext2\0" \
|
|
+ "mmcargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=${mmcroot} " \
|
|
+ "rootfstype=${mmcrootfstype}\0" \
|
|
+ "spiroot=/dev/mtdblock4 rw\0" \
|
|
+ "spirootfstype=jffs2\0" \
|
|
+ "spisrcaddr=0xe0000\0" \
|
|
+ "spiimgsize=0x362000\0" \
|
|
+ "spibusno=0\0" \
|
|
+ "spiargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=${spiroot} " \
|
|
+ "rootfstype=${spirootfstype}\0" \
|
|
+ "netargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=/dev/nfs " \
|
|
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
|
+ "ip=dhcp\0" \
|
|
+ "bootenv=uEnv.txt\0" \
|
|
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
|
+ "importbootenv=echo Importing environment from mmc ...; " \
|
|
+ "env import -t $loadaddr $filesize\0" \
|
|
+ "ramargs=setenv bootargs console=${console} " \
|
|
+ "${optargs} " \
|
|
+ "root=${ramroot} " \
|
|
+ "rootfstype=${ramrootfstype}\0" \
|
|
+ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
|
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
|
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
|
+ "mmcloados=run mmcargs; " \
|
|
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
|
+ "if run loadfdt; then " \
|
|
+ "bootz ${loadaddr} - ${fdtaddr}; " \
|
|
+ "else " \
|
|
+ "if test ${boot_fdt} = try; then " \
|
|
+ "bootz; " \
|
|
+ "else " \
|
|
+ "echo WARN: Cannot load the DT; " \
|
|
+ "fi; " \
|
|
+ "fi; " \
|
|
+ "else " \
|
|
+ "bootz; " \
|
|
+ "fi;\0" \
|
|
+ "mmcboot=mmc dev ${mmcdev}; " \
|
|
+ "if mmc rescan; then " \
|
|
+ "echo SD/MMC found on device ${mmcdev};" \
|
|
+ "if run loadbootenv; then " \
|
|
+ "echo Loaded environment from ${bootenv};" \
|
|
+ "run importbootenv;" \
|
|
+ "fi;" \
|
|
+ "if test -n $uenvcmd; then " \
|
|
+ "echo Running uenvcmd ...;" \
|
|
+ "run uenvcmd;" \
|
|
+ "fi;" \
|
|
+ "if run loadimage; then " \
|
|
+ "run mmcloados;" \
|
|
+ "fi;" \
|
|
+ "fi;\0" \
|
|
+ "spiboot=echo Booting from spi ...; " \
|
|
+ "run spiargs; " \
|
|
+ "sf probe ${spibusno}:0; " \
|
|
+ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
|
|
+ "bootz ${loadaddr}\0" \
|
|
+ "netboot=echo Booting from network ...; " \
|
|
+ "setenv autoload no; " \
|
|
+ "dhcp; " \
|
|
+ "tftp ${loadaddr} ${bootfile}; " \
|
|
+ "tftp ${fdtaddr} ${fdtfile}; " \
|
|
+ "run netargs; " \
|
|
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
|
|
+ "ramboot=echo Booting from ramdisk ...; " \
|
|
+ "run ramargs; " \
|
|
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
|
|
+ "findfdt="\
|
|
+ "setenv fdtfile am335x-chiliboard.dtb;\0" \
|
|
+ NANDARGS \
|
|
+ DFUARGS
|
|
+#endif
|
|
+
|
|
+#define CONFIG_BOOTCOMMAND \
|
|
+ "run findfdt; " \
|
|
+ "run mmcboot;" \
|
|
+ "setenv mmcdev 1; " \
|
|
+ "setenv bootpart 1:2; " \
|
|
+ "run mmcboot;" \
|
|
+ "run nandboot;"
|
|
+
|
|
+/* NS16550 Configuration */
|
|
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
|
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
|
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
|
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
|
|
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
|
|
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
|
+#define CONFIG_BAUDRATE 115200
|
|
+
|
|
+/*
|
|
+#define CONFIG_CMD_EEPROM
|
|
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
|
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
|
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
|
+*/
|
|
+
|
|
+/* PMIC support */
|
|
+#define CONFIG_POWER_TPS65217
|
|
+/* #define CONFIG_POWER_TPS65910 */
|
|
+
|
|
+/* SPL */
|
|
+#ifndef CONFIG_NOR_BOOT
|
|
+#define CONFIG_SPL_POWER_SUPPORT
|
|
+#define CONFIG_SPL_YMODEM_SUPPORT
|
|
+
|
|
+/* Bootcount using the RTC block */
|
|
+#define CONFIG_BOOTCOUNT_LIMIT
|
|
+#define CONFIG_BOOTCOUNT_AM33XX
|
|
+
|
|
+/* USB gadget RNDIS */
|
|
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
|
|
+
|
|
+/* General network SPL, both CPSW and USB gadget RNDIS */
|
|
+#define CONFIG_SPL_NET_SUPPORT
|
|
+#define CONFIG_SPL_ENV_SUPPORT
|
|
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
|
|
+
|
|
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
|
+
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_NAND_OMAP_GPMC
|
|
+#define CONFIG_NAND_OMAP_ELM
|
|
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
|
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
|
+ CONFIG_SYS_NAND_PAGE_SIZE)
|
|
+
|
|
+#ifndef CONFIG_NAND512MB
|
|
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
|
+#define CONFIG_SYS_NAND_OOBSIZE 64
|
|
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
|
|
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
|
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
|
+ 10, 11, 12, 13, 14, 15, 16, 17, \
|
|
+ 18, 19, 20, 21, 22, 23, 24, 25, \
|
|
+ 26, 27, 28, 29, 30, 31, 32, 33, \
|
|
+ 34, 35, 36, 37, 38, 39, 40, 41, \
|
|
+ 42, 43, 44, 45, 46, 47, 48, 49, \
|
|
+ 50, 51, 52, 53, 54, 55, 56, 57, }
|
|
+
|
|
+#define CONFIG_SYS_NAND_ECCSIZE 512
|
|
+#define CONFIG_SYS_NAND_ECCBYTES 14
|
|
+#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
|
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
|
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
|
+#else
|
|
+#define CONFIG_SYS_NAND_PAGE_SIZE 4096
|
|
+#define CONFIG_SYS_NAND_OOBSIZE 224
|
|
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
|
|
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
|
+#define CONFIG_SYS_NAND_ECCPOS {\
|
|
+ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
|
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
|
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
|
|
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
|
|
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
|
|
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
|
|
+ 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
|
|
+ 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
|
|
+ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,\
|
|
+ 110, 111, 112, 113, 114, 115, 116, 117, 118, 119,\
|
|
+ 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\
|
|
+ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\
|
|
+ 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\
|
|
+ 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,\
|
|
+ 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,\
|
|
+ 170, 171, 172, 173, 174, 175, 176, 177, 178, 179,\
|
|
+ 180, 181, 182, 183, 184, 185, 186, 187, 188, 189,\
|
|
+ 190, 191, 192, 193, 194, 195, 196, 197, 198, 199,\
|
|
+ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
|
|
+
|
|
+#define CONFIG_SYS_NAND_ECCSIZE 512
|
|
+#define CONFIG_SYS_NAND_ECCBYTES 26
|
|
+#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
|
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
|
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
|
|
+#endif
|
|
+
|
|
+#endif
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * For NOR boot, we must set this to the start of where NOR is mapped
|
|
+ * in memory.
|
|
+ */
|
|
+#ifdef CONFIG_NOR_BOOT
|
|
+#define CONFIG_SYS_TEXT_BASE 0x08000000
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * USB configuration. We enable MUSB support, both for host and for
|
|
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
|
|
+ * board schematic and physical port wired to each. Then for host we
|
|
+ * add mass storage support and for gadget we add both RNDIS ethernet
|
|
+ * and DFU.
|
|
+ */
|
|
+#define CONFIG_USB_MUSB_DSPS
|
|
+#define CONFIG_ARCH_MISC_INIT
|
|
+#define CONFIG_MUSB_GADGET
|
|
+#define CONFIG_MUSB_PIO_ONLY
|
|
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
|
|
+#define CONFIG_USB_GADGET
|
|
+#define CONFIG_USBDOWNLOAD_GADGET
|
|
+#define CONFIG_USB_GADGET_DUALSPEED
|
|
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
|
+#define CONFIG_MUSB_HOST
|
|
+#define CONFIG_AM335X_USB0
|
|
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
|
+#define CONFIG_AM335X_USB1
|
|
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
|
+
|
|
+#ifdef CONFIG_MUSB_HOST
|
|
+#define CONFIG_CMD_USB
|
|
+#define CONFIG_USB_STORAGE
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_MUSB_GADGET
|
|
+#define CONFIG_USB_ETHER
|
|
+#define CONFIG_USB_ETH_RNDIS
|
|
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
|
|
+
|
|
+/* USB TI's IDs */
|
|
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
|
|
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
|
|
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
|
|
+#endif /* CONFIG_MUSB_GADGET */
|
|
+
|
|
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
|
|
+/* disable host part of MUSB in SPL */
|
|
+#undef CONFIG_MUSB_HOST
|
|
+/* disable EFI partitions and partition UUID support */
|
|
+#undef CONFIG_PARTITION_UUIDS
|
|
+#undef CONFIG_EFI_PARTITION
|
|
+/*
|
|
+ * Disable CPSW SPL support so we fit within the 101KiB limit.
|
|
+ */
|
|
+#undef CONFIG_SPL_ETH_SUPPORT
|
|
+#endif
|
|
+
|
|
+/* USB Device Firmware Update support */
|
|
+#ifndef CONFIG_SPL_BUILD
|
|
+#define CONFIG_DFU_FUNCTION
|
|
+#define CONFIG_DFU_MMC
|
|
+#define CONFIG_CMD_DFU
|
|
+#define DFU_ALT_INFO_MMC \
|
|
+ "dfu_alt_info_mmc=" \
|
|
+ "boot part 0 1;" \
|
|
+ "rootfs part 0 2;" \
|
|
+ "MLO fat 0 1;" \
|
|
+ "MLO.raw mmc 0x100 0x100;" \
|
|
+ "u-boot.img.raw mmc 0x300 0x400;" \
|
|
+ "spl-os-args.raw mmc 0x80 0x80;" \
|
|
+ "spl-os-image.raw mmc 0x900 0x2000;" \
|
|
+ "spl-os-args fat 0 1;" \
|
|
+ "spl-os-image fat 0 1;" \
|
|
+ "u-boot.img fat 0 1;" \
|
|
+ "uEnv.txt fat 0 1\0"
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_DFU_NAND
|
|
+#define DFU_ALT_INFO_NAND \
|
|
+ "dfu_alt_info_nand=" \
|
|
+ "SPL part 0 1;" \
|
|
+ "SPL.backup1 part 0 2;" \
|
|
+ "SPL.backup2 part 0 3;" \
|
|
+ "SPL.backup3 part 0 4;" \
|
|
+ "u-boot part 0 5;" \
|
|
+ "u-boot-spl-os part 0 6;" \
|
|
+ "kernel part 0 8;" \
|
|
+ "rootfs part 0 9\0"
|
|
+#else
|
|
+#define DFU_ALT_INFO_NAND ""
|
|
+#endif
|
|
+#define CONFIG_DFU_RAM
|
|
+#define DFU_ALT_INFO_RAM \
|
|
+ "dfu_alt_info_ram=" \
|
|
+ "kernel ram 0x80200000 0xD80000;" \
|
|
+ "fdt ram 0x80F80000 0x80000;" \
|
|
+ "ramdisk ram 0x81000000 0x4000000\0"
|
|
+#define DFUARGS \
|
|
+ "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
|
|
+ DFU_ALT_INFO_MMC \
|
|
+ DFU_ALT_INFO_RAM \
|
|
+ DFU_ALT_INFO_NAND
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * Default to using SPI for environment, etc.
|
|
+ * 0x000000 - 0x020000 : SPL (128KiB)
|
|
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
|
|
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
|
|
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
|
|
+ * 0x0E0000 - 0x442000 : Linux Kernel
|
|
+ * 0x442000 - 0x800000 : Userland
|
|
+ */
|
|
+#if defined(CONFIG_SPI_BOOT)
|
|
+/* SPL related */
|
|
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
|
|
+#define CONFIG_SPL_SPI_SUPPORT
|
|
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
|
+#define CONFIG_SPL_SPI_LOAD
|
|
+#define CONFIG_SPL_SPI_BUS 0
|
|
+#define CONFIG_SPL_SPI_CS 0
|
|
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
|
+
|
|
+#define CONFIG_ENV_IS_IN_SPI_FLASH
|
|
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
|
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
|
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
|
|
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
|
|
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
|
|
+#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
|
|
+#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
|
|
+ "512k(u-boot),128k(u-boot-env1)," \
|
|
+ "128k(u-boot-env2),3464k(kernel)," \
|
|
+ "-(rootfs)"
|
|
+#elif defined(CONFIG_EMMC_BOOT)
|
|
+#undef CONFIG_ENV_IS_NOWHERE
|
|
+#define CONFIG_ENV_IS_IN_MMC
|
|
+#define CONFIG_SYS_MMC_ENV_DEV 1
|
|
+#define CONFIG_SYS_MMC_ENV_PART 2
|
|
+#define CONFIG_ENV_OFFSET 0x0
|
|
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
|
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
|
+#endif
|
|
+
|
|
+/* SPI flash. */
|
|
+#define CONFIG_CMD_SF
|
|
+#define CONFIG_SPI_FLASH
|
|
+#define CONFIG_SPI_FLASH_WINBOND
|
|
+#define CONFIG_SF_DEFAULT_SPEED 24000000
|
|
+
|
|
+/* Network. */
|
|
+#define CONFIG_PHY_GIGE
|
|
+#define CONFIG_PHYLIB
|
|
+#define CONFIG_PHY_SMSC
|
|
+
|
|
+/* NAND support */
|
|
+#ifdef CONFIG_NAND
|
|
+#define CONFIG_CMD_NAND
|
|
+#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
|
|
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
|
|
+
|
|
+#ifndef CONFIG_NAND512MB
|
|
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
|
|
+ "128k(SPL.backup1)," \
|
|
+ "128k(SPL.backup2)," \
|
|
+ "128k(SPL.backup3),1792k(u-boot)," \
|
|
+ "128k(u-boot-spl-os)," \
|
|
+ "128k(u-boot-env),5m(kernel),-(rootfs)"
|
|
+#define CONFIG_ENV_IS_IN_NAND
|
|
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
|
|
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
|
+#else
|
|
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:256k(SPL)," \
|
|
+ "256k(SPL.backup1)," \
|
|
+ "256k(SPL.backup2)," \
|
|
+ "256k(SPL.backup3),2048k(u-boot)," \
|
|
+ "256k(u-boot-spl-os)," \
|
|
+ "256k(u-boot-env),5m(kernel),-(rootfs)"
|
|
+#define CONFIG_ENV_IS_IN_NAND
|
|
+#define CONFIG_ENV_OFFSET 0x340000 /* environment starts here */
|
|
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
|
+#endif
|
|
+
|
|
+#endif
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * NOR Size = 16 MiB
|
|
+ * Number of Sectors/Blocks = 128
|
|
+ * Sector Size = 128 KiB
|
|
+ * Word length = 16 bits
|
|
+ * Default layout:
|
|
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
|
|
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
|
|
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
|
|
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
|
|
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
|
|
+ */
|
|
+#if defined(CONFIG_NOR)
|
|
+#undef CONFIG_SYS_NO_FLASH
|
|
+#define CONFIG_CMD_FLASH
|
|
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
|
+#define CONFIG_SYS_FLASH_PROTECTION
|
|
+#define CONFIG_SYS_FLASH_CFI
|
|
+#define CONFIG_FLASH_CFI_DRIVER
|
|
+#define CONFIG_FLASH_CFI_MTD
|
|
+#define CONFIG_SYS_MAX_FLASH_SECT 128
|
|
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
|
|
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
|
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
+/* Reduce SPL size by removing unlikey targets */
|
|
+#ifdef CONFIG_NOR_BOOT
|
|
+#define CONFIG_ENV_IS_IN_FLASH
|
|
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
|
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
|
|
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
|
|
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
|
|
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
|
|
+ "512k(u-boot)," \
|
|
+ "128k(u-boot-env1)," \
|
|
+ "128k(u-boot-env2)," \
|
|
+ "4m(kernel),-(rootfs)"
|
|
+#endif
|
|
+#endif /* NOR support */
|
|
+
|
|
+#endif /* ! __CONFIG_CHILISOM_H */
|
|
--
|
|
2.5.0
|
|
|