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PKGBUILDs/core/linux-wandboard/0001-Swap-usdhc1-and-usdhc3.patch
Kevin Mihelich 3697ded1c0 core/linux-wandboard to 3.10.17-5
2015-01-03 06:54:19 +00:00

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From 9e1f894719f38a4222cd1713b4f5d1f36c9cd9c2 Mon Sep 17 00:00:00 2001
From: Kevin Mihelich <kevin@archlinuxarm.org>
Date: Mon, 12 May 2014 13:56:09 -0600
Subject: [PATCH] Swap usdhc1 and usdhc3
U-Boot recognizes the module SD slot as mmc0 and the base board slot as mmc1,
so carry this forward into the kernel so that when both slots are occupied mmc1
from U-Boot does not become mmc0.
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
---
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 15 +++--
arch/arm/boot/dts/imx6qdl.dtsi | 104 +++++++++++++++----------------
2 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 5244e95..518cefe 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -480,12 +480,11 @@ reference manual.
status = "okay";
};
-&usdhc1 { /* Baseboard microSD slot */
+&usdhc1 { /* Module microSD slot */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_1>;
- bus-width = <4>;
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
vmmc-supply = <&reg_3p3v>;
- cd-gpios = <&gpio1 2 0>;
+ cd-gpios = <&gpio3 9 0>;
status = "okay";
};
@@ -499,11 +498,11 @@ reference manual.
status = "okay";
};
-&usdhc3 { /* Module microSD slot */
+&usdhc3 { /* Baseboard microSD slot */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
+ bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
- cd-gpios = <&gpio3 9 0>;
+ cd-gpios = <&gpio1 2 0>;
status = "okay";
};
-
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 95bd7b1..3e644ce 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -836,11 +836,11 @@
status = "disabled";
};
- usdhc1: usdhc@02190000 {
+ usdhc1: usdhc@02198000 {
compatible = "fsl,imx6q-usdhc";
- reg = <0x02190000 0x4000>;
- interrupts = <0 22 0x04>;
- clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+ reg = <0x02198000 0x4000>;
+ interrupts = <0 24 0x04>;
+ clocks = <&clks 165>, <&clks 165>, <&clks 165>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -856,11 +856,11 @@
status = "disabled";
};
- usdhc3: usdhc@02198000 {
+ usdhc3: usdhc@02190000 {
compatible = "fsl,imx6q-usdhc";
- reg = <0x02198000 0x4000>;
- interrupts = <0 24 0x04>;
- clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+ reg = <0x02190000 0x4000>;
+ interrupts = <0 22 0x04>;
+ clocks = <&clks 163>, <&clks 163>, <&clks 163>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@@ -1584,47 +1584,6 @@
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
- >;
- };
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2_2: usdhc2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
@@ -1638,7 +1597,7 @@
>;
};
- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
+ pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { /* 100Mhz */
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
@@ -1653,7 +1612,7 @@
>;
};
- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
+ pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { /* 200Mhz */
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
@@ -1668,7 +1627,7 @@
>;
};
- pinctrl_usdhc3_2: usdhc3grp-2 {
+ pinctrl_usdhc1_2: usdhc1grp-2 {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
@@ -1680,6 +1639,47 @@
};
};
+ usdhc2 {
+ pinctrl_usdhc2_1: usdhc2grp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_2: usdhc2grp-2 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+ };
+
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
--
2.2.1
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