mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
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124 lines
4 KiB
Diff
124 lines
4 KiB
Diff
From 357e09b98bf0c14ec08c73db61708899a053ad28 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:44 +0200
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Subject: [PATCH 4/7] PCI: aardvark: set host and device to the same MAX
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payload size
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Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
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subsystem will not align the MAX payload size between the host and the
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device. This patch ensures that the host and device have the same MAX
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payload size, fixing a number of problems with various PCIe devices.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 4f2bdb84b97f..ec0cd637fd37 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -30,8 +30,10 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -297,7 +299,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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@@ -879,6 +882,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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return err;
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}
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
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+
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+ return 0;
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+}
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+
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
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+{
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+ int mps;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
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+ pcie_set_mps(dev, mps);
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
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+{
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
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+ u32 reg;
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+
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
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+
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+ /* Configure RC MAX payload size */
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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+
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+ /* Configure device MAX payload size */
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
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+}
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+
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -952,6 +1007,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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+ /* Configure the MAX pay load size */
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+ advk_pcie_configure_mps(bus, pcie);
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+
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pci_bus_add_devices(bus);
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return 0;
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}
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--
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2.14.2
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