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https://github.com/archlinuxarm/PKGBUILDs.git
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43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
From 88b3509f36a458b882b895ecf9eb50e922ddb2e1 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:33 +0100
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Subject: [PATCH 1/8] ARM64: dts: marvell: armada37xx: Fix timer interrupt
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specifiers
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Contrary to popular belief, PPIs connected to a GICv3 to not have
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an affinity field similar to that of GICv2. That is consistent
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with the fact that GICv3 is designed to accomodate thousands of
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CPUs, and fitting them as a bitmap in a byte is... difficult.
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++--------
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1 file changed, 4 insertions(+), 8 deletions(-)
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diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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index 4d495ec39202..bc179efb10ef 100644
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@@ -75,14 +75,10 @@
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timer {
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compatible = "arm,armv8-timer";
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- interrupts = <GIC_PPI 13
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- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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- <GIC_PPI 14
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- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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- <GIC_PPI 11
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- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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- <GIC_PPI 10
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- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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--
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2.13.2
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