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33 lines
998 B
Diff
33 lines
998 B
Diff
From ce10ca38bc54e6e8c6063de18a690f1e065339d6 Mon Sep 17 00:00:00 2001
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From: Fabio Estevam <fabio.estevam@freescale.com>
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Date: Fri, 3 May 2013 04:37:11 +0000
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Subject: [PATCH 07/15] mxs: spl_mem_init: Remove erroneous DDR setting
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On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.
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Remove this erroneous setting.
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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---
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arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ----
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1 file changed, 4 deletions(-)
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diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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index 300da0a..df25535 100644
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--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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@@ -279,10 +279,6 @@ static void mx23_mem_init(void)
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setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
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setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
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-
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- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
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- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
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- ;
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}
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#endif
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--
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1.8.2.2
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