mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2024-11-08 22:45:43 +00:00
213 lines
6 KiB
Diff
213 lines
6 KiB
Diff
From 9e1f894719f38a4222cd1713b4f5d1f36c9cd9c2 Mon Sep 17 00:00:00 2001
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From: Kevin Mihelich <kevin@archlinuxarm.org>
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Date: Mon, 12 May 2014 13:56:09 -0600
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Subject: [PATCH] Swap usdhc1 and usdhc3
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U-Boot recognizes the module SD slot as mmc0 and the base board slot as mmc1,
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so carry this forward into the kernel so that when both slots are occupied mmc1
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from U-Boot does not become mmc0.
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Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
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---
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arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 15 +++--
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arch/arm/boot/dts/imx6qdl.dtsi | 104 +++++++++++++++----------------
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2 files changed, 59 insertions(+), 60 deletions(-)
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diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
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index 5244e95..518cefe 100644
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--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
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@@ -480,12 +480,11 @@ reference manual.
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status = "okay";
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};
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-&usdhc1 { /* Baseboard microSD slot */
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+&usdhc1 { /* Module microSD slot */
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_usdhc1_1>;
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- bus-width = <4>;
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+ pinctrl-0 = <&pinctrl_usdhc1_2>;
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vmmc-supply = <®_3p3v>;
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- cd-gpios = <&gpio1 2 0>;
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+ cd-gpios = <&gpio3 9 0>;
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status = "okay";
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};
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@@ -499,11 +498,11 @@ reference manual.
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status = "okay";
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};
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-&usdhc3 { /* Module microSD slot */
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+&usdhc3 { /* Baseboard microSD slot */
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_usdhc3_2>;
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+ pinctrl-0 = <&pinctrl_usdhc3_1>;
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+ bus-width = <4>;
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vmmc-supply = <®_3p3v>;
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- cd-gpios = <&gpio3 9 0>;
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+ cd-gpios = <&gpio1 2 0>;
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status = "okay";
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};
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-
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diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
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index 95bd7b1..3e644ce 100644
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--- a/arch/arm/boot/dts/imx6qdl.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl.dtsi
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@@ -836,11 +836,11 @@
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status = "disabled";
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};
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- usdhc1: usdhc@02190000 {
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+ usdhc1: usdhc@02198000 {
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compatible = "fsl,imx6q-usdhc";
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- reg = <0x02190000 0x4000>;
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- interrupts = <0 22 0x04>;
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- clocks = <&clks 163>, <&clks 163>, <&clks 163>;
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+ reg = <0x02198000 0x4000>;
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+ interrupts = <0 24 0x04>;
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+ clocks = <&clks 165>, <&clks 165>, <&clks 165>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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@@ -856,11 +856,11 @@
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status = "disabled";
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};
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- usdhc3: usdhc@02198000 {
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+ usdhc3: usdhc@02190000 {
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compatible = "fsl,imx6q-usdhc";
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- reg = <0x02198000 0x4000>;
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- interrupts = <0 24 0x04>;
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- clocks = <&clks 165>, <&clks 165>, <&clks 165>;
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+ reg = <0x02190000 0x4000>;
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+ interrupts = <0 22 0x04>;
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+ clocks = <&clks 163>, <&clks 163>, <&clks 163>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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@@ -1584,47 +1584,6 @@
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usdhc1 {
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pinctrl_usdhc1_1: usdhc1grp-1 {
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fsl,pins = <
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- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
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- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
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- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
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- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
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- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
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- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
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- >;
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- };
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- };
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-
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- usdhc2 {
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- pinctrl_usdhc2_1: usdhc2grp-1 {
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- fsl,pins = <
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- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
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- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
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- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
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- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
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- >;
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- };
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-
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- pinctrl_usdhc2_2: usdhc2grp-2 {
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- fsl,pins = <
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- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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- >;
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- };
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- };
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-
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- usdhc3 {
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- pinctrl_usdhc3_1: usdhc3grp-1 {
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- fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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@@ -1638,7 +1597,7 @@
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>;
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};
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- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
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+ pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { /* 100Mhz */
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
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@@ -1653,7 +1612,7 @@
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>;
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};
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- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
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+ pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { /* 200Mhz */
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
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@@ -1668,7 +1627,7 @@
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>;
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};
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- pinctrl_usdhc3_2: usdhc3grp-2 {
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+ pinctrl_usdhc1_2: usdhc1grp-2 {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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@@ -1680,6 +1639,47 @@
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};
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};
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+ usdhc2 {
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+ pinctrl_usdhc2_1: usdhc2grp-1 {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
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+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
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+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
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+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
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+ >;
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+ };
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+
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+ pinctrl_usdhc2_2: usdhc2grp-2 {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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+ >;
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+ };
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+ };
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+
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+ usdhc3 {
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+ pinctrl_usdhc3_1: usdhc3grp-1 {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
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+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
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+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
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+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
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+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
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+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
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+ >;
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+ };
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+ };
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+
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usdhc4 {
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pinctrl_usdhc4_1: usdhc4grp-1 {
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fsl,pins = <
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--
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2.2.1
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