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https://github.com/archlinuxarm/PKGBUILDs.git
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104 lines
3.7 KiB
Diff
104 lines
3.7 KiB
Diff
From 9fe10853807dd1bd370ca2bf8baf76c4cfe242a9 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Mon, 27 Mar 2017 18:28:25 +0800
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Subject: [PATCH 10/12] fix: pci: aardvark: use isr1 interrupt in legacy irq
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mode
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The Aardvark has two interrupts sets, first set is bit[23:16] of
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PCIe ISR 0 register(RD0074840h), second set is bit[11:8] of PCIe
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ISR 1 register(RD0074848h). Only one set should be used, while
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another set should be masked.
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The second set is more advanced, the Legacy INT_X status bit is
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asserted once Assert_INTX message is received, and de-asserted after
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Deassert_INTX message is received, which provides alternate way
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besides of the assert/deassert interrupt pairs in PCIe ISR 0 register.
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Change-Id: Idef2eb474a094754195a031ad580caa8a88f046d
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/38024
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 29 ++++++++++++++++++-----------
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1 file changed, 18 insertions(+), 11 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 072bc70e900c..10154dcf219b 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -103,7 +103,8 @@
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#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
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#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
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#define PCIE_ISR1_FLUSH BIT(5)
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-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
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+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
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+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
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#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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@@ -612,9 +613,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static void advk_pcie_irq_unmask(struct irq_data *d)
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@@ -623,9 +624,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static int advk_pcie_irq_map(struct irq_domain *h,
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@@ -769,14 +770,20 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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static void advk_pcie_handle_int(struct advk_pcie *pcie)
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{
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u32 val, mask, status;
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+ u32 val2, mask2, status2;
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int i, virq;
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val = advk_readl(pcie, PCIE_ISR0_REG);
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mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
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- if (!status) {
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+ val2 = advk_readl(pcie, PCIE_ISR1_REG);
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+ mask2 = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ status2 = val2 & ((~mask2) & PCIE_ISR1_ALL_MASK);
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+
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+ if (!status && !status2) {
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advk_writel(pcie, val, PCIE_ISR0_REG);
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+ advk_writel(pcie, val2, PCIE_ISR1_REG);
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return;
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}
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@@ -786,11 +793,11 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
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/* Process legacy interrupts */
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for (i = 0; i < LEGACY_IRQ_NUM; i++) {
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- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
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+ if (!(status2 & PCIE_ISR1_INTX_ASSERT(i)))
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continue;
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- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
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- PCIE_ISR0_REG);
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+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
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+ PCIE_ISR1_REG);
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virq = irq_find_mapping(pcie->irq_domain, i);
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generic_handle_irq(virq);
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--
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2.13.2
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