mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2024-11-08 22:45:43 +00:00
37 lines
1.2 KiB
Diff
37 lines
1.2 KiB
Diff
From 00e0b98f95698b734a037abe2d3007dbc730c20e Mon Sep 17 00:00:00 2001
|
|
From: Fabio Estevam <fabio.estevam@freescale.com>
|
|
Date: Sun, 5 May 2013 16:11:59 +0000
|
|
Subject: [PATCH 12/15] mxs: Explain why some mx23 DDR registers are not
|
|
configured
|
|
|
|
Put an explanation in the source code as to why some DDR registers do not
|
|
need to be configured.
|
|
|
|
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
---
|
|
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
|
|
index 4ed197b..3902406 100644
|
|
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
|
|
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
|
|
@@ -127,6 +127,15 @@ static void initialize_dram_values(void)
|
|
|
|
mxs_adjust_memory_params(dram_vals);
|
|
|
|
+ /*
|
|
+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
|
|
+ * per FSL bootlets code.
|
|
+ *
|
|
+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
|
|
+ * "reserved".
|
|
+ * HW_DRAM_CTL8 is setup as the last element.
|
|
+ * So skip the initialization of these HW_DRAM_CTL registers.
|
|
+ */
|
|
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
|
|
if (i == 8 || i == 27 || i == 28 || i == 35)
|
|
continue;
|
|
--
|
|
1.8.2.2
|
|
|