From d870d559535d618ab1fd654e032b88f38f803838 Mon Sep 17 00:00:00 2001 From: Wouter van der Vinne Date: Mon, 22 Aug 2022 20:27:18 +0200 Subject: [PATCH] Logic board PCB design added (converterd from Eagle) and moved powerboard schematic drawings to other folder --- PCB/kicad/SB2500-battery-cache.lib | 540 -- PCB/kicad/logicBoard/Microcontroller.sch | 836 +++ PCB/kicad/logicBoard/Psup_5v_and_3.3v.sch | 755 ++ PCB/kicad/logicBoard/SB_HEADERS.sch | 2824 +++++++ .../SB_LOGICBOARD_V01-eagle-import.dcm | 3 + .../logicBoard/SB_LOGICBOARD_V01.kicad_pcb | 6563 +++++++++++++++++ .../SB_LOGICBOARD_V01.pretty/1X06.kicad_mod | 70 + .../1X06_LOCK.kicad_mod | 70 + .../SB_LOGICBOARD_V01.pretty/1X07.kicad_mod | 80 + .../SB_LOGICBOARD_V01.pretty/1X20.kicad_mod | 210 + .../SB_LOGICBOARD_V01.pretty/2X06.kicad_mod | 88 + .../SB_LOGICBOARD_V01.pretty/2X07.kicad_mod | 101 + .../2X20_2MM.kicad_mod | 94 + .../SB_LOGICBOARD_V01.pretty/B2,54.kicad_mod | 17 + .../SB_LOGICBOARD_V01.pretty/C0603.kicad_mod | 22 + .../SB_LOGICBOARD_V01.pretty/C0805.kicad_mod | 22 + .../SB_LOGICBOARD_V01.pretty/C1206.kicad_mod | 22 + .../CRYSTAL-SMD-5X3.kicad_mod | 20 + .../SB_LOGICBOARD_V01.pretty/JP1.kicad_mod | 29 + .../SB_LOGICBOARD_V01.pretty/L0805.kicad_mod | 17 + .../SB_LOGICBOARD_V01.pretty/LED5MM.kicad_mod | 22 + .../SB_LOGICBOARD_V01.pretty/MA03-1.kicad_mod | 41 + .../SB_LOGICBOARD_V01.pretty/R0805.kicad_mod | 22 + .../SB_LOGICBOARD_V01.pretty/SB-PCB.kicad_mod | 61 + .../SML0805.kicad_mod | 22 + .../SB_LOGICBOARD_V01.pretty/SO08.kicad_mod | 40 + .../SB_LOGICBOARD_V01.pretty/SO20W.kicad_mod | 101 + .../SB_LOGICBOARD_V01.pretty/SOT223.kicad_mod | 41 + .../SB_LOGICBOARD_V01.pretty/TQFP64.kicad_mod | 148 + .../SB_LOGICBOARD_V01.pretty/W237-4.kicad_mod | 59 + PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pro | 43 + PCB/kicad/logicBoard/SB_LOGICBOARD_V01.sch | 34 + PCB/kicad/logicBoard/empty.kicad_wks | 5 + PCB/kicad/logicBoard/fp-lib-table | 3 + PCB/kicad/logicBoard/sym-lib-table | 3 + PCB/kicad/{ => powerBoard}/DCBus.sch | 0 .../{ => powerBoard}/SB2500-battery.kicad_pcb | 0 PCB/kicad/{ => powerBoard}/SB2500-battery.pro | 0 PCB/kicad/{ => powerBoard}/SB2500-battery.sch | 0 PCB/kicad/{ => powerBoard}/logicboard.sch | 0 PCB/kicad/{ => powerBoard}/powerline.sch | 0 41 files changed, 12488 insertions(+), 540 deletions(-) delete mode 100644 PCB/kicad/SB2500-battery-cache.lib create mode 100644 PCB/kicad/logicBoard/Microcontroller.sch create mode 100644 PCB/kicad/logicBoard/Psup_5v_and_3.3v.sch create mode 100644 PCB/kicad/logicBoard/SB_HEADERS.sch create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01-eagle-import.dcm create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.kicad_pcb create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06_LOCK.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X07.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X20.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X06.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X07.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X20_2MM.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/B2,54.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0603.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0805.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C1206.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/CRYSTAL-SMD-5X3.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/JP1.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/L0805.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/LED5MM.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/MA03-1.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/R0805.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SB-PCB.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SML0805.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO08.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO20W.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SOT223.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/TQFP64.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/W237-4.kicad_mod create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pro create mode 100644 PCB/kicad/logicBoard/SB_LOGICBOARD_V01.sch create mode 100644 PCB/kicad/logicBoard/empty.kicad_wks create mode 100644 PCB/kicad/logicBoard/fp-lib-table create mode 100644 PCB/kicad/logicBoard/sym-lib-table rename PCB/kicad/{ => powerBoard}/DCBus.sch (100%) rename PCB/kicad/{ => powerBoard}/SB2500-battery.kicad_pcb (100%) rename PCB/kicad/{ => powerBoard}/SB2500-battery.pro (100%) rename PCB/kicad/{ => powerBoard}/SB2500-battery.sch (100%) rename PCB/kicad/{ => powerBoard}/logicboard.sch (100%) rename PCB/kicad/{ => powerBoard}/powerline.sch (100%) diff --git a/PCB/kicad/SB2500-battery-cache.lib b/PCB/kicad/SB2500-battery-cache.lib deleted file mode 100644 index fd9c3cd..0000000 --- a/PCB/kicad/SB2500-battery-cache.lib +++ /dev/null @@ -1,540 +0,0 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# Connector_Generic_Conn_02x20_Odd_Even -# -DEF Connector_Generic_Conn_02x20_Odd_Even J 0 40 Y N 1 F N -F0 "J" 50 1000 50 H V C CNN -F1 "Connector_Generic_Conn_02x20_Odd_Even" 50 -1100 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Connector*:*_2x??_* -$ENDFPLIST -DRAW -S -50 -995 0 -1005 1 1 6 N -S -50 -895 0 -905 1 1 6 N -S -50 -795 0 -805 1 1 6 N -S -50 -695 0 -705 1 1 6 N -S -50 -595 0 -605 1 1 6 N -S -50 -495 0 -505 1 1 6 N -S -50 -395 0 -405 1 1 6 N -S -50 -295 0 -305 1 1 6 N -S -50 -195 0 -205 1 1 6 N -S -50 -95 0 -105 1 1 6 N -S -50 5 0 -5 1 1 6 N -S -50 105 0 95 1 1 6 N -S -50 205 0 195 1 1 6 N -S -50 305 0 295 1 1 6 N -S -50 405 0 395 1 1 6 N -S -50 505 0 495 1 1 6 N -S -50 605 0 595 1 1 6 N -S -50 705 0 695 1 1 6 N -S -50 805 0 795 1 1 6 N -S -50 905 0 895 1 1 6 N -S -50 950 150 -1050 1 1 10 f -S 150 -995 100 -1005 1 1 6 N -S 150 -895 100 -905 1 1 6 N -S 150 -795 100 -805 1 1 6 N -S 150 -695 100 -705 1 1 6 N -S 150 -595 100 -605 1 1 6 N -S 150 -495 100 -505 1 1 6 N -S 150 -395 100 -405 1 1 6 N -S 150 -295 100 -305 1 1 6 N -S 150 -195 100 -205 1 1 6 N -S 150 -95 100 -105 1 1 6 N -S 150 5 100 -5 1 1 6 N -S 150 105 100 95 1 1 6 N -S 150 205 100 195 1 1 6 N -S 150 305 100 295 1 1 6 N -S 150 405 100 395 1 1 6 N -S 150 505 100 495 1 1 6 N -S 150 605 100 595 1 1 6 N -S 150 705 100 695 1 1 6 N -S 150 805 100 795 1 1 6 N -S 150 905 100 895 1 1 6 N -X Pin_1 1 -200 900 150 R 50 50 1 1 P -X Pin_10 10 300 500 150 L 50 50 1 1 P -X Pin_11 11 -200 400 150 R 50 50 1 1 P -X Pin_12 12 300 400 150 L 50 50 1 1 P -X Pin_13 13 -200 300 150 R 50 50 1 1 P -X Pin_14 14 300 300 150 L 50 50 1 1 P -X Pin_15 15 -200 200 150 R 50 50 1 1 P -X Pin_16 16 300 200 150 L 50 50 1 1 P -X Pin_17 17 -200 100 150 R 50 50 1 1 P -X Pin_18 18 300 100 150 L 50 50 1 1 P -X Pin_19 19 -200 0 150 R 50 50 1 1 P -X Pin_2 2 300 900 150 L 50 50 1 1 P -X Pin_20 20 300 0 150 L 50 50 1 1 P -X Pin_21 21 -200 -100 150 R 50 50 1 1 P -X Pin_22 22 300 -100 150 L 50 50 1 1 P -X Pin_23 23 -200 -200 150 R 50 50 1 1 P -X Pin_24 24 300 -200 150 L 50 50 1 1 P -X Pin_25 25 -200 -300 150 R 50 50 1 1 P -X Pin_26 26 300 -300 150 L 50 50 1 1 P -X Pin_27 27 -200 -400 150 R 50 50 1 1 P -X Pin_28 28 300 -400 150 L 50 50 1 1 P -X Pin_29 29 -200 -500 150 R 50 50 1 1 P -X Pin_3 3 -200 800 150 R 50 50 1 1 P -X Pin_30 30 300 -500 150 L 50 50 1 1 P -X Pin_31 31 -200 -600 150 R 50 50 1 1 P -X Pin_32 32 300 -600 150 L 50 50 1 1 P -X Pin_33 33 -200 -700 150 R 50 50 1 1 P -X Pin_34 34 300 -700 150 L 50 50 1 1 P -X Pin_35 35 -200 -800 150 R 50 50 1 1 P -X Pin_36 36 300 -800 150 L 50 50 1 1 P -X Pin_37 37 -200 -900 150 R 50 50 1 1 P -X Pin_38 38 300 -900 150 L 50 50 1 1 P -X Pin_39 39 -200 -1000 150 R 50 50 1 1 P -X Pin_4 4 300 800 150 L 50 50 1 1 P -X Pin_40 40 300 -1000 150 L 50 50 1 1 P -X Pin_5 5 -200 700 150 R 50 50 1 1 P -X Pin_6 6 300 700 150 L 50 50 1 1 P -X Pin_7 7 -200 600 150 R 50 50 1 1 P -X Pin_8 8 300 600 150 L 50 50 1 1 P -X Pin_9 9 -200 500 150 R 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_EMI_Filter_CommonMode -# -DEF Device_EMI_Filter_CommonMode FL 0 10 Y N 1 F N -F0 "FL" 0 175 50 H V C CNN -F1 "Device_EMI_Filter_CommonMode" 0 -175 50 H V C CNN -F2 "" 0 40 50 H I C CNN -F3 "" 0 40 50 H I C CNN -ALIAS EMI_Filter_CommonMode -$FPLIST - L_* - L_CommonMode* -$ENDFPLIST -DRAW -A -80 -80 20 1 1799 0 1 0 N -60 -80 -100 -80 -A -80 80 20 -1799 -1 0 1 0 N -100 80 -60 80 -A -40 -80 20 1 1799 0 1 0 N -20 -80 -60 -80 -A -40 80 20 -1799 -1 0 1 0 N -60 80 -20 80 -A 0 -80 20 1 1799 0 1 0 N 20 -80 -20 -80 -A 0 80 20 -1799 -1 0 1 0 N -20 80 20 80 -A 40 -80 20 1 1799 0 1 0 N 60 -80 20 -80 -A 40 80 20 -1799 -1 0 1 0 N 20 80 60 80 -A 80 -80 20 1 1799 0 1 0 N 100 -80 60 -80 -A 80 80 20 -1799 -1 0 1 0 N 60 80 100 80 -C -120 -50 10 0 1 0 F -C -120 60 10 0 1 0 F -P 2 0 1 0 -100 -80 -100 -100 N -P 2 0 1 0 -100 20 100 20 N -P 2 0 1 0 -100 80 -100 100 N -P 2 0 1 0 100 -80 100 -100 N -P 2 0 1 0 100 -20 -100 -20 N -P 2 0 1 0 100 100 100 80 N -X 1 1 -200 100 100 R 50 50 1 1 P -X 2 2 200 100 100 L 50 50 1 1 P -X 3 3 -200 -100 100 R 50 50 1 1 P -X 4 4 200 -100 100 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_L -# -DEF Device_L L 0 40 N N 1 F N -F0 "L" -50 0 50 V V C CNN -F1 "Device_L" 75 0 50 V V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Choke_* - *Coil* - Inductor_* - L_* -$ENDFPLIST -DRAW -A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 -A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 -A 0 25 25 -899 899 0 1 0 N 0 0 0 50 -A 0 75 25 -899 899 0 1 0 N 0 50 0 100 -X 1 1 0 150 50 D 50 50 1 1 P -X 2 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Q_NIGBT_GCE -# -DEF Device_Q_NIGBT_GCE Q 0 0 Y N 1 F N -F0 "Q" 200 50 50 H V L CNN -F1 "Device_Q_NIGBT_GCE" 200 -50 50 H V L CNN -F2 "" 200 100 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 10 30 -40 30 -80 N -P 2 0 1 10 30 20 30 -20 N -P 2 0 1 10 30 80 30 40 N -P 2 0 1 0 100 -95 30 -60 N -P 2 0 1 0 100 -35 30 0 N -P 2 0 1 0 100 95 30 60 N -P 3 0 1 10 10 75 10 -75 10 -75 N -P 4 0 1 0 55 -85 65 -65 100 -95 55 -85 F -P 4 0 1 0 85 75 75 95 40 65 85 75 F -X G 1 -200 0 210 R 50 50 1 1 I -X C 2 100 200 100 D 50 50 1 1 P -X E 3 100 -200 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_R -# -DEF Device_R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "Device_R" 0 0 50 V V C CNN -F2 "" -70 0 50 V I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - R_* -$ENDFPLIST -DRAW -S -40 -100 40 100 0 1 10 N -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Thermistor_PTC -# -DEF Device_Thermistor_PTC TH 0 0 N Y 1 F N -F0 "TH" -160 0 50 V V C CNN -F1 "Device_Thermistor_PTC" 120 0 50 V V C CNN -F2 "" 50 -200 50 H I L CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - *PTC* - *Thermistor* - PIN?ARRAY* - bornier* - *Terminal?Block* - R_* -$ENDFPLIST -DRAW -A -126 88 7 -265 818 0 1 0 N -120 85 -125 95 -A -110 85 10 1800 -900 0 1 0 N -120 85 -110 75 -A -110 85 10 -900 0 0 1 0 N -110 75 -100 85 -A -110 110 10 0 900 0 1 0 N -100 110 -110 120 -A -110 110 10 900 1800 0 1 0 N -110 120 -120 110 -A -110 110 10 1800 -900 0 1 0 N -120 110 -110 100 -A -104 119 20 -1075 -253 0 1 0 N -110 100 -85 110 -S -40 100 40 -100 0 1 10 N -P 2 0 1 0 -100 85 -100 110 N -P 4 0 1 0 -70 100 -70 60 70 -60 70 -100 N -P 6 0 1 0 -100 -145 -100 -55 -110 -85 -90 -85 -100 -55 -100 -65 F -P 6 0 1 0 -70 -145 -70 -55 -80 -85 -60 -85 -70 -55 -70 -65 F -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Transformer_1P_1S -# -DEF Device_Transformer_1P_1S T 0 40 Y N 1 F N -F0 "T" 0 250 50 H V C CNN -F1 "Device_Transformer_1P_1S" 0 -300 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -A -100 -150 50 899 1 0 1 0 N -100 -100 -50 -150 -A -100 -150 50 -1 -899 0 1 0 N -50 -150 -100 -199 -A -100 -50 50 899 1 0 1 0 N -100 0 -50 -50 -A -100 -50 50 -1 -899 0 1 0 N -50 -50 -100 -99 -A -100 50 50 899 1 0 1 0 N -100 100 -50 50 -A -100 50 50 -1 -899 0 1 0 N -50 50 -100 1 -A -100 150 50 899 1 0 1 0 N -100 200 -50 150 -A -100 150 50 -1 -899 0 1 0 N -50 150 -100 101 -A 100 -50 50 899 -1799 0 1 0 N 100 0 51 -50 -A 100 -50 50 1799 -899 0 1 0 N 51 -50 100 -99 -A 100 50 50 899 -1799 0 1 0 N 100 100 51 50 -A 100 50 50 1799 -899 0 1 0 N 51 50 100 1 -A 100 150 50 899 -1799 0 1 0 N 100 200 51 150 -A 100 150 50 1799 -899 0 1 0 N 51 150 100 101 -A 101 -150 50 910 -1799 0 1 0 N 101 -100 52 -150 -A 101 -150 50 -912 -1799 0 1 0 N 101 -199 52 -150 -P 2 0 1 0 -25 200 -25 -200 N -P 2 0 1 0 25 -200 25 200 N -X AA 1 -400 200 300 R 50 50 1 1 P -X AB 2 -400 -200 300 R 50 50 1 1 P -X SA 3 400 -200 300 L 50 50 1 1 P -X SB 4 400 200 300 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Transformer_1P_SS -# -DEF Device_Transformer_1P_SS T 0 40 Y N 1 F N -F0 "T" 0 250 50 H V C CNN -F1 "Device_Transformer_1P_SS" 0 -300 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -A -100 -150 50 899 1 0 1 0 N -100 -100 -50 -150 -A -100 -150 50 -1 -899 0 1 0 N -50 -150 -100 -199 -A -100 -50 50 899 1 0 1 0 N -100 0 -50 -50 -A -100 -50 50 -1 -899 0 1 0 N -50 -50 -100 -99 -A -100 50 50 899 1 0 1 0 N -100 100 -50 50 -A -100 50 50 -1 -899 0 1 0 N -50 50 -100 1 -A -100 150 50 899 1 0 1 0 N -100 200 -50 150 -A -100 150 50 -1 -899 0 1 0 N -50 150 -100 101 -A 100 -50 50 899 -1799 0 1 0 N 100 0 51 -50 -A 100 -50 50 1799 -899 0 1 0 N 51 -50 100 -99 -A 100 50 50 899 -1799 0 1 0 N 100 100 51 50 -A 100 50 50 1799 -899 0 1 0 N 51 50 100 1 -A 100 150 50 899 -1799 0 1 0 N 100 200 51 150 -A 100 150 50 1799 -899 0 1 0 N 51 150 100 101 -A 101 -150 50 910 -1799 0 1 0 N 101 -100 52 -150 -A 101 -150 50 -912 -1799 0 1 0 N 101 -199 52 -150 -P 2 0 1 0 -25 200 -25 -200 N -P 2 0 1 0 25 -200 25 200 N -X AA 1 -400 200 300 R 50 50 1 1 P -X AB 2 -400 -200 300 R 50 50 1 1 P -X SA 3 400 -200 300 L 50 50 1 1 P -X SC 4 400 0 300 L 50 50 1 1 P -X SB 5 400 200 300 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Varistor -# -DEF Device_Varistor RV 0 0 N Y 1 F N -F0 "RV" 125 0 50 V V C CNN -F1 "Device_Varistor" -125 0 50 V V C CNN -F2 "" -70 0 50 V I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - RV_* - Varistor* -$ENDFPLIST -DRAW -T 0 -70 -80 50 0 0 0 U Normal 0 C C -S -40 -100 40 100 0 1 10 N -P 3 0 1 0 -75 100 -75 50 75 -50 N -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Filter_1FP41-4R -# -DEF Filter_1FP41-4R FL 0 20 Y Y 1 F N -F0 "FL" 0 300 50 H V C CNN -F1 "Filter_1FP41-4R" 0 200 50 H V C CNN -F2 "Filter:Filter_FILTERCON_1FPxx" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS 1FP65-0R 1FP45-1R 1FP65-1R 1FP44-2R 1FP64-2R 1FP42-3R 1FP62-3R 1FP41-4R 1FP61-4R -$FPLIST - Filter*FILTERCON*1FPxx* -$ENDFPLIST -DRAW -A -45 -100 15 1 1799 1 1 0 N -30 -100 -60 -100 -A -45 100 15 1 1799 1 1 0 N -30 100 -60 100 -A -15 -100 15 1 1799 1 1 0 N 0 -100 -30 -100 -A -15 100 15 1 1799 1 1 0 N 0 100 -30 100 -A 15 -100 15 1 1799 1 1 0 N 30 -100 0 -100 -A 15 100 15 1 1799 1 1 0 N 30 100 0 100 -A 45 -100 15 1 1799 1 1 0 N 60 -100 30 -100 -A 45 100 15 1 1799 1 1 0 N 60 100 30 100 -C 0 0 71 1 1 0 N -S -400 150 400 -150 1 1 10 f -S -190 -10 -110 -20 1 1 0 F -S -190 10 -110 20 1 1 0 F -S 110 -10 190 -20 1 1 0 F -S 110 10 190 20 1 1 0 F -P 2 1 1 0 -270 -50 -270 50 N -P 2 1 1 0 -270 -50 -230 -50 N -P 2 1 1 0 -270 50 -230 50 N -P 2 1 1 0 -250 -50 -250 -100 N -P 2 1 1 0 -250 50 -250 100 N -P 2 1 1 0 -230 -50 -230 50 N -P 2 1 1 0 -150 -20 -150 -100 N -P 2 1 1 0 -150 20 -150 100 N -P 2 1 1 0 -60 -100 -300 -100 N -P 2 1 1 0 -60 100 -300 100 N -P 2 1 1 0 60 -100 280 -100 N -P 2 1 1 0 150 -20 150 -100 N -P 2 1 1 0 150 20 150 100 N -P 2 1 1 0 280 100 60 100 N -X P 1 -500 100 100 R 50 50 1 1 P -X P' 2 500 100 100 L 50 50 1 1 P -X N 3 -500 -100 100 R 50 50 1 1 P -X N' 4 500 -100 100 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Relay_RM50-xx21 -# -DEF Relay_RM50-xx21 K 0 20 Y Y 1 F N -F0 "K" 450 150 50 H V L CNN -F1 "Relay_RM50-xx21" 450 50 50 H V L CNN -F2 "Relay_THT:Relay_SPST_Finder_32.21-x300" 1270 -30 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS FINDER-36.11-4301 RM50-xx21 -$FPLIST - Relay*SPST*Finder*32.21*x300* -$ENDFPLIST -DRAW -S -400 200 400 -200 0 1 10 f -S -325 75 -75 -75 0 1 10 N -P 2 0 1 10 -300 -75 -100 75 N -P 2 0 1 0 -200 -200 -200 -75 N -P 2 0 1 0 -200 200 -200 75 N -P 2 0 1 10 -75 0 -50 0 N -P 2 0 1 10 -25 0 0 0 N -P 2 0 1 10 25 0 50 0 N -P 2 0 1 10 75 0 100 0 N -P 2 0 1 10 125 0 150 0 N -P 2 0 1 20 200 -100 125 150 N -P 2 0 1 0 200 -100 200 -200 N -P 4 0 1 0 300 200 300 100 275 125 300 150 N -X ~ 11 200 -300 100 U 50 50 1 1 P -X ~ 14 300 300 100 D 50 50 1 1 P -X ~ A1 -200 300 100 D 50 50 1 1 P -X ~ A2 -200 -300 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Sensor_Current_HX15-P-SP2 -# -DEF Sensor_Current_HX15-P-SP2 U 0 20 Y Y 1 F N -F0 "U" -200 350 50 H V R CNN -F1 "Sensor_Current_HX15-P-SP2" 550 350 50 H V R CNN -F2 "Sensor_Current:LEM_HX15-P-SP2" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - LEM*HX15*P*SP2* -$ENDFPLIST -DRAW -S -300 300 300 -300 0 1 10 f -X GND 1 0 -400 100 U 50 50 1 1 W -X GND 2 100 -400 100 U 50 50 1 1 W -X + 3 0 400 100 D 50 50 1 1 W -X OUT 4 400 0 100 L 50 50 1 1 O -X IN+ 5 -400 100 100 R 50 50 1 1 P -X IN- 6 -400 -100 100 R 50 50 1 1 P -ENDDRAW -ENDDEF -# -# power_+15V -# -DEF power_+15V #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "power_+15V" 0 140 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 2 0 1 0 -30 50 0 100 N -P 2 0 1 0 0 0 0 100 N -P 2 0 1 0 0 100 30 50 N -X +15V 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_+VDC -# -DEF power_+VDC #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -100 50 H I C CNN -F1 "power_+VDC" 0 250 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -C 0 125 75 0 1 10 N -P 2 0 1 20 -45 125 45 125 N -P 2 0 1 0 0 0 0 50 N -P 2 0 1 20 0 80 0 170 N -X +VDC 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_-15V -# -DEF power_-15V #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 100 50 H I C CNN -F1 "power_-15V" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F -X -15V 1 0 0 0 U 50 50 0 0 W N -ENDDRAW -ENDDEF -# -# power_-VDC -# -DEF power_-VDC #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -100 50 H I C CNN -F1 "power_-VDC" 0 250 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -C 0 125 75 0 1 10 N -P 2 0 1 20 -45 125 45 125 N -P 2 0 1 0 0 0 0 50 N -X -VDC 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_Earth -# -DEF power_Earth #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "power_Earth" 0 -150 50 H I C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 2 0 1 0 -25 -75 25 -75 N -P 2 0 1 0 -5 -100 5 -100 N -P 2 0 1 0 0 -50 0 0 N -P 2 0 1 0 50 -50 -50 -50 N -X Earth 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_GND -# -DEF power_GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "power_GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_PRI_MID -# -DEF power_PRI_MID #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "power_PRI_MID" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 2 0 1 0 -30 50 0 100 N -P 2 0 1 0 0 0 0 100 N -P 2 0 1 0 0 100 30 50 N -X PRI_MID 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# pspice_CAP -# -DEF pspice_CAP C 0 10 Y Y 1 F N -F0 "C" 100 150 50 V V C CNN -F1 "pspice_CAP" 100 -150 50 V V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS C -DRAW -P 2 0 1 0 -150 -50 150 -50 N -P 2 0 1 0 -150 50 150 50 N -X ~ 1 0 250 200 D 40 40 1 1 P -X ~ 2 0 -250 200 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/PCB/kicad/logicBoard/Microcontroller.sch b/PCB/kicad/logicBoard/Microcontroller.sch new file mode 100644 index 0000000..e48d2f6 --- /dev/null +++ b/PCB/kicad/logicBoard/Microcontroller.sch @@ -0,0 +1,836 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr User 12398 8268 +encoding utf-8 +Sheet 1 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5800 4100 5100 4100 +Text GLabel 5800 4100 0 10 BiDi ~ 0 +GND +Wire Wire Line + 8100 2500 8900 2500 +Text GLabel 8100 2500 0 10 BiDi ~ 0 +GND +Wire Wire Line + 4900 3500 5800 3500 +Text GLabel 4900 3500 0 10 BiDi ~ 0 +GND +Wire Wire Line + 8900 4100 9000 4100 +Text GLabel 8900 4100 0 10 BiDi ~ 0 +GND +Wire Wire Line + 3200 3800 3200 4000 +Wire Wire Line + 3200 4000 3600 4000 +Wire Wire Line + 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H 10960 3815 59 0000 L BNN +F 1 "2.2uf/6.3v/x7r" H 10960 3615 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0603" H 10900 3800 50 0001 C CNN +F 3 "" H 10900 3800 50 0001 C CNN + 1 10900 3800 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND57 +U 1 1 304CF269 +P 10100 4100 +AR Path="/304CF269" Ref="#GND57" Part="1" +AR Path="/6303E571/304CF269" Ref="#GND057" Part="1" +F 0 "#GND057" H 10100 4100 50 0001 C CNN +F 1 "GND" H 10000 4000 59 0000 L BNN +F 2 "" H 10100 4100 50 0001 C CNN +F 3 "" H 10100 4100 50 0001 C CNN + 1 10100 4100 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:+3V3 #+3V18 +U 1 1 A02C8E50 +P 10100 3600 +AR Path="/A02C8E50" Ref="#+3V18" Part="1" +AR Path="/6303E571/A02C8E50" Ref="#+3V018" Part="1" +F 0 "#+3V018" H 10100 3600 50 0001 C CNN +F 1 "+3V3" V 10000 3400 59 0000 L BNN +F 2 "" H 10100 3600 50 0001 C CNN +F 3 "" H 10100 3600 50 0001 C CNN + 1 10100 3600 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0603 C5 +U 1 1 286F808E +P 4700 5300 +AR Path="/286F808E" Ref="C5" Part="1" +AR Path="/6303E571/286F808E" Ref="C5" Part="1" +F 0 "C5" H 4760 5315 59 0000 L BNN +F 1 "NC" H 4760 5115 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0603" H 4700 5300 50 0001 C CNN +F 3 "" H 4700 5300 50 0001 C CNN + 1 4700 5300 + 0 1 1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND63 +U 1 1 B66ACBFF +P 4400 5300 +AR Path="/B66ACBFF" Ref="#GND63" Part="1" +AR Path="/6303E571/B66ACBFF" Ref="#GND063" Part="1" +F 0 "#GND063" H 4400 5300 50 0001 C CNN +F 1 "GND" H 4300 5200 59 0000 L BNN +F 2 "" H 4400 5300 50 0001 C CNN +F 3 "" H 4400 5300 50 0001 C CNN + 1 4400 5300 + 0 1 1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:SMD-FERRITE-BEAD-200R-2A(0805) L9 +U 1 1 1BD628B3 +P 4400 3600 +AR Path="/1BD628B3" Ref="L9" Part="1" +AR Path="/6303E571/1BD628B3" Ref="L9" Part="1" +F 0 "L9" H 4300 3650 42 0000 L BNN +F 1 "LCBB-601" H 4300 3500 42 0000 L BNN +F 2 "SB_LOGICBOARD_V01:L0805" H 4400 3600 50 0001 C CNN +F 3 "" H 4400 3600 50 0001 C CNN + 1 4400 3600 + -1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:+3V3 #+3V19 +U 1 1 36055ABC +P 4200 3400 +AR Path="/36055ABC" Ref="#+3V19" Part="1" +AR Path="/6303E571/36055ABC" Ref="#+3V019" Part="1" +F 0 "#+3V019" H 4200 3400 50 0001 C CNN +F 1 "+3V3" V 4100 3200 59 0000 L BNN +F 2 "" H 4200 3400 50 0001 C CNN +F 3 "" H 4200 3400 50 0001 C CNN + 1 4200 3400 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0603 C28 +U 1 1 B8A72585 +P 4600 3700 +AR Path="/B8A72585" Ref="C28" Part="1" +AR Path="/6303E571/B8A72585" Ref="C28" Part="1" +F 0 "C28" H 4660 3715 59 0000 L BNN +F 1 "2.2uf/6.3v/x7r" H 4660 3515 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0603" H 4600 3700 50 0001 C CNN +F 3 "" H 4600 3700 50 0001 C CNN + 1 4600 3700 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0603 C42 +U 1 1 F57E786C +P 4800 3700 +AR Path="/F57E786C" Ref="C42" Part="1" +AR Path="/6303E571/F57E786C" Ref="C42" Part="1" +F 0 "C42" H 4860 3715 59 0000 L BNN +F 1 "2.2uf/6.3v/x7r" H 4860 3515 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0603" H 4800 3700 50 0001 C CNN +F 3 "" H 4800 3700 50 0001 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND65 +U 1 1 DC4DDF45 +P 4400 4000 +AR Path="/DC4DDF45" Ref="#GND65" Part="1" +AR Path="/6303E571/DC4DDF45" Ref="#GND065" Part="1" +F 0 "#GND065" H 4400 4000 50 0001 C CNN +F 1 "GND" H 4300 3900 59 0000 L BNN +F 2 "" H 4400 4000 50 0001 C CNN +F 3 "" H 4400 4000 50 0001 C CNN + 1 4400 4000 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:JP1E JP18 +U 1 1 24BB3575 +P 4600 4800 +AR Path="/24BB3575" Ref="JP18" Part="1" +AR Path="/6303E571/24BB3575" Ref="JP18" Part="1" +F 0 "JP18" V 4550 4800 59 0000 L BNN +F 1 "JP1E" V 4825 4800 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:JP1" H 4600 4800 50 0001 C CNN +F 3 "" H 4600 4800 50 0001 C CNN + 1 4600 4800 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:JP1E JP19 +U 1 1 8C09E143 +P 9400 3800 +AR Path="/8C09E143" Ref="JP19" Part="1" +AR Path="/6303E571/8C09E143" Ref="JP19" Part="1" +F 0 "JP19" V 9350 3800 59 0000 L BNN +F 1 "JP1E" V 9625 3800 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:JP1" H 9400 3800 50 0001 C CNN +F 3 "" H 9400 3800 50 0001 C CNN + 1 9400 3800 + 0 1 1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND51 +U 1 1 2CF0FB45 +P 9300 4100 +AR Path="/2CF0FB45" Ref="#GND51" Part="1" +AR Path="/6303E571/2CF0FB45" Ref="#GND051" Part="1" +F 0 "#GND051" H 9300 4100 50 0001 C CNN +F 1 "GND" H 9200 4000 59 0000 L BNN +F 2 "" H 9300 4100 50 0001 C CNN +F 3 "" H 9300 4100 50 0001 C CNN + 1 9300 4100 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:MA03-1 SV1 +U 1 1 1FCB83CC +P 900 3500 +AR Path="/1FCB83CC" Ref="SV1" Part="1" +AR Path="/6303E571/1FCB83CC" Ref="SV1" Part="1" +F 0 "SV1" H 850 3730 59 0000 L BNN +F 1 "MA03-1" H 850 3200 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:MA03-1" H 900 3500 50 0001 C CNN +F 3 "" H 900 3500 50 0001 C CNN + 1 900 3500 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND18 +U 1 1 195191A6 +P 1400 3700 +AR Path="/195191A6" Ref="#GND18" Part="1" +AR Path="/6303E571/195191A6" Ref="#GND018" Part="1" +F 0 "#GND018" H 1400 3700 50 0001 C CNN +F 1 "GND" H 1300 3600 59 0000 L BNN +F 2 "" H 1400 3700 50 0001 C CNN +F 3 "" H 1400 3700 50 0001 C CNN + 1 1400 3700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/PCB/kicad/logicBoard/Psup_5v_and_3.3v.sch b/PCB/kicad/logicBoard/Psup_5v_and_3.3v.sch new file mode 100644 index 0000000..4302d95 --- /dev/null +++ b/PCB/kicad/logicBoard/Psup_5v_and_3.3v.sch @@ -0,0 +1,755 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5300 4800 5200 4800 +Wire Wire Line + 5200 4900 5200 4800 +Wire Wire Line + 5200 4800 4700 4800 +Wire Wire Line + 4700 4800 4500 4800 +Wire Wire Line + 4500 4800 4500 4600 +Wire Wire Line + 4700 4900 4700 4800 +Wire Wire Line + 4500 4800 4500 4900 +Connection ~ 5200 4800 +Text GLabel 5300 4800 0 10 BiDi ~ 0 ++5V +Wire Wire Line + 7200 5400 7200 5300 +Text GLabel 7200 5400 0 10 BiDi ~ 0 +GND +Wire Wire Line + 6600 5100 6600 5300 +Text GLabel 6600 5100 0 10 BiDi ~ 0 +GND +Wire Wire Line + 7600 5300 7600 5400 +Text GLabel 7600 5300 0 10 BiDi ~ 0 +GND +Wire Wire Line + 8000 5300 8000 5400 +Wire Wire Line + 8000 5300 8100 5300 +Text GLabel 8000 5300 0 10 BiDi ~ 0 +GND +Wire Wire Line + 6100 5200 6100 5300 +Text GLabel 6100 5200 0 10 BiDi ~ 0 +GND +Wire Wire Line + 5200 5700 5200 5800 +Text GLabel 5200 5700 0 10 BiDi ~ 0 +GND +Wire Wire Line + 8300 5700 8300 5900 +Text GLabel 8300 5700 0 10 BiDi ~ 0 +GND +Wire Wire Line + 5850 5200 5850 5300 +Text GLabel 5850 5200 0 10 BiDi ~ 0 +GND +Wire Wire Line + 5600 2900 6400 2900 +Text GLabel 5600 2900 0 10 BiDi ~ 0 +GND +Wire Wire Line + 3400 5200 3400 5300 +Text GLabel 3400 5200 0 10 BiDi ~ 0 +GND +Wire Wire Line + 4100 3300 4100 3400 +Text GLabel 4100 3300 0 10 BiDi ~ 0 +GND +Wire Wire Line + 4700 5300 4700 5200 +Wire Wire Line + 4500 5200 4700 5200 +Text GLabel 4700 5300 0 10 BiDi ~ 0 +GND +Wire Wire Line + 5200 5200 5200 5300 +Wire Wire Line + 8300 5200 8300 5300 +Wire Wire Line + 8300 4800 8300 4900 +Wire Wire Line + 8300 4700 8300 4800 +Wire Wire Line + 8000 4600 8000 4800 +Wire Wire Line + 8000 4800 8100 4800 +Wire Wire Line + 8100 4800 8300 4800 +Wire Wire Line + 8000 5000 8000 4800 +Wire Wire Line + 8100 5000 8100 4800 +Connection ~ 8300 4800 +Connection ~ 8000 4800 +Text GLabel 8300 4800 0 10 BiDi ~ 0 ++3V3 +Wire Wire Line + 5700 3100 5700 3400 +Wire Wire Line + 5600 3100 5700 3100 +Text GLabel 5700 3100 0 10 BiDi ~ 0 ++3V3 +Wire Wire Line + 4100 2400 4100 2500 +Text GLabel 4100 2400 0 10 BiDi ~ 0 ++3V3 +Wire Wire Line + 7200 4800 7200 5000 +Wire Wire Line + 7200 4800 7600 4800 +Wire Wire Line + 7000 4800 7200 4800 +Wire Wire Line + 7600 5000 7600 4800 +Connection ~ 7200 4800 +Connection ~ 7600 4800 +Wire Wire Line + 5850 4800 5700 4800 +Wire Wire Line + 5850 4900 5850 4800 +Wire Wire Line + 6100 4800 5850 4800 +Wire Wire Line + 6100 4900 6100 4800 +Wire Wire Line + 6100 4800 6200 4800 +Connection ~ 5850 4800 +Connection ~ 6100 4800 +Wire Wire Line + 6600 2600 5800 2600 +Wire Wire Line + 5800 2600 5800 2700 +Wire Wire Line + 5600 2700 5800 2700 +Text GLabel 6600 2600 2 70 BiDi ~ 0 +RESET +Wire Wire Line + 4100 2900 4100 3000 +Wire Wire Line + 4100 2900 3500 2900 +Text GLabel 3500 2900 0 70 BiDi ~ 0 +RESET +Connection ~ 4100 2900 +Wire Wire Line + 6630 2800 5600 2800 +Text GLabel 6630 2800 2 70 BiDi ~ 0 +SWDIO +Wire Wire Line + 5800 3200 5800 3000 +Wire Wire Line + 6700 3200 5800 3200 +Wire Wire Line + 5800 3000 5600 3000 +Text GLabel 6700 3200 2 70 BiDi ~ 0 +SWCLK +Wire Wire Line + 5700 2600 5700 2400 +Wire Wire Line + 5700 2400 6600 2400 +Wire Wire Line + 5700 2600 5600 2600 +Text GLabel 6600 2400 2 70 BiDi ~ 0 +SWO +Wire Wire Line + 5200 2600 5100 2600 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50 0001 C CNN + 1 7200 5200 + -1 0 0 1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND29 +U 1 1 B0E7A0AF +P 7200 5500 +AR Path="/B0E7A0AF" Ref="#GND29" Part="1" +AR Path="/6303E79D/B0E7A0AF" Ref="#GND029" Part="1" +F 0 "#GND029" H 7200 5500 50 0001 C CNN +F 1 "GND" H 7100 5400 59 0000 L BNN +F 2 "" H 7200 5500 50 0001 C CNN +F 3 "" H 7200 5500 50 0001 C CNN + 1 7200 5500 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0805 C25 +U 1 1 9CB31313 +P 7600 5200 +AR Path="/9CB31313" Ref="C25" Part="1" +AR Path="/6303E79D/9CB31313" Ref="C25" Part="1" +F 0 "C25" H 7390 5025 59 0000 L BNN +F 1 "100n" H 7460 5215 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0805" H 7600 5200 50 0001 C CNN +F 3 "" H 7600 5200 50 0001 C CNN + 1 7600 5200 + -1 0 0 1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC1206 C26 +U 1 1 8E9A860F +P 8000 5200 +AR Path="/8E9A860F" Ref="C26" Part="1" +AR Path="/6303E79D/8E9A860F" Ref="C26" Part="1" +F 0 "C26" H 8060 5215 59 0001 L BNN +F 1 "1206DD106KAT2A" H 8060 5015 59 0001 L BNN +F 2 "SB_LOGICBOARD_V01:C1206" H 8000 5200 50 0001 C CNN +F 3 "" H 8000 5200 50 0001 C CNN + 1 8000 5200 + -1 0 0 1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND32 +U 1 1 FD501343 +P 7600 5500 +AR Path="/FD501343" Ref="#GND32" Part="1" +AR Path="/6303E79D/FD501343" Ref="#GND032" Part="1" +F 0 "#GND032" H 7600 5500 50 0001 C CNN +F 1 "GND" H 7500 5400 59 0000 L BNN +F 2 "" H 7600 5500 50 0001 C CNN +F 3 "" H 7600 5500 50 0001 C CNN + 1 7600 5500 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND33 +U 1 1 C5585B8D +P 8000 5500 +AR Path="/C5585B8D" Ref="#GND33" Part="1" +AR Path="/6303E79D/C5585B8D" Ref="#GND033" Part="1" +F 0 "#GND033" H 8000 5500 50 0001 C CNN +F 1 "GND" H 7900 5400 59 0000 L BNN +F 2 "" H 8000 5500 50 0001 C CNN +F 3 "" H 8000 5500 50 0001 C CNN + 1 8000 5500 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0805 C31 +U 1 1 C442BB79 +P 6100 5100 +AR Path="/C442BB79" Ref="C31" Part="1" +AR Path="/6303E79D/C442BB79" Ref="C31" Part="1" +F 0 "C31" H 6160 5115 59 0000 L BNN +F 1 "100n" H 6160 4915 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0805" H 6100 5100 50 0001 C CNN +F 3 "" H 6100 5100 50 0001 C CNN + 1 6100 5100 + -1 0 0 1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND36 +U 1 1 CF583ECA +P 6100 5400 +AR Path="/CF583ECA" Ref="#GND36" Part="1" +AR Path="/6303E79D/CF583ECA" Ref="#GND036" Part="1" +F 0 "#GND036" H 6100 5400 50 0001 C CNN +F 1 "GND" H 6000 5300 59 0000 L BNN +F 2 "" H 6100 5400 50 0001 C CNN +F 3 "" H 6100 5400 50 0001 C CNN + 1 6100 5400 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:LEDSML0805 5VOK +U 1 1 20425762 +P 5200 5000 +AR Path="/20425762" Ref="5VOK" Part="1" +AR Path="/6303E79D/20425762" Ref="5VOK1" Part="1" +F 0 "5VOK1" V 5340 4820 59 0000 L BNN +F 1 "OSR50805C1E" V 5425 4820 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:SML0805" H 5200 5000 50 0001 C CNN +F 3 "" H 5200 5000 50 0001 C CNN + 1 5200 5000 + 1 0 0 -1 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8800 3700 +Wire Wire Line + 8800 3700 8600 3700 +Text GLabel 8500 3700 0 50 BiDi ~ 0 +TEMPHEAT +Wire Wire Line + 9400 3700 9400 3600 +Wire Wire Line + 9400 3700 9300 3700 +Wire Wire Line + 9600 3800 9600 3700 +Wire Wire Line + 9600 3700 9400 3700 +Text GLabel 9300 3700 0 50 BiDi ~ 0 +VDCBUS +Wire Wire Line + 10600 3700 10600 3600 +Wire Wire Line + 10600 3700 10500 3700 +Wire Wire Line + 10800 3800 10800 3700 +Wire Wire Line + 10800 3700 10600 3700 +Text GLabel 10500 3700 0 50 BiDi ~ 0 +VARISTOR_SENSE +Wire Wire Line + 7900 3800 7900 3700 +Wire Wire Line + 7900 3700 7600 3700 +Wire Wire Line + 7600 3600 7600 3700 +Wire Wire Line + 7600 3700 7500 3700 +Text GLabel 7500 3700 0 50 BiDi ~ 0 +RELAY1_CHECK +Wire Wire Line + 5900 3200 5900 3100 +Wire Wire Line + 5900 3200 5800 3200 +Wire Wire Line + 6200 3300 6200 3200 +Wire Wire Line + 6200 3200 5900 3200 +Text GLabel 5800 3200 0 50 BiDi ~ 0 +RELAY0_CHECK +Wire Wire Line + 13200 4500 13200 4400 +Wire Wire Line + 13200 4500 13100 4500 +Wire Wire Line + 13500 4600 13500 4500 +Wire Wire Line + 13500 4500 13200 4500 +Text GLabel 13100 4500 0 50 BiDi ~ 0 +LCD_MIC +Wire Wire Line + 14500 4900 14500 5300 +Wire Wire Line + 14500 5300 14500 5600 +Text Label 14500 5600 3 50 ~ 0 +RS485_RX_5V +Connection ~ 14500 5300 +Wire Wire Line + 12200 4000 12200 3900 +Text Label 12200 3900 1 50 ~ 0 +RS485_RX_5V +Wire Wire Line + 12200 4500 12200 4400 +Wire Wire Line + 12200 4500 12100 4500 +Text GLabel 12100 4500 0 50 BiDi ~ 0 +RS485_RX +Wire Wire Line + 14600 4900 14600 5300 +Wire Wire Line + 14600 5300 14600 5600 +Text GLabel 14600 5600 1 50 BiDi ~ 0 +RS485_TX +Connection ~ 14600 5300 +Wire Wire Line + 2100 6700 2000 6700 +Wire Wire Line + 2000 6700 1800 6700 +Wire Wire Line + 2000 6800 2000 6700 +Wire Wire Line + 2100 6500 2000 6500 +Wire Wire Line + 2000 6200 1800 6200 +Wire Wire Line + 2200 6200 2000 6200 +Wire Wire Line + 2000 6200 2000 6500 +Wire Wire Line + 1400 6700 1200 6700 +Wire Wire Line + 1200 6700 1100 6700 +Wire Wire Line + 1200 6900 1200 6700 +Text Label 1100 6700 2 50 ~ 0 +ADC_IN0_5V +Wire Wire Line + 2700 6600 2700 6200 +Wire Wire Line + 2700 6200 2600 6200 +Wire Wire Line + 2700 6600 3100 6600 +Text GLabel 3100 6600 2 50 BiDi ~ 0 +ADC_IN0 +Connection ~ 2700 6600 +Wire Wire Line + 7600 10100 7200 10100 +Text GLabel 7200 10100 0 50 BiDi ~ 0 +IO_OUT0 +Wire Wire Line + 7600 10200 7200 10200 +Text GLabel 7200 10200 0 50 BiDi ~ 0 +IO_OUT1 +Wire Wire Line + 7600 10300 7200 10300 +Text Label 7200 10300 2 50 ~ 0 +IO_OUT2 +Wire Wire Line + 7600 10400 7200 10400 +Text Label 7200 10400 2 50 ~ 0 +IO_OUT3 +Wire Wire Line + 8900 10500 9100 10500 +Text Label 8900 10500 0 10 ~ 0 +IO_OUT3 +Wire Wire Line + 8600 10100 8900 10100 +Wire Wire Line + 8900 10100 9100 10100 +Text Label 9100 10100 0 50 ~ 0 +IO_OUT0_5V +Connection ~ 8900 10100 +Wire Wire Line + 8600 10200 8900 10200 +Wire Wire Line + 8900 10200 9100 10200 +Text Label 9100 10200 0 50 ~ 0 +IO_OUT1_5V +Connection ~ 8900 10200 +Wire Wire Line + 8600 10300 8900 10300 +Wire Wire Line + 8900 10300 9100 10300 +Text Label 9100 10300 0 50 ~ 0 +IO_OUT2_5V +Connection ~ 8900 10300 +Wire Wire Line + 8600 10400 8900 10400 +Wire Wire Line + 8900 10400 9100 10400 +Text Label 9100 10400 0 50 ~ 0 +IO_OUT3_5V +Connection ~ 8900 10400 +Wire Wire Line + 15800 1700 15800 1600 +Wire Wire Line + 15800 1700 15400 1700 +Wire Wire Line + 16100 1800 16100 1700 +Wire Wire Line + 16100 1700 15800 1700 +Text GLabel 15400 1700 0 50 BiDi ~ 0 +IO_IN0 +Wire Wire Line + 15500 1100 15800 1100 +Wire Wire Line + 15800 1100 15800 1200 +Text Label 15800 1100 1 50 ~ 0 +IO_IN0_5V +Wire Wire Line + 17600 1200 17600 1100 +Wire Wire Line + 17200 1200 17600 1200 +Text Label 17600 1100 1 50 ~ 0 +ADC_IN1_5V +Wire Wire Line + 17600 1700 17600 1600 +Wire Wire Line + 17600 1700 17300 1700 +Wire Wire Line + 17900 1800 17900 1700 +Wire Wire Line + 17900 1700 17600 1700 +Text GLabel 17300 1700 0 50 BiDi ~ 0 +ADC_IN1 +Wire Wire Line + 17900 8500 17900 8100 +Wire Wire Line + 17900 8100 17900 7800 +Text Label 17900 7800 1 50 ~ 0 +BRIDGE1_LIN_5V +Connection ~ 17900 8100 +Wire Wire Line + 11900 6400 12400 6400 +Text Label 12400 6400 0 50 ~ 0 +BRIDGE1_LIN_5V +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-2X20_2MM MAINB +U 1 1 5503CD28 +P 18100 8700 +AR Path="/5503CD28" Ref="MAINB" Part="1" +AR Path="/6303EA23/5503CD28" Ref="MAINB1" Part="1" +F 0 "MAINB1" H 17850 9725 59 0000 L BNN +F 1 "PINHD-2X20_2MM" H 17850 7500 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:2X20_2MM" H 18100 8700 50 0001 C CNN +F 3 "" H 18100 8700 50 0001 C CNN + 1 18100 8700 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-2X6 ISO +U 1 1 3CABF9DC +P 14700 8000 +AR Path="/3CABF9DC" Ref="ISO" Part="1" +AR Path="/6303EA23/3CABF9DC" Ref="ISO1" Part="1" +F 0 "ISO1" H 14450 8325 59 0000 L BNN +F 1 "PINHD-2X6" H 14450 7500 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:2X06" H 14700 8000 50 0001 C CNN +F 3 "" H 14700 8000 50 0001 C CNN + 1 14700 8000 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-2X7 RX485 +U 1 1 C22FC15E +P 14700 4800 +AR Path="/C22FC15E" Ref="RX485" Part="1" +AR Path="/6303EA23/C22FC15E" Ref="RX485" Part="1" +F 0 "RX485" H 14450 5225 59 0000 L BNN +F 1 "PINHD-2X7" H 14450 4300 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:2X07" H 14700 4800 50 0001 C CNN +F 3 "" H 14700 4800 50 0001 C CNN + 1 14700 4800 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-2X7 LCD +U 1 1 4A66F212 +P 18000 4800 +AR Path="/4A66F212" Ref="LCD" Part="1" +AR Path="/6303EA23/4A66F212" Ref="LCD1" Part="1" +F 0 "LCD1" H 17750 5225 59 0000 L BNN +F 1 "PINHD-2X7" H 17750 4300 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:2X07" H 18000 4800 50 0001 C CNN +F 3 "" H 18000 4800 50 0001 C CNN + 1 18000 4800 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND4 +U 1 1 12C122FD +P 19600 9500 +AR Path="/12C122FD" Ref="#GND4" Part="1" +AR Path="/6303EA23/12C122FD" Ref="#GND04" Part="1" +F 0 "#GND04" H 19600 9500 50 0001 C CNN +F 1 "GND" H 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CNN + 1 14700 4100 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-1X6 JP9 +U 1 1 C8B46213 +P 14800 7300 +AR Path="/C8B46213" Ref="JP9" Part="1" +AR Path="/6303EA23/C8B46213" Ref="JP9" Part="1" +F 0 "JP9" H 14550 7725 59 0000 L BNN +F 1 "PINHD-1X6" H 14550 6900 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:1X06" H 14800 7300 50 0001 C CNN +F 3 "" H 14800 7300 50 0001 C CNN + 1 14800 7300 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-1X6 JP10 +U 1 1 A1D90C10 +P 14800 8400 +AR Path="/A1D90C10" Ref="JP10" Part="1" +AR Path="/6303EA23/A1D90C10" Ref="JP10" Part="1" +F 0 "JP10" H 14550 8825 59 0000 L BNN +F 1 "PINHD-1X6" H 14550 8000 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:1X06" H 14800 8400 50 0001 C CNN +F 3 "" H 14800 8400 50 0001 C CNN + 1 14800 8400 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-1X7 JP11 +U 1 1 E9E46F75 +P 18000 5200 +AR Path="/E9E46F75" Ref="JP11" Part="1" +AR Path="/6303EA23/E9E46F75" Ref="JP11" Part="1" +F 0 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#GND6 +U 1 1 F6847280 +P 18600 4000 +AR Path="/F6847280" Ref="#GND6" Part="1" +AR Path="/6303EA23/F6847280" Ref="#GND06" Part="1" +F 0 "#GND06" H 18600 4000 50 0001 C CNN +F 1 "GND" H 18500 3900 59 0000 L BNN +F 2 "" H 18600 4000 50 0001 C CNN +F 3 "" H 18600 4000 50 0001 C CNN + 1 18600 4000 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND7 +U 1 1 C2693486 +P 18600 5500 +AR Path="/C2693486" Ref="#GND7" Part="1" +AR Path="/6303EA23/C2693486" Ref="#GND07" Part="1" +F 0 "#GND07" H 18600 5500 50 0001 C CNN +F 1 "GND" H 18500 5400 59 0000 L BNN +F 2 "" H 18600 5500 50 0001 C CNN +F 3 "" H 18600 5500 50 0001 C CNN + 1 18600 5500 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND8 +U 1 1 E3161DBF +P 15300 5500 +AR Path="/E3161DBF" Ref="#GND8" Part="1" +AR Path="/6303EA23/E3161DBF" Ref="#GND08" Part="1" +F 0 "#GND08" H 15300 5500 50 0001 C CNN +F 1 "GND" H 15200 5400 59 0000 L BNN +F 2 "" H 15300 5500 50 0001 C CNN +F 3 "" H 15300 5500 50 0001 C CNN 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Ref="WARN" Part="1" +AR Path="/6303EA23/16F216A7" Ref="WARN1" Part="1" +F 0 "WARN1" V 21040 5520 59 0000 L BNN +F 1 "LED5MM" V 21125 5520 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:LED5MM" H 20900 5700 50 0001 C CNN +F 3 "" H 20900 5700 50 0001 C CNN + 1 20900 5700 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND12 +U 1 1 8C4C494A +P 21200 4900 +AR Path="/8C4C494A" Ref="#GND12" Part="1" +AR Path="/6303EA23/8C4C494A" Ref="#GND012" Part="1" +F 0 "#GND012" H 21200 4900 50 0001 C CNN +F 1 "GND" H 21100 4800 59 0000 L BNN +F 2 "" H 21200 4900 50 0001 C CNN +F 3 "" H 21200 4900 50 0001 C CNN + 1 21200 4900 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND13 +U 1 1 85B66688 +P 21200 5300 +AR Path="/85B66688" Ref="#GND13" Part="1" +AR Path="/6303EA23/85B66688" Ref="#GND013" Part="1" +F 0 "#GND013" H 21200 5300 50 0001 C CNN +F 1 "GND" H 21100 5200 59 0000 L BNN +F 2 "" H 21200 5300 50 0001 C CNN +F 3 "" H 21200 5300 50 0001 C CNN + 1 21200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND14 +U 1 1 B9C9B342 +P 21200 5700 +AR Path="/B9C9B342" Ref="#GND14" Part="1" +AR Path="/6303EA23/B9C9B342" Ref="#GND014" Part="1" +F 0 "#GND014" H 21200 5700 50 0001 C CNN +F 1 "GND" H 21100 5600 59 0000 L BNN +F 2 "" H 21200 5700 50 0001 C CNN +F 3 "" H 21200 5700 50 0001 C CNN + 1 21200 5700 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:R-EU_R0805 R4 +U 1 1 0138DFE6 +P 20600 4900 +AR Path="/0138DFE6" Ref="R4" Part="1" +AR Path="/6303EA23/0138DFE6" Ref="R4" Part="1" +F 0 "R4" H 20450 4959 59 0000 L BNN +F 1 "330" H 20450 4770 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:R0805" H 20600 4900 50 0001 C CNN +F 3 "" H 20600 4900 50 0001 C CNN + 1 20600 4900 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:R-EU_R0805 R5 +U 1 1 71430D2B +P 20600 5300 +AR Path="/71430D2B" Ref="R5" Part="1" +AR Path="/6303EA23/71430D2B" Ref="R5" Part="1" +F 0 "R5" H 20450 5359 59 0000 L BNN +F 1 "330" H 20450 5170 59 0000 L BNN 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Ref="IC2" Part="1" +AR Path="/6303EA23/509C8314" Ref="IC2" Part="1" +F 0 "IC2" H 11375 6575 59 0000 L BNN +F 1 "74HCT244DW OR 74VHCT541A" H 11100 6100 59 0001 L BNN +F 2 "SB_LOGICBOARD_V01:SO20W" H 11400 6600 50 0001 C CNN +F 3 "" H 11400 6600 50 0001 C CNN + 1 11400 6600 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:74244DW IC2 +U 2 1 509C8318 +P 11400 7600 +AR Path="/509C8318" Ref="IC2" Part="2" +AR Path="/6303EA23/509C8318" Ref="IC2" Part="2" +F 0 "IC2" H 11375 7575 59 0000 L BNN +F 1 "74HCT244DW OR 74VHCT541A" H 11100 7100 59 0001 L BNN +F 2 "SB_LOGICBOARD_V01:SO20W" H 11400 7600 50 0001 C CNN +F 3 "" H 11400 7600 50 0001 C CNN + 2 11400 7600 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:74244DW IC2 +U 3 1 509C831C +P 11300 5400 +AR Path="/509C831C" Ref="IC2" Part="3" +AR Path="/6303EA23/509C831C" Ref="IC2" Part="3" +F 0 "IC2" H 11275 5375 59 0000 L BNN +F 1 "74HCT244DW OR 74VHCT541A" H 11000 4900 59 0001 L BNN +F 2 "SB_LOGICBOARD_V01:SO20W" H 11300 5400 50 0001 C CNN +F 3 "" H 11300 5400 50 0001 C CNN + 3 11300 5400 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND15 +U 1 1 7499CEA7 +P 11300 5800 +AR Path="/7499CEA7" Ref="#GND15" Part="1" +AR Path="/6303EA23/7499CEA7" Ref="#GND015" Part="1" +F 0 "#GND015" H 11300 5800 50 0001 C CNN +F 1 "GND" H 11200 5700 59 0000 L BNN +F 2 "" H 11300 5800 50 0001 C CNN +F 3 "" H 11300 5800 50 0001 C CNN + 1 11300 5800 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:+5V #P+2 +U 1 1 637B3A6A +P 17400 7200 +AR Path="/637B3A6A" Ref="#P+2" Part="1" +AR Path="/6303EA23/637B3A6A" Ref="#P+02" Part="1" +F 0 "#P+02" H 17400 7200 50 0001 C CNN +F 1 "+5V" V 17300 7000 59 0000 L BNN +F 2 "" H 17400 7200 50 0001 C CNN +F 3 "" H 17400 7200 50 0001 C CNN + 1 17400 7200 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:+5V #P+3 +U 1 1 48C2C5DB +P 11300 5000 +AR Path="/48C2C5DB" Ref="#P+3" Part="1" +AR Path="/6303EA23/48C2C5DB" Ref="#P+03" Part="1" +F 0 "#P+03" H 11300 5000 50 0001 C CNN +F 1 "+5V" V 11200 4800 59 0000 L BNN +F 2 "" H 11300 5000 50 0001 C CNN +F 3 "" H 11300 5000 50 0001 C CNN + 1 11300 5000 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0805 C3 +U 1 1 EE7D9419 +P 10800 5300 +AR Path="/EE7D9419" Ref="C3" Part="1" +AR Path="/6303EA23/EE7D9419" Ref="C3" Part="1" +F 0 "C3" H 10860 5315 59 0000 L BNN +F 1 "100n" H 10860 5115 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0805" H 10800 5300 50 0001 C CNN +F 3 "" H 10800 5300 50 0001 C CNN + 1 10800 5300 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND16 +U 1 1 12C6E2A1 +P 10900 7000 +AR Path="/12C6E2A1" Ref="#GND16" Part="1" +AR Path="/6303EA23/12C6E2A1" Ref="#GND016" Part="1" +F 0 "#GND016" H 10900 7000 50 0001 C CNN +F 1 "GND" H 10800 6900 59 0000 L BNN +F 2 "" H 10900 7000 50 0001 C CNN +F 3 "" H 10900 7000 50 0001 C CNN + 1 10900 7000 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND17 +U 1 1 CBB20165 +P 10900 8000 +AR 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1715 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0805" H 17900 1900 50 0001 C CNN +F 3 "" H 17900 1900 50 0001 C CNN + 1 17900 1900 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:JP1E AIN0 +U 1 1 BBFD11B3 +P 1100 7000 +AR Path="/BBFD11B3" Ref="AIN0" Part="1" +AR Path="/6303EA23/BBFD11B3" Ref="AIN0" Part="1" +F 0 "AIN0" V 1050 7000 59 0000 L BNN +F 1 "JP1E" V 1325 7000 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:JP1" H 1100 7000 50 0001 C CNN +F 3 "" H 1100 7000 50 0001 C CNN + 1 1100 7000 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND30 +U 1 1 A606055F +P 1200 7200 +AR Path="/A606055F" Ref="#GND30" Part="1" +AR Path="/6303EA23/A606055F" Ref="#GND030" Part="1" +F 0 "#GND030" H 1200 7200 50 0001 C CNN +F 1 "GND" H 1100 7100 59 0000 L BNN +F 2 "" H 1200 7200 50 0001 C CNN +F 3 "" H 1200 7200 50 0001 C CNN + 1 1200 7200 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:JP1E JP15 +U 1 1 4861989B +P 17100 1300 +AR Path="/4861989B" Ref="JP15" Part="1" +AR Path="/6303EA23/4861989B" Ref="JP15" Part="1" +F 0 "JP15" V 17050 1300 59 0000 L BNN +F 1 "JP1E" V 17325 1300 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:JP1" H 17100 1300 50 0001 C CNN +F 3 "" H 17100 1300 50 0001 C CNN + 1 17100 1300 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:JP1E JP16 +U 1 1 5B0B6750 +P 15400 1200 +AR Path="/5B0B6750" Ref="JP16" Part="1" +AR Path="/6303EA23/5B0B6750" Ref="JP16" Part="1" +F 0 "JP16" V 15350 1200 59 0000 L BNN +F 1 "JP1E" V 15625 1200 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:JP1" H 15400 1200 50 0001 C CNN +F 3 "" H 15400 1200 50 0001 C CNN + 1 15400 1200 + 0 -1 -1 0 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND47 +U 1 1 E3D3C258 +P 15500 1400 +AR Path="/E3D3C258" Ref="#GND47" Part="1" +AR Path="/6303EA23/E3D3C258" Ref="#GND047" Part="1" +F 0 "#GND047" H 15500 1400 50 0001 C CNN +F 1 "GND" H 15400 1300 59 0000 L BNN +F 2 "" H 15500 1400 50 0001 C CNN +F 3 "" H 15500 1400 50 0001 C CNN + 1 15500 1400 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND34 +U 1 1 85A992D2 +P 17200 1500 +AR Path="/85A992D2" Ref="#GND34" Part="1" +AR Path="/6303EA23/85A992D2" Ref="#GND034" Part="1" +F 0 "#GND034" H 17200 1500 50 0001 C CNN +F 1 "GND" H 17100 1400 59 0000 L BNN +F 2 "" H 17200 1500 50 0001 C CNN +F 3 "" H 17200 1500 50 0001 C CNN + 1 17200 1500 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:PINHD-1X6 JP17 +U 1 1 2206741E +P 8800 10300 +AR Path="/2206741E" Ref="JP17" Part="1" +AR Path="/6303EA23/2206741E" Ref="JP17" Part="1" +F 0 "JP17" H 8550 10725 59 0000 L BNN +F 1 "PINHD-1X6" H 8550 9900 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:1X06" H 8800 10300 50 0001 C CNN +F 3 "" H 8800 10300 50 0001 C CNN + 1 8800 10300 + -1 0 0 1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:GND #GND49 +U 1 1 3E396B75 +P 9100 11000 +AR Path="/3E396B75" Ref="#GND49" Part="1" +AR Path="/6303EA23/3E396B75" Ref="#GND049" Part="1" +F 0 "#GND049" H 9100 11000 50 0001 C CNN +F 1 "GND" H 9000 10900 59 0000 L BNN +F 2 "" H 9100 11000 50 0001 C CNN +F 3 "" H 9100 11000 50 0001 C CNN + 1 9100 11000 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:74244DW IC6 +U 3 1 E24D3BE4 +P 11600 5400 +AR Path="/E24D3BE4" Ref="IC6" Part="3" +AR Path="/6303EA23/E24D3BE4" Ref="IC6" Part="3" +F 0 "IC6" H 11575 5375 59 0000 L BNN +F 1 "74HCT244DW OR 74VHCT541A" H 11300 4900 59 0001 L BNN +F 2 "SB_LOGICBOARD_V01:SO20W" H 11600 5400 50 0001 C CNN +F 3 "" H 11600 5400 50 0001 C CNN + 3 11600 5400 + 1 0 0 -1 +$EndComp +$Comp +L SB_LOGICBOARD_V01-eagle-import:C-EUC0805 C14 +U 1 1 73BFF46F +P 11000 5300 +AR Path="/73BFF46F" Ref="C14" Part="1" +AR Path="/6303EA23/73BFF46F" Ref="C14" Part="1" +F 0 "C14" H 11060 5315 59 0000 L BNN +F 1 "100n" H 11060 5115 59 0000 L BNN +F 2 "SB_LOGICBOARD_V01:C0805" H 11000 5300 50 0001 C CNN +F 3 "" H 11000 5300 50 0001 C CNN + 1 11000 5300 + 1 0 0 -1 +$EndComp +Text Notes 5300 4400 0 42 ~ 0 +A=0.303\nAOffset = 1\nMeas range is now:\n3.3/0.303=10Vpp, That is 30A +/-\n +Text Notes 1500 4300 0 42 ~ 0 +A=1/3.9\nAOffset = 1\nMeas range is now:\n3.3*3.39=12.87Vpp, That is \n230/4.88=47.13\n10.89/2*47.13=303Vac\n +$EndSCHEMATC diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01-eagle-import.dcm b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01-eagle-import.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01-eagle-import.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.kicad_pcb b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.kicad_pcb new file mode 100644 index 0000000..d8e44b5 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.kicad_pcb @@ -0,0 +1,6563 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.12)-1") + + (general + (thickness 1.6) + (drawings 91) + (tracks 1366) + (zones 0) + (modules 119) + (nets 138) + ) + + (page A4) + (layers + (0 Top signal) + (31 Bottom signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFF77F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 RS485_TX) + (net 3 +3V3) + (net 4 BRIDGE1_LIN) + (net 5 +5V) + (net 6 RESET) + (net 7 SWDIO) + (net 8 SWCLK) + (net 9 SWO) + (net 10 IO_IN0) + (net 11 IO_OUT0) + (net 12 HEARTBEAT_LED) + (net 13 BRIDGE0_LIN) + (net 14 RS485_RXENA) + (net 15 RS485_TXENA) + (net 16 LCD_SWB) + (net 17 LCD_D5) + (net 18 LCD_ENA) + (net 19 LCD_RS) + (net 20 LCD_BACKL) + (net 21 LCD_D7) + (net 22 LCD_D6) + (net 23 LCD_RW) + (net 24 LCD_SWA) + (net 25 LCD_D4) + (net 26 LED_YELLOW) + (net 27 LED_RED) + (net 28 LED_GREEN) + (net 29 BRIDGES_SHUTDOWN) + (net 30 GRIDRELAY_0) + (net 31 GRIDRELAY_1) + (net 32 +12V) + (net 33 -12V) + (net 34 VCC/2) + (net 35 TRAFO) + (net 36 CURSENS) + (net 37 TEMPHEAT) + (net 38 VDCBUS) + (net 39 VARISTOR_SENSE) + (net 40 RELAY1_CHECK) + (net 41 RELAY0_CHECK) + (net 42 LCD_MIC) + (net 43 ADC_IN1) + (net 44 RS485_RX) + (net 45 ADC_IN0) + (net 46 IO_OUT1) + (net 47 BRIDGE1_HIN) + (net 48 BRIDGE0_HIN) + (net 49 /Microcontroller/IO_IN1) + (net 50 "Net-(C21-Pad2)") + (net 51 /Microcontroller/IO_IN2) + (net 52 "Net-(C5-Pad1)") + (net 53 "Net-(C30-Pad1)") + (net 54 /Microcontroller/USART2_RX) + (net 55 /Microcontroller/ISOLATION_SENSE) + (net 56 /Microcontroller/USART2_TX) + (net 57 "Net-(C28-Pad1)") + (net 58 /Microcontroller/NC) + (net 59 "Net-(C55-Pad1)") + (net 60 /Microcontroller/NCNO3) + (net 61 "Net-(C57-Pad1)") + (net 62 "Net-(C20-Pad2)") + (net 63 "Net-(C31-Pad2)") + (net 64 "Net-(J1-Pad6)") + (net 65 "Net-(J1-Pad5)") + (net 66 "Net-(J1-Pad4)") + (net 67 "Net-(J1-Pad3)") + (net 68 "Net-(J1-Pad2)") + (net 69 "Net-(J1-Pad1)") + (net 70 /SB_HEADERS/N$63) + (net 71 /SB_HEADERS/N$88) + (net 72 /SB_HEADERS/N$62) + (net 73 /SB_HEADERS/N$87) + (net 74 /SB_HEADERS/SOMESIGNAL) + (net 75 /SB_HEADERS/N$86) + (net 76 /SB_HEADERS/ADC_UNKNOWN) + (net 77 /SB_HEADERS/VARISTOR_SENSE_5V) + (net 78 /SB_HEADERS/VDCBUS_5V) + (net 79 /SB_HEADERS/TEMPHEAT_5V) + (net 80 /SB_HEADERS/TRAFO_5V) + (net 81 /SB_HEADERS/CURSENS_5V) + (net 82 /SB_HEADERS/GRIDRELAY_1_5V) + (net 83 /SB_HEADERS/RELAY1_CHECK_5V) + (net 84 /SB_HEADERS/RELAY0_CHECK_5V) + (net 85 /SB_HEADERS/GRIDRELAY_0_5V) + (net 86 /SB_HEADERS/N$53) + (net 87 /SB_HEADERS/BRIDGES_SHUTDOWN_5V) + (net 88 /SB_HEADERS/BRIDGE1_LIN_5V) + (net 89 /SB_HEADERS/BRIDGE1_HIN_5V) + (net 90 /SB_HEADERS/BRIDGE0_LIN_5V) + (net 91 /SB_HEADERS/BRIDGE0_HIN_5V) + (net 92 /SB_HEADERS/AC_MODEM) + (net 93 /SB_HEADERS/VSUP3) + (net 94 "Net-(JP6-Pad1)") + (net 95 /SB_HEADERS/N$30) + (net 96 /SB_HEADERS/N$42) + (net 97 /SB_HEADERS/N$29) + (net 98 /SB_HEADERS/RS485_GND) + (net 99 /SB_HEADERS/RS485_B) + (net 100 /SB_HEADERS/50OHMTOGND) + (net 101 /SB_HEADERS/RS485_A) + (net 102 /SB_HEADERS/120OHMTOA) + (net 103 /SB_HEADERS/N$25) + (net 104 /SB_HEADERS/N$31) + (net 105 /SB_HEADERS/NC4) + (net 106 /SB_HEADERS/RX2) + (net 107 /SB_HEADERS/NC3) + (net 108 /SB_HEADERS/NC2) + (net 109 /SB_HEADERS/NC1) + (net 110 /SB_HEADERS/RS485_RX_5V) + (net 111 /SB_HEADERS/NC5) + (net 112 /SB_HEADERS/NC6) + (net 113 /SB_HEADERS/LCD_MIC_5V) + (net 114 "Net-(R6-Pad2)") + (net 115 /SB_HEADERS/N$60) + (net 116 "Net-(X1-Pad4)") + (net 117 "Net-(C6-Pad1)") + (net 118 "Net-(IC3-Pad3)") + (net 119 "Net-(IC3-Pad2)") + (net 120 "Net-(IC4-Pad5)") + (net 121 "Net-(IC4-Pad6)") + (net 122 "Net-(IC4-Pad3)") + (net 123 "Net-(IC4-Pad2)") + (net 124 /SB_HEADERS/ADC_IN0_5V) + (net 125 /SB_HEADERS/IO_OUT3_5V) + (net 126 /SB_HEADERS/IO_OUT0_5V) + (net 127 /SB_HEADERS/IO_OUT1_5V) + (net 128 /SB_HEADERS/IO_OUT2_5V) + (net 129 /SB_HEADERS/IO_OUT3) + (net 130 /SB_HEADERS/IO_OUT2) + (net 131 /SB_HEADERS/IO_IN0_5V) + (net 132 /SB_HEADERS/ADC_IN1_5V) + (net 133 "Net-(5VOK1-PadC)") + (net 134 "Net-(3V3OK1-PadC)") + (net 135 "Net-(HB1-PadC)") + (net 136 "Net-(OK1-PadA)") + (net 137 "Net-(ERR1-PadA)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +12V) + (add_net +3V3) + (add_net +5V) + (add_net -12V) + (add_net /Microcontroller/IO_IN1) + (add_net /Microcontroller/IO_IN2) + (add_net /Microcontroller/ISOLATION_SENSE) + (add_net /Microcontroller/NC) + (add_net /Microcontroller/NCNO3) + (add_net /Microcontroller/USART2_RX) + (add_net /Microcontroller/USART2_TX) + (add_net /SB_HEADERS/120OHMTOA) + (add_net /SB_HEADERS/50OHMTOGND) + (add_net /SB_HEADERS/AC_MODEM) + (add_net /SB_HEADERS/ADC_IN0_5V) + (add_net /SB_HEADERS/ADC_IN1_5V) + (add_net /SB_HEADERS/ADC_UNKNOWN) + (add_net /SB_HEADERS/BRIDGE0_HIN_5V) + (add_net /SB_HEADERS/BRIDGE0_LIN_5V) + (add_net /SB_HEADERS/BRIDGE1_HIN_5V) + (add_net /SB_HEADERS/BRIDGE1_LIN_5V) + (add_net /SB_HEADERS/BRIDGES_SHUTDOWN_5V) + (add_net /SB_HEADERS/CURSENS_5V) + (add_net /SB_HEADERS/GRIDRELAY_0_5V) + (add_net /SB_HEADERS/GRIDRELAY_1_5V) + (add_net /SB_HEADERS/IO_IN0_5V) + (add_net /SB_HEADERS/IO_OUT0_5V) + (add_net /SB_HEADERS/IO_OUT1_5V) + (add_net /SB_HEADERS/IO_OUT2) + (add_net /SB_HEADERS/IO_OUT2_5V) + (add_net /SB_HEADERS/IO_OUT3) + (add_net /SB_HEADERS/IO_OUT3_5V) + (add_net /SB_HEADERS/LCD_MIC_5V) + (add_net /SB_HEADERS/N$25) + (add_net /SB_HEADERS/N$29) + (add_net /SB_HEADERS/N$30) + (add_net /SB_HEADERS/N$31) + (add_net /SB_HEADERS/N$42) + (add_net /SB_HEADERS/N$53) + (add_net /SB_HEADERS/N$60) + (add_net /SB_HEADERS/N$62) + (add_net /SB_HEADERS/N$63) + (add_net /SB_HEADERS/N$86) + (add_net /SB_HEADERS/N$87) + (add_net /SB_HEADERS/N$88) + (add_net /SB_HEADERS/NC1) + (add_net /SB_HEADERS/NC2) + (add_net /SB_HEADERS/NC3) + (add_net /SB_HEADERS/NC4) + (add_net /SB_HEADERS/NC5) + (add_net /SB_HEADERS/NC6) + (add_net /SB_HEADERS/RELAY0_CHECK_5V) + (add_net /SB_HEADERS/RELAY1_CHECK_5V) + (add_net /SB_HEADERS/RS485_A) + (add_net /SB_HEADERS/RS485_B) + (add_net /SB_HEADERS/RS485_GND) + (add_net /SB_HEADERS/RS485_RX_5V) + (add_net /SB_HEADERS/RX2) + (add_net /SB_HEADERS/SOMESIGNAL) + (add_net /SB_HEADERS/TEMPHEAT_5V) + (add_net /SB_HEADERS/TRAFO_5V) + (add_net /SB_HEADERS/VARISTOR_SENSE_5V) + (add_net /SB_HEADERS/VDCBUS_5V) + (add_net /SB_HEADERS/VSUP3) + (add_net ADC_IN0) + (add_net ADC_IN1) + (add_net BRIDGE0_HIN) + (add_net BRIDGE0_LIN) + (add_net BRIDGE1_HIN) + (add_net BRIDGE1_LIN) + (add_net BRIDGES_SHUTDOWN) + (add_net CURSENS) + (add_net GND) + (add_net GRIDRELAY_0) + (add_net GRIDRELAY_1) + (add_net HEARTBEAT_LED) + (add_net IO_IN0) + (add_net IO_OUT0) + (add_net IO_OUT1) + (add_net LCD_BACKL) + (add_net LCD_D4) + (add_net LCD_D5) + (add_net LCD_D6) + (add_net LCD_D7) + (add_net LCD_ENA) + (add_net LCD_MIC) + (add_net LCD_RS) + (add_net LCD_RW) + (add_net LCD_SWA) + (add_net LCD_SWB) + (add_net LED_GREEN) + (add_net LED_RED) + (add_net LED_YELLOW) + (add_net "Net-(3V3OK1-PadC)") + (add_net "Net-(5VOK1-PadC)") + (add_net "Net-(C20-Pad2)") + (add_net "Net-(C21-Pad2)") + (add_net "Net-(C28-Pad1)") + (add_net "Net-(C30-Pad1)") + (add_net "Net-(C31-Pad2)") + (add_net "Net-(C5-Pad1)") + (add_net "Net-(C55-Pad1)") + (add_net "Net-(C57-Pad1)") + (add_net "Net-(C6-Pad1)") + (add_net "Net-(ERR1-PadA)") + (add_net "Net-(HB1-PadC)") + (add_net "Net-(IC3-Pad2)") + (add_net "Net-(IC3-Pad3)") + (add_net "Net-(IC4-Pad2)") + (add_net "Net-(IC4-Pad3)") + (add_net "Net-(IC4-Pad5)") + (add_net "Net-(IC4-Pad6)") + (add_net "Net-(J1-Pad1)") + (add_net "Net-(J1-Pad2)") + (add_net "Net-(J1-Pad3)") + (add_net "Net-(J1-Pad4)") + (add_net "Net-(J1-Pad5)") + (add_net "Net-(J1-Pad6)") + (add_net "Net-(JP6-Pad1)") + (add_net "Net-(OK1-PadA)") + (add_net "Net-(R6-Pad2)") + (add_net "Net-(X1-Pad4)") + (add_net RELAY0_CHECK) + (add_net RELAY1_CHECK) + (add_net RESET) + (add_net RS485_RX) + (add_net RS485_RXENA) + (add_net RS485_TX) + (add_net RS485_TXENA) + (add_net SWCLK) + (add_net SWDIO) + (add_net SWO) + (add_net TEMPHEAT) + (add_net TRAFO) + (add_net VARISTOR_SENSE) + (add_net VCC/2) + (add_net VDCBUS) + ) + + (module SB_LOGICBOARD_V01:TQFP64 (layer Top) (tedit 0) (tstamp 6303C944) + (at 193.0011 97.5036) + (descr "64-Lead TQFP Plastic Thin Quad Flatpack - 10x10x1mm Body, 2mmFP") + (path /6303E571/BCE09641) + (fp_text reference U$5 (at -2.75 -0.75) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value STM32F405RG (at -3 3) (layer F.Fab) + (effects (font (size 0.38608 0.38608) (thickness 0.030886)) (justify left bottom)) + ) + (fp_line (start 5.1 5.1) (end 5.1 4.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.1 5.1) (end 5.1 5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5.1 4.1) (end -4.1 5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 5.1 -5.1) (end 5.1 -4.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.1 -5.1) (end 5.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5.1 -5.1) (end -4.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5.1 -4.1) (end -5.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5 -5) (end 5 -5) (layer F.Fab) (width 0.2032)) + (fp_line (start -5 5) (end -5 -5) (layer F.Fab) (width 0.2032)) + (fp_line (start 5 5) (end -5 5) (layer F.Fab) (width 0.2032)) + (fp_line (start 5 -5) (end 5 5) (layer F.Fab) (width 0.2032)) + (pad 58 smd rect (at -5.75 0.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 2 RS485_TX) (solder_mask_margin 0.1016)) + (pad 60 smd rect (at -5.75 1.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 62 smd rect (at -5.75 2.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 14 RS485_RXENA) (solder_mask_margin 0.1016)) + (pad 64 smd rect (at -5.75 3.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 63 smd rect (at -5.75 3.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 61 smd rect (at -5.75 2.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 17 LCD_D5) (solder_mask_margin 0.1016)) + (pad 59 smd rect (at -5.75 1.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 44 RS485_RX) (solder_mask_margin 0.1016)) + (pad 49 smd rect (at -5.75 -3.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 8 SWCLK) (solder_mask_margin 0.1016)) + (pad 51 smd rect (at -5.75 -2.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 21 LCD_D7) (solder_mask_margin 0.1016)) + (pad 53 smd rect (at -5.75 -1.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 25 LCD_D4) (solder_mask_margin 0.1016)) + (pad 55 smd rect (at -5.75 -0.75 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 9 SWO) (solder_mask_margin 0.1016)) + (pad 50 smd rect (at -5.75 -3.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 49 /Microcontroller/IO_IN1) (solder_mask_margin 0.1016)) + (pad 52 smd rect (at -5.75 -2.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 22 LCD_D6) (solder_mask_margin 0.1016)) + (pad 54 smd rect (at -5.75 -1.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 24 LCD_SWA) (solder_mask_margin 0.1016)) + (pad 57 smd rect (at -5.75 0.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 18 LCD_ENA) (solder_mask_margin 0.1016)) + (pad 56 smd rect (at -5.75 -0.25 270) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 19 LCD_RS) (solder_mask_margin 0.1016)) + (pad 42 smd rect (at -0.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 48 BRIDGE0_HIN) (solder_mask_margin 0.1016)) + (pad 44 smd rect (at -1.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 11 IO_OUT0) (solder_mask_margin 0.1016)) + (pad 46 smd rect (at -2.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 7 SWDIO) (solder_mask_margin 0.1016)) + (pad 48 smd rect (at -3.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 47 smd rect (at -3.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 50 "Net-(C21-Pad2)") (solder_mask_margin 0.1016)) + (pad 45 smd rect (at -2.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 15 RS485_TXENA) (solder_mask_margin 0.1016)) + (pad 43 smd rect (at -1.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 47 BRIDGE1_HIN) (solder_mask_margin 0.1016)) + (pad 33 smd rect (at 3.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 28 LED_GREEN) (solder_mask_margin 0.1016)) + (pad 35 smd rect (at 2.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 13 BRIDGE0_LIN) (solder_mask_margin 0.1016)) + (pad 37 smd rect (at 1.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 12 HEARTBEAT_LED) (solder_mask_margin 0.1016)) + (pad 39 smd rect (at 0.75 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 20 LCD_BACKL) (solder_mask_margin 0.1016)) + (pad 34 smd rect (at 3.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 29 BRIDGES_SHUTDOWN) (solder_mask_margin 0.1016)) + (pad 36 smd rect (at 2.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 4 BRIDGE1_LIN) (solder_mask_margin 0.1016)) + (pad 38 smd rect (at 1.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 23 LCD_RW) (solder_mask_margin 0.1016)) + (pad 41 smd rect (at -0.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 46 IO_OUT1) (solder_mask_margin 0.1016)) + (pad 40 smd rect (at 0.25 -5.75 180) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 16 LCD_SWB) (solder_mask_margin 0.1016)) + (pad 26 smd rect (at 5.75 -0.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 51 /Microcontroller/IO_IN2) (solder_mask_margin 0.1016)) + (pad 28 smd rect (at 5.75 -1.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 27 LED_RED) (solder_mask_margin 0.1016)) + (pad 30 smd rect (at 5.75 -2.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 52 "Net-(C5-Pad1)") (solder_mask_margin 0.1016)) + (pad 32 smd rect (at 5.75 -3.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 31 smd rect (at 5.75 -3.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 53 "Net-(C30-Pad1)") (solder_mask_margin 0.1016)) + (pad 29 smd rect (at 5.75 -2.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 26 LED_YELLOW) (solder_mask_margin 0.1016)) + (pad 27 smd rect (at 5.75 -1.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 42 LCD_MIC) (solder_mask_margin 0.1016)) + (pad 17 smd rect (at 5.75 3.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 54 /Microcontroller/USART2_RX) (solder_mask_margin 0.1016)) + (pad 19 smd rect (at 5.75 2.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 21 smd rect (at 5.75 1.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 40 RELAY1_CHECK) (solder_mask_margin 0.1016)) + (pad 23 smd rect (at 5.75 0.75 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 10 IO_IN0) (solder_mask_margin 0.1016)) + (pad 18 smd rect (at 5.75 3.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 20 smd rect (at 5.75 2.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 38 VDCBUS) (solder_mask_margin 0.1016)) + (pad 22 smd rect (at 5.75 1.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 41 RELAY0_CHECK) (solder_mask_margin 0.1016)) + (pad 25 smd rect (at 5.75 -0.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 55 /Microcontroller/ISOLATION_SENSE) (solder_mask_margin 0.1016)) + (pad 24 smd rect (at 5.75 0.25 90) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 43 ADC_IN1) (solder_mask_margin 0.1016)) + (pad 10 smd rect (at 0.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 35 TRAFO) (solder_mask_margin 0.1016)) + (pad 12 smd rect (at 1.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 14 smd rect (at 2.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 39 VARISTOR_SENSE) (solder_mask_margin 0.1016)) + (pad 16 smd rect (at 3.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 56 /Microcontroller/USART2_TX) (solder_mask_margin 0.1016)) + (pad 15 smd rect (at 3.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 37 TEMPHEAT) (solder_mask_margin 0.1016)) + (pad 13 smd rect (at 2.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 57 "Net-(C28-Pad1)") (solder_mask_margin 0.1016)) + (pad 11 smd rect (at 1.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 58 /Microcontroller/NC) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -3.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 3 smd rect (at -2.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 31 GRIDRELAY_1) (solder_mask_margin 0.1016)) + (pad 5 smd rect (at -1.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 59 "Net-(C55-Pad1)") (solder_mask_margin 0.1016)) + (pad 7 smd rect (at -0.75 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 6 RESET) (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -3.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 60 /Microcontroller/NCNO3) (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -2.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 30 GRIDRELAY_0) (solder_mask_margin 0.1016)) + (pad 6 smd rect (at -1.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 61 "Net-(C57-Pad1)") (solder_mask_margin 0.1016)) + (pad 9 smd rect (at 0.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 36 CURSENS) (solder_mask_margin 0.1016)) + (pad 8 smd rect (at -0.25 5.75) (size 0.22 1) (layers Top F.Paste F.Mask) + (net 45 ADC_IN0) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303C992) + (at 161.5011 106.0036 90) + (descr CAPACITOR

) + (path /6303E79D/12BF572B) + (fp_text reference C20 (at -2 0.5) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 62 "Net-(C20-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303C9A0) + (at 158.5011 106.0036 90) + (descr CAPACITOR

) + (path /6303E79D/9CB31313) + (fp_text reference C25 (at 0.5 -2 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 62 "Net-(C20-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C1206 (layer Top) (tedit 0) (tstamp 6303C9AE) + (at 168.7236 105.6386 90) + (descr CAPACITOR) + (path /6303E79D/8E9A860F) + (fp_text reference C26 (at 2.785 0.5 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 1206DD106KAT2A (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.473 -0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0 90) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -1.4 0 90) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303C9BC) + (at 154.2511 106.0036 90) + (descr CAPACITOR

) + (path /6303E79D/C442BB79) + (fp_text reference C31 (at 0.5 1 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 63 "Net-(C31-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SML0805 (layer Top) (tedit 0) (tstamp 6303C9CA) + (at 94.3511 91.3436 90) + (descr "SML0805-2CW-TR (0805 PROFILE) COOL WHITE

\nSource: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf") + (path /6303E79D/20425762) + (fp_text reference 5VOK1 (at -2.16 -0.85 90) (layer F.SilkS) + (effects (font (size 1.14 1.14) (thickness 0.1368)) (justify left bottom)) + ) + (fp_text value OSR50805C1E (at -1.5 2 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_circle (center -0.275 -0.4) (end -0.2125 -0.4) (layer F.SilkS) (width 0.125)) + (fp_line (start -0.025 0.175) (end -0.175 0.025) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0.15 0) (end -0.025 0.175) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0 -0.15) (end 0.15 0) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.175 0.025) (end 0 -0.15) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.95 -0.55) (end -0.95 0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 -0.55) (end -0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 0.55) (end 0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.95 0.55) (end 0.95 0.55) (layer F.Fab) (width 0.1016)) + (pad A smd rect (at 1.05 0 90) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + (pad C smd rect (at -1.05 0 90) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 133 "Net-(5VOK1-PadC)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303C9D8) + (at 94.3511 95.6736 90) + (descr RESISTOR

) + (path /6303E79D/64ABC050) + (fp_text reference R108 (at -5.58 0.4 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2k2/1% (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 133 "Net-(5VOK1-PadC)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SML0805 (layer Top) (tedit 0) (tstamp 6303C9E6) + (at 200.7061 66.6586 270) + (descr "SML0805-2CW-TR (0805 PROFILE) COOL WHITE

\nSource: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf") + (path /6303E79D/22729381) + (fp_text reference 3V3OK1 (at 1.75 0.75 90) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value OSR50805C1E (at -1.5 2 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_circle (center -0.275 -0.4) (end -0.2125 -0.4) (layer F.SilkS) (width 0.125)) + (fp_line (start -0.025 0.175) (end -0.175 0.025) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0.15 0) (end -0.025 0.175) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0 -0.15) (end 0.15 0) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.175 0.025) (end 0 -0.15) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.95 -0.55) (end -0.95 0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 -0.55) (end -0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 0.55) (end 0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.95 0.55) (end 0.95 0.55) (layer F.Fab) (width 0.1016)) + (pad A smd rect (at 1.05 0 270) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad C smd rect (at -1.05 0 270) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 134 "Net-(3V3OK1-PadC)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303C9F4) + (at 195.5011 66.7536 90) + (descr RESISTOR

) + (path /6303E79D/C6AC243E) + (fp_text reference R109 (at -0.635 -1.27 90) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text value 2k2/1% (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 134 "Net-(3V3OK1-PadC)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303CA02) + (at 151.2511 106.0036 270) + (descr CAPACITOR

) + (path /6303E79D/15BE111E) + (fp_text reference C74 (at 0.25 2 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 63 "Net-(C31-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:B2,54 (layer Top) (tedit 0) (tstamp 6303CA10) + (at 172.8261 103.3536 90) + (descr "TEST PAD") + (path /6303E79D/FCCF6EE1) + (fp_text reference 3V3 (at 3.024 2.295) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value NC (at -1.27 1.397 90) (layer F.Fab) + (effects (font (size 0.02413 0.02413) (thickness 0.00193)) (justify left bottom)) + ) + (fp_text user >TP_SIGNAL_NAME (at -1.27 3.175 90) (layer Dwgs.User) + (effects (font (size 0.95 0.95) (thickness 0.08)) (justify left bottom)) + ) + (fp_circle (center 0 0) (end 0.635 0) (layer Dwgs.User) (width 0.254)) + (fp_line (start 0 0.635) (end 0 -0.635) (layer Dwgs.User) (width 0.0024)) + (fp_line (start -0.635 0) (end 0.635 0) (layer Dwgs.User) (width 0.0024)) + (pad TP smd roundrect (at 0 0 90) (size 2.54 2.54) (layers Top F.Mask) (roundrect_rratio 0.5) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA18) + (at 189.0011 89.0036 270) + (descr CAPACITOR) + (path /6303E571/9E548DD3) + (fp_text reference C21 (at -4.635 0.615 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 270) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 50 "Net-(C21-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 270) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA26) + (at 203.0011 92.0036) + (descr CAPACITOR) + (path /6303E571/0344B64C) + (fp_text reference C30 (at 1.365 0.365) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 53 "Net-(C30-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303CA34) + (at 186.5011 113.0036 270) + (descr CAPACITOR

) + (path /6303E571/B172C0F6) + (fp_text reference C55 (at 2.075 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22pf (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 59 "Net-(C55-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303CA42) + (at 191.0011 113.0036 270) + (descr CAPACITOR

) + (path /6303E571/573C8F8F) + (fp_text reference C57 (at 1.98 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22pf (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 61 "Net-(C57-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:CRYSTAL-SMD-5X3 (layer Top) (tedit 0) (tstamp 6303CA50) + (at 189.0011 108.5036) + (path /6303E571/169E846A) + (fp_text reference Y3 (at -4.345 -0.8175 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 8.00M-CFPX104 (at -2.54 2.54) (layer F.Fab) + (effects (font (size 0.38608 0.38608) (thickness 0.030886)) (justify left bottom)) + ) + (fp_line (start -2.5 -0.3) (end -2.5 0.3) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.6 1.6) (end -0.6 1.6) (layer F.SilkS) (width 0.2032)) + (fp_line (start 2.5 -0.3) (end 2.5 0.3) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.6 -1.6) (end 0.6 -1.6) (layer F.SilkS) (width 0.2032)) + (pad 2 smd rect (at 1.85 1.15) (size 1.9 1.1) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -1.85 -1.15) (size 1.9 1.1) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 1.85 -1.15) (size 1.9 1.1) (layers Top F.Paste F.Mask) + (net 61 "Net-(C57-Pad1)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -1.85 1.15) (size 1.9 1.1) (layers Top F.Paste F.Mask) + (net 59 "Net-(C55-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA5B) + (at 186.8211 90.2486 90) + (descr CAPACITOR) + (path /6303E571/324ED17E) + (fp_text reference C37 (at 1.865 0.865 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA69) + (at 204.0011 72.5036 90) + (descr CAPACITOR) + (path /6303E571/A1C79CAE) + (fp_text reference C38 (at -4.635 0.365 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA77) + (at 200.0011 91.0036 90) + (descr CAPACITOR) + (path /6303E571/D731FBCB) + (fp_text reference C39 (at 1.865 0.615 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA85) + (at 184.7511 103.0036 90) + (descr CAPACITOR) + (path /6303E571/132A8524) + (fp_text reference C40 (at -1.385 -1.135 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CA93) + (at 200.5011 103.2536 180) + (descr CAPACITOR) + (path /6303E571/0D7E0265) + (fp_text reference C41 (at -1.385 -0.6625 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CAA1) + (at 147.5011 105.0036) + (path /6303E79D/BF223536) + (fp_text reference L26 (at -1.905 -1.143) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 63 "Net-(C31-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 5 +5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CAAB) + (at 164.7511 103.5036) + (path /6303E79D/8233CBD5) + (fp_text reference L27 (at -1.905 -1.143) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 62 "Net-(C20-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CAB5) + (at 203.0011 94.0036) + (descr CAPACITOR) + (path /6303E571/286F808E) + (fp_text reference C5 (at 3.385 -0.615) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value NC (at -0.635 1.905) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 52 "Net-(C5-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CAC3) + (at 199.0011 107.0036 270) + (path /6303E571/1BD628B3) + (fp_text reference L9 (at -1.095 -1.123 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 270) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 270) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 57 "Net-(C28-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CACD) + (at 196.0011 106.0036 180) + (descr CAPACITOR) + (path /6303E571/B8A72585) + (fp_text reference C28 (at 1.5 0.69) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 57 "Net-(C28-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0603 (layer Top) (tedit 0) (tstamp 6303CADB) + (at 196.0011 108.2536 180) + (descr CAPACITOR) + (path /6303E571/F57E786C) + (fp_text reference C42 (at 1.42 0.02) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 57 "Net-(C28-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SOT223 (layer Top) (tedit 0) (tstamp 6303CAE9) + (at 156.5011 98.7536) + (descr "Small Outline Transistor") + (path /6303E79D/41C6949E) + (fp_text reference IC1 (at -2.54 -0.0508) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text value MCP1826S-3302ED (at -2.54 1.3208) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 1.8796 3.6576) (xy 2.7432 3.6576) (xy 2.7432 1.8034) (xy 1.8796 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.7432 3.6576) (xy -1.8796 3.6576) (xy -1.8796 1.8034) (xy -2.7432 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.4318 3.6576) (xy 0.4318 3.6576) (xy 0.4318 1.8034) (xy -0.4318 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.6002 -1.8034) (xy 1.6002 -1.8034) (xy 1.6002 -3.6576) (xy -1.6002 -3.6576)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.8796 3.6576) (xy 2.7432 3.6576) (xy 2.7432 1.8034) (xy 1.8796 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.7432 3.6576) (xy -1.8796 3.6576) (xy -1.8796 1.8034) (xy -2.7432 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.4318 3.6576) (xy 0.4318 3.6576) (xy 0.4318 1.8034) (xy -0.4318 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.6002 -1.8034) (xy 1.6002 -1.8034) (xy 1.6002 -3.6576) (xy -1.6002 -3.6576)) (layer F.Fab) (width 0)) + (fp_text user 2 (at -1.2906 4.3274) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 1 (at -3.4526 4.318) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 4 (at 1.905 -2.54) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 3 (at 1.0208 4.318) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_line (start -3.2766 -1.778) (end 3.2766 -1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start -3.2766 1.778) (end -3.2766 -1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.2766 1.778) (end -3.2766 1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.2766 -1.778) (end 3.2766 1.778) (layer F.SilkS) (width 0.2032)) + (pad 4 smd rect (at 0 -3.099) (size 3.6 2.2) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 2.3114 3.0988) (size 1.2192 2.2352) (layers Top F.Paste F.Mask) + (net 62 "Net-(C20-Pad2)") (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 0 3.0988) (size 1.2192 2.2352) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -2.3114 3.0988) (size 1.2192 2.2352) (layers Top F.Paste F.Mask) + (net 63 "Net-(C31-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303CB00) + (at 177.5011 103.5036 270) + (descr CAPACITOR

) + (path /6303E79D/9F409597) + (fp_text reference C61 (at 1.98 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:1X06_LOCK (layer Top) (tedit 0) (tstamp 6303CB0E) + (at 207.0011 69.5036) + (descr "This footprint was designed to help hold the alignment of a through-hole component (i.e. 6-pin header) while soldering it into place. \nYou may notice that each hole has been shifted either up or down by 0.005 of an inch from it's more standard position (which is a perfectly straight line). \nThis slight alteration caused the pins (the squares in the middle) to touch the edges of the holes. Because they are alternating, it causes a \"brace\" \nto hold the component in place. 0.005 has proven to be the perfect amount of \"off-center\" position when using our standard breakaway headers.\nAlthough looks a little odd when you look at the bare footprint, once you have a header in there, the alteration is very hard to notice. Also,\nif you push a header all the way into place, it is covered up entirely on the bottom side. This idea of altering the position of holes to aid alignment \nwill be further integrated into the Sparkfun Library for other footprints. It can help hold any component with 3 or more connection pins.") + (path /6303E79D/414D4D2E) + (fp_text reference J1 (at -1.27 -1.778) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text value ZL201-06G (at -1.27 3.302) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 12.4079 0.4191) (xy 12.9921 0.4191) (xy 12.9921 -0.1651) (xy 12.4079 -0.1651)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 9.8679 0.4191) (xy 10.4521 0.4191) (xy 10.4521 -0.1651) (xy 9.8679 -0.1651)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 7.3279 0.4191) (xy 7.9121 0.4191) (xy 7.9121 -0.1651) (xy 7.3279 -0.1651)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.7879 0.4191) (xy 5.3721 0.4191) (xy 5.3721 -0.1651) (xy 4.7879 -0.1651)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.2479 0.4191) (xy 2.8321 0.4191) (xy 2.8321 -0.1651) (xy 2.2479 -0.1651)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.2921 0.4191) (xy 0.2921 0.4191) (xy 0.2921 -0.1651) (xy -0.2921 -0.1651)) (layer F.Fab) (width 0)) + (fp_line (start 11.43 -0.508) (end 11.43 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 8.89 -0.508) (end 8.89 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 6.35 -0.508) (end 6.35 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.81 -0.508) (end 3.81 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.27 -0.508) (end 1.27 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start -1.27 0.762) (end -1.27 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.635 1.397) (end -1.27 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.635 1.397) (end -0.635 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.27 0.762) (end 0.635 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.905 1.397) (end 1.27 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.175 1.397) (end 1.905 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.81 0.762) (end 3.175 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.445 1.397) (end 3.81 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 5.715 1.397) (end 4.445 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 6.35 0.762) (end 5.715 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 6.985 1.397) (end 6.35 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 8.255 1.397) (end 6.985 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 8.89 0.762) (end 8.255 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 9.525 1.397) (end 8.89 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 10.795 1.397) (end 9.525 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 11.43 0.762) (end 10.795 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 12.065 1.397) (end 11.43 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 13.335 1.397) (end 12.065 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 13.97 0.762) (end 13.335 1.397) (layer F.SilkS) (width 0.2032)) + (fp_line (start 13.97 -0.508) (end 13.97 0.762) (layer F.SilkS) (width 0.2032)) + (fp_line (start 13.335 -1.143) (end 13.97 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 12.065 -1.143) (end 13.335 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 11.43 -0.508) (end 12.065 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 10.795 -1.143) (end 11.43 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 9.525 -1.143) (end 10.795 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 8.89 -0.508) (end 9.525 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 8.255 -1.143) (end 8.89 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 6.985 -1.143) (end 8.255 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 6.35 -0.508) (end 6.985 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 5.715 -1.143) (end 6.35 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.445 -1.143) (end 5.715 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.81 -0.508) (end 4.445 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.175 -1.143) (end 3.81 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.905 -1.143) (end 3.175 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.27 -0.508) (end 1.905 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.635 -1.143) (end 1.27 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.635 -1.143) (end 0.635 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start -1.27 -0.508) (end -0.635 -1.143) (layer F.SilkS) (width 0.2032)) + (pad 6 thru_hole circle (at 12.7 0.254) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 64 "Net-(J1-Pad6)") (solder_mask_margin 0.1016)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 65 "Net-(J1-Pad5)") (solder_mask_margin 0.1016)) + (pad 4 thru_hole circle (at 7.62 0.254) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 66 "Net-(J1-Pad4)") (solder_mask_margin 0.1016)) + (pad 3 thru_hole circle (at 5.08 0) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 67 "Net-(J1-Pad3)") (solder_mask_margin 0.1016)) + (pad 2 thru_hole circle (at 2.54 0.254) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 68 "Net-(J1-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 thru_hole circle (at 0 0) (size 1.8796 1.8796) (drill 1.016) (layers *.Cu *.Mask) + (net 69 "Net-(J1-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB48) + (at 220.0011 73.0036 90) + (path /6303E79D/D47120D7) + (fp_text reference L1 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 64 "Net-(J1-Pad6)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 9 SWO) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB52) + (at 217.0011 73.0036 90) + (path /6303E79D/9AC71C44) + (fp_text reference L2 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 65 "Net-(J1-Pad5)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 6 RESET) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB5C) + (at 214.5011 73.0036 90) + (path /6303E79D/E9E9B7BD) + (fp_text reference L3 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 66 "Net-(J1-Pad4)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 7 SWDIO) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB66) + (at 212.0011 73.0036 90) + (path /6303E79D/C1710F1F) + (fp_text reference L6 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 67 "Net-(J1-Pad3)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB70) + (at 209.5011 73.0036 90) + (path /6303E79D/9601F5AB) + (fp_text reference L7 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 68 "Net-(J1-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 8 SWCLK) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:L0805 (layer Top) (tedit 0) (tstamp 6303CB7A) + (at 207.0011 73.0036 90) + (path /6303E79D/23DB1BBD) + (fp_text reference L8 (at -1.905 -1.143 90) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032 90) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (pad 2 smd roundrect (at 0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 69 "Net-(J1-Pad1)") (solder_mask_margin 0.1016)) + (pad 1 smd roundrect (at -0.889 0 90) (size 1.016 1.397) (layers Top F.Paste F.Mask) (roundrect_rratio 0.125) + (net 3 +3V3) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303CB84) + (at 213.5011 82.5036 180) + (descr RESISTOR

) + (path /6303E79D/EFC0BE74) + (fp_text reference R1 (at -1.135 -1.27) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 330 (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 135 "Net-(HB1-PadC)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SML0805 (layer Top) (tedit 0) (tstamp 6303CB92) + (at 207.5011 82.5036 180) + (descr "SML0805-2CW-TR (0805 PROFILE) COOL WHITE

\nSource: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf") + (path /6303E79D/D302D039) + (fp_text reference HB1 (at -1.25 2.5) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value OSR50805C1E (at -1.5 2) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_circle (center -0.275 -0.4) (end -0.2125 -0.4) (layer F.SilkS) (width 0.125)) + (fp_line (start -0.025 0.175) (end -0.175 0.025) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0.15 0) (end -0.025 0.175) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0 -0.15) (end 0.15 0) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.175 0.025) (end 0 -0.15) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.95 -0.55) (end -0.95 0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 -0.55) (end -0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 0.55) (end 0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.95 0.55) (end 0.95 0.55) (layer F.Fab) (width 0.1016)) + (pad A smd rect (at 1.05 0 180) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 12 HEARTBEAT_LED) (solder_mask_margin 0.1016)) + (pad C smd rect (at -1.05 0 180) (size 1.2 1.2) (layers Top F.Paste F.Mask) + (net 135 "Net-(HB1-PadC)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303CBA0) + (at 195.5011 114.0036) + (descr CAPACITOR

) + (path /6303E79D/AEC71D01) + (fp_text reference C2 (at -1.02 2.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 6 RESET) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303CBAE) + (at 195.5011 111.0036) + (descr RESISTOR

) + (path /6303E79D/ABABC248) + (fp_text reference R3 (at 2.115 0.23) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 6 RESET) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:2X20_2MM (layer Top) (tedit 0) (tstamp 6303CBBC) + (at 112.0011 141.0036) + (descr "PIN HEADER") + (path /6303EA23/5503CD28) + (fp_text reference MAINB1 (at -5.195 1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value PINHD-2X20_2MM (at -1.27 3.175) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start 20 1.7) (end 41.55 1.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.55 1.7) (end 18 1.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 41.55 -3.7) (end 41.55 1.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.55 -3.7) (end 41.55 -3.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.55 1.7) (end -3.55 -3.7) (layer F.SilkS) (width 0.127)) + (pad 40 thru_hole circle (at 38 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 70 /SB_HEADERS/N$63) (solder_mask_margin 0.1016)) + (pad 39 thru_hole circle (at 38 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 71 /SB_HEADERS/N$88) (solder_mask_margin 0.1016)) + (pad 38 thru_hole circle (at 36 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 72 /SB_HEADERS/N$62) (solder_mask_margin 0.1016)) + (pad 37 thru_hole circle (at 36 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 73 /SB_HEADERS/N$87) (solder_mask_margin 0.1016)) + (pad 36 thru_hole circle (at 34 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 74 /SB_HEADERS/SOMESIGNAL) (solder_mask_margin 0.1016)) + (pad 35 thru_hole circle (at 34 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 75 /SB_HEADERS/N$86) (solder_mask_margin 0.1016)) + (pad 34 thru_hole circle (at 32 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 33 thru_hole circle (at 32 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 32 thru_hole circle (at 30 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 76 /SB_HEADERS/ADC_UNKNOWN) (solder_mask_margin 0.1016)) + (pad 31 thru_hole circle (at 30 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 77 /SB_HEADERS/VARISTOR_SENSE_5V) (solder_mask_margin 0.1016)) + (pad 30 thru_hole circle (at 28 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 78 /SB_HEADERS/VDCBUS_5V) (solder_mask_margin 0.1016)) + (pad 29 thru_hole circle (at 28 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 79 /SB_HEADERS/TEMPHEAT_5V) (solder_mask_margin 0.1016)) + (pad 28 thru_hole circle (at 26 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 80 /SB_HEADERS/TRAFO_5V) (solder_mask_margin 0.1016)) + (pad 27 thru_hole circle (at 26 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 81 /SB_HEADERS/CURSENS_5V) (solder_mask_margin 0.1016)) + (pad 26 thru_hole circle (at 24 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 25 thru_hole circle (at 24 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 24 thru_hole circle (at 22 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 82 /SB_HEADERS/GRIDRELAY_1_5V) (solder_mask_margin 0.1016)) + (pad 23 thru_hole circle (at 22 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 83 /SB_HEADERS/RELAY1_CHECK_5V) (solder_mask_margin 0.1016)) + (pad 22 thru_hole circle (at 20 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 84 /SB_HEADERS/RELAY0_CHECK_5V) (solder_mask_margin 0.1016)) + (pad 21 thru_hole circle (at 20 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 85 /SB_HEADERS/GRIDRELAY_0_5V) (solder_mask_margin 0.1016)) + (pad 20 thru_hole circle (at 18 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 86 /SB_HEADERS/N$53) (solder_mask_margin 0.1016)) + (pad 19 thru_hole circle (at 18 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 87 /SB_HEADERS/BRIDGES_SHUTDOWN_5V) (solder_mask_margin 0.1016)) + (pad 18 thru_hole circle (at 16 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + (pad 17 thru_hole circle (at 16 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 16 thru_hole circle (at 14 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 88 /SB_HEADERS/BRIDGE1_LIN_5V) (solder_mask_margin 0.1016)) + (pad 15 thru_hole circle (at 14 0) (size 1.308 1.308) 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thru_hole oval (at -21.59 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 93 /SB_HEADERS/VSUP3) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -24.13 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 94 "Net-(JP6-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:1X07 (layer Top) (tedit 0) (tstamp 6303CE44) + (at 79.6011 100.0536) + (descr "PIN HEADER") + (path /6303EA23/ADC4B3B7) + (fp_text reference JP7 (at -8.9662 -1.8288) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value PINHD-1X7 (at -8.89 3.175) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 7.366 0.254) (xy 7.874 0.254) (xy 7.874 -0.254) (xy 7.366 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -7.874 0.254) (xy -7.366 0.254) (xy -7.366 -0.254) (xy -7.874 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.334 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GND) (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 14 RS485_RXENA) (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 2 RS485_TX) (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 110 /SB_HEADERS/RS485_RX_5V) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 112 /SB_HEADERS/NC6) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:1X07 (layer Top) (tedit 0) (tstamp 6303CE87) + (at 79.6011 90.2036) + (descr "PIN HEADER") + (path /6303EA23/357D3C8D) + (fp_text reference JP8 (at -8.9662 -1.8288) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value PINHD-1X7 (at -8.89 3.175) (layer F.Fab) + (effects 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F.SilkS) (width 0.1524)) + (fp_line (start 6.35 -0.635) (end 6.35 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 -1.27) (end 6.35 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 -1.27) (end 5.715 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -0.635) (end 4.445 -1.27) (layer F.SilkS) (width 0.1524)) + (pad 7 thru_hole oval (at 7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 22 LCD_D6) (solder_mask_margin 0.1016)) + (pad 6 thru_hole oval (at 5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 25 LCD_D4) (solder_mask_margin 0.1016)) + (pad 5 thru_hole oval (at 2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 24 LCD_SWA) (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 19 LCD_RS) (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 18 LCD_ENA) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:1X07 (layer Top) (tedit 0) (tstamp 6303CF81) + (at 147.1011 70.0536) + (descr "PIN HEADER") + (path /6303EA23/196A7625) + (fp_text reference JP12 (at -8.9662 -1.8288) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value PINHD-1X7 (at -8.89 3.175) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 7.366 0.254) (xy 7.874 0.254) (xy 7.874 -0.254) (xy 7.366 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -7.874 0.254) (xy -7.366 0.254) (xy -7.366 -0.254) (xy -7.874 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.334 0.254) (xy -4.826 0.254) (xy -4.826 -0.254) (xy -5.334 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 0.254) (xy -2.286 0.254) (xy -2.286 -0.254) (xy -2.794 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 0.254) (xy 0.254 0.254) (xy 0.254 -0.254) (xy -0.254 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.286 0.254) (xy 2.794 0.254) (xy 2.794 -0.254) (xy 2.286 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.826 0.254) (xy 5.334 0.254) (xy 5.334 -0.254) (xy 4.826 -0.254)) (layer F.Fab) (width 0)) + (fp_line (start 8.255 1.27) (end 6.985 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 0.635) (end 6.985 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 -1.27) (end 6.35 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.89 0.635) (end 8.255 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.89 -0.635) (end 8.89 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.255 -1.27) (end 8.89 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 -1.27) (end 8.255 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 1.27) (end -8.255 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.89 0.635) (end -8.255 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.255 -1.27) (end -8.89 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.89 -0.635) (end -8.89 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 1.27) (end -6.35 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 1.27) (end -5.715 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 0.635) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -0.635) (end -3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 -1.27) (end -3.81 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 -1.27) (end -4.445 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 -0.635) (end -5.715 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 0.635) (end -6.985 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 -0.635) (end -6.35 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 -1.27) (end -6.35 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.255 -1.27) (end -6.985 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 1.27) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.635) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -1.27) (end -1.27 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 1.27) (end -3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 1.27) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.635) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -0.635) (end -1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -1.27) (end -1.27 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -1.27) (end -1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -0.635) (end -3.175 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 1.27) (end 1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 1.27) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 0.635) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -0.635) (end 3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -1.27) (end 3.81 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 3.175 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -0.635) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.635) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -0.635) (end 1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -1.27) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 1.27) (end 3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 1.27) (end 4.445 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 0.635) (end 5.715 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 -0.635) (end 6.35 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 -1.27) (end 6.35 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 -1.27) (end 5.715 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -0.635) (end 4.445 -1.27) (layer F.SilkS) (width 0.1524)) + (pad 7 thru_hole oval (at 7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 21 LCD_D7) (solder_mask_margin 0.1016)) + (pad 6 thru_hole oval (at 5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 17 LCD_D5) (solder_mask_margin 0.1016)) + (pad 5 thru_hole oval (at 2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 16 LCD_SWB) (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 113 /SB_HEADERS/LCD_MIC_5V) (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 20 LCD_BACKL) (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 23 LCD_RW) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:LED5MM (layer Top) (tedit 0) (tstamp 6303CFC4) + (at 212.5011 93.5036) + (descr "LED

\n5 mm, round") + (path /6303EA23/3A507120) + (fp_text reference OK1 (at 3.175 1.4666) (layer F.SilkS) + (effects (font (size 2.85 2.85) (thickness 0.342)) (justify left bottom)) + ) + (fp_text value LED5MM (at 3.2004 1.8034) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_circle (center 0 0) (end 2.54 0) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end 0 2.159) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -2.159 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.651) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.651 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.143) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.143 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 2.54 1.905) (angle 286.260205) (layer F.SilkS) (width 0.254)) + (fp_line (start 2.54 1.905) (end 2.54 -1.905) (layer F.SilkS) (width 0.2032)) + (pad K thru_hole circle (at 1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad A thru_hole circle (at -1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 136 "Net-(OK1-PadA)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:LED5MM (layer Top) (tedit 0) (tstamp 6303CFD2) + (at 212.5011 109.0036) + (descr "LED

\n5 mm, round") + (path /6303EA23/E909F65F) + (fp_text reference ERR1 (at 3.425 1.4666) (layer F.SilkS) + (effects (font (size 2.85 2.85) (thickness 0.342)) (justify left bottom)) + ) + (fp_text value LED5MM (at 3.2004 1.8034) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_circle (center 0 0) (end 2.54 0) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end 0 2.159) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -2.159 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.651) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.651 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.143) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.143 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 2.54 1.905) (angle 286.260205) (layer F.SilkS) (width 0.254)) + (fp_line (start 2.54 1.905) (end 2.54 -1.905) (layer F.SilkS) (width 0.2032)) + (pad K thru_hole circle (at 1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad A thru_hole circle (at -1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 137 "Net-(ERR1-PadA)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:LED5MM (layer Top) (tedit 0) (tstamp 6303CFE0) + (at 212.5011 123.5036) + (descr "LED

\n5 mm, round") + (path /6303EA23/16F216A7) + (fp_text reference WARN1 (at 3.425 1.2166) (layer F.SilkS) + (effects (font (size 2.85 2.85) (thickness 0.342)) (justify left bottom)) + ) + (fp_text value LED5MM (at 3.2004 1.8034) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_circle (center 0 0) (end 2.54 0) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end 0 2.159) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -2.159 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.651) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.651 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.143) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.143 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 2.54 1.905) (angle 286.260205) (layer F.SilkS) (width 0.254)) + (fp_line (start 2.54 1.905) (end 2.54 -1.905) (layer F.SilkS) (width 0.2032)) + (pad K thru_hole circle (at 1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad A thru_hole circle (at -1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 114 "Net-(R6-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303CFEE) + (at 212.5011 88.5036) + (descr RESISTOR

) + (path /6303EA23/0138DFE6) + (fp_text reference R4 (at -0.635 -1.27) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 330 (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 136 "Net-(OK1-PadA)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 28 LED_GREEN) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303CFFC) + (at 212.0011 103.5036 270) + (descr RESISTOR

) + (path /6303EA23/71430D2B) + (fp_text reference R5 (at -2.365 -0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 330 (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 137 "Net-(ERR1-PadA)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 27 LED_RED) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D00A) + (at 212.5011 118.5036) + (descr RESISTOR

) + (path /6303EA23/A0406511) + (fp_text reference R6 (at -0.635 -1.27) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 330 (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 114 "Net-(R6-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 26 LED_YELLOW) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SB-PCB (layer Top) (tedit 0) (tstamp 6303D018) + (at 68.5011 147.0036) + (path /6303EA23/89E33A62) + (fp_text reference U$1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_text value SB_LOGIC_PCB (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_circle (center 43.5 -6) (end 44 -6) (layer F.Fab) (width 0.127)) + (fp_circle (center 71 -71) (end 71.5 -71) (layer F.Fab) (width 0.127)) + (fp_circle (center 3.5 -50.75) (end 4 -50.75) (layer F.Fab) (width 0.127)) + (fp_circle (center 5 -16) (end 5.5 -16) (layer F.Fab) (width 0.127)) + (fp_text user MOUNT (at 71 -63) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user MOUNT (at 121 -7) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user MOUNT (at 21 -7) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 51 -71) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 51 -25) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 113 -25) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 113 -71) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LED (at 148 -23) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LED (at 148 -38) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LED (at 148 -53) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_circle (center 144 -53.5) (end 146.5 -53.5) (layer F.Fab) (width 0.127)) + (fp_circle (center 144 -38.5) (end 146.5 -38.5) (layer F.Fab) (width 0.127)) + (fp_circle (center 144 -23.5) (end 146.5 -23.5) (layer F.Fab) (width 0.127)) + (fp_arc (start 156 -4) (end 156 0) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 4 0) (end 156 0) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 4 -4) (end 0 -4) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 0 -80) (end 0 -4) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 4 -80) (end 4 -84) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 156 -84) (end 4 -84) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 156 -80) (end 160 -80) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 160 -4) (end 160 -80) (layer Edge.Cuts) (width 0.05)) + (pad "" np_thru_hole circle (at 80 -63.5) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 48 -72) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 48 -26) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 110 -72) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 110 -26) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 130 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 95 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 30 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + ) + + (module SB_LOGICBOARD_V01:SO20W (layer Top) (tedit 0) (tstamp 6303D03C) + (at 132.0011 120.5036 90) + (descr "Wide Small Outline package 300 mil") + (path /6303EA23/509C8314) + (fp_text reference IC2 (at -3.825 1.358 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value "74HCT244DW OR 74VHCT541A" (at -3.81 1.778 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy 5.461 5.334) (xy 5.969 5.334) (xy 5.969 3.8608) (xy 5.461 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 5.334) (xy 4.699 5.334) (xy 4.699 3.8608) (xy 4.191 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 3.8608) (xy 5.969 3.8608) (xy 5.969 3.7338) (xy 5.461 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 3.8608) (xy 4.699 3.8608) (xy 4.699 3.7338) (xy 4.191 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.8608) (xy 5.969 -3.8608) (xy 5.969 -5.334) (xy 5.461 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.8608) (xy 4.699 -3.8608) (xy 4.699 -5.334) (xy 4.191 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.7338) (xy 5.969 -3.7338) (xy 5.969 -3.8608) (xy 5.461 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.7338) (xy 4.699 -3.7338) (xy 4.699 -3.8608) (xy 4.191 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.8608) (xy 3.429 -3.8608) (xy 3.429 -5.334) (xy 2.921 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.7338) (xy 3.429 -3.7338) (xy 3.429 -3.8608) (xy 2.921 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.8608) (xy 2.159 -3.8608) (xy 2.159 -5.334) (xy 1.651 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.7338) (xy 2.159 -3.7338) (xy 2.159 -3.8608) (xy 1.651 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.8608) (xy 0.889 -3.8608) (xy 0.889 -5.334) (xy 0.381 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.7338) (xy 0.889 -3.7338) (xy 0.889 -3.8608) (xy 0.381 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.8608) (xy -0.381 -3.8608) (xy -0.381 -5.334) (xy -0.889 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.7338) (xy -0.381 -3.7338) (xy -0.381 -3.8608) (xy -0.889 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.8608) (xy -1.651 -3.8608) (xy -1.651 -5.334) (xy -2.159 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.7338) (xy -1.651 -3.7338) (xy -1.651 -3.8608) (xy -2.159 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.8608) (xy -2.921 -3.8608) (xy -2.921 -5.334) (xy -3.429 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.7338) (xy -2.921 -3.7338) (xy -2.921 -3.8608) (xy -3.429 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.8608) (xy -4.191 -3.8608) (xy -4.191 -5.334) (xy -4.699 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.7338) (xy -4.191 -3.7338) (xy -4.191 -3.8608) (xy -4.699 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.7338) (xy -5.461 -3.7338) (xy -5.461 -3.8608) (xy -5.969 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.8608) (xy -5.461 -3.8608) (xy -5.461 -5.334) (xy -5.969 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 5.334) (xy 3.429 5.334) (xy 3.429 3.8608) (xy 2.921 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 3.8608) (xy 3.429 3.8608) (xy 3.429 3.7338) (xy 2.921 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 5.334) (xy 2.159 5.334) (xy 2.159 3.8608) (xy 1.651 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 3.8608) (xy 2.159 3.8608) (xy 2.159 3.7338) (xy 1.651 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 5.334) (xy 0.889 5.334) (xy 0.889 3.8608) (xy 0.381 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 3.8608) (xy 0.889 3.8608) (xy 0.889 3.7338) (xy 0.381 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 3.8608) (xy -0.381 3.8608) (xy -0.381 3.7338) (xy -0.889 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 5.334) (xy -0.381 5.334) (xy -0.381 3.8608) (xy -0.889 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 5.334) (xy -1.651 5.334) (xy -1.651 3.8608) (xy -2.159 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 3.8608) (xy -1.651 3.8608) (xy -1.651 3.7338) (xy -2.159 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 5.334) (xy -2.921 5.334) (xy -2.921 3.8608) (xy -3.429 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 3.8608) (xy -2.921 3.8608) (xy -2.921 3.7338) (xy -3.429 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 5.334) (xy -4.191 5.334) (xy -4.191 3.8608) (xy -4.699 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 3.8608) (xy -4.191 3.8608) (xy -4.191 3.7338) (xy -4.699 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 5.334) (xy -5.461 5.334) (xy -5.461 3.8608) (xy -5.969 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 3.8608) (xy -5.461 3.8608) (xy -5.461 3.7338) (xy -5.969 3.7338)) (layer F.Fab) (width 0)) + (fp_arc (start -6.5024 0) (end -6.5024 -1.27) (angle 180) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.477 3.3782) (end 6.477 3.3782) (layer F.SilkS) (width 0.0508)) + (fp_line (start -6.5024 1.27) (end -6.5024 3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -1.27) (end -6.5024 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -3.3528) (end -6.5024 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.5024 3.3528) (end 6.5024 -3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.1214 3.7338) (end 6.1214 3.7338) (layer F.Fab) (width 0.1524)) + (fp_arc (start -6.1214 3.3528) (end -6.5024 3.3528) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 6.1214 -3.3528) (end 6.1214 -3.7338) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -6.1214 -3.3528) (end -6.5024 -3.3528) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 6.1214 3.3528) (end 6.1214 3.7338) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.1214 -3.7338) (end -6.1214 -3.7338) (layer F.Fab) (width 0.1524)) + (pad 11 smd rect (at 5.715 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 29 BRIDGES_SHUTDOWN) (solder_mask_margin 0.1016)) + (pad 12 smd rect (at 4.445 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 91 /SB_HEADERS/BRIDGE0_HIN_5V) (solder_mask_margin 0.1016)) + (pad 10 smd rect (at 5.715 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 9 smd rect (at 4.445 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 87 /SB_HEADERS/BRIDGES_SHUTDOWN_5V) (solder_mask_margin 0.1016)) + (pad 20 smd rect (at -5.715 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + (pad 19 smd rect (at -4.445 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 18 smd rect (at -3.175 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 88 /SB_HEADERS/BRIDGE1_LIN_5V) (solder_mask_margin 0.1016)) + (pad 17 smd rect (at -1.905 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 16 smd rect (at -0.635 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 89 /SB_HEADERS/BRIDGE1_HIN_5V) (solder_mask_margin 0.1016)) + (pad 15 smd rect (at 0.635 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 31 GRIDRELAY_1) (solder_mask_margin 0.1016)) + (pad 14 smd rect (at 1.905 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 90 /SB_HEADERS/BRIDGE0_LIN_5V) (solder_mask_margin 0.1016)) + (pad 13 smd rect (at 3.175 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 30 GRIDRELAY_0) (solder_mask_margin 0.1016)) + (pad 8 smd rect (at 3.175 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 47 BRIDGE1_HIN) (solder_mask_margin 0.1016)) + (pad 7 smd rect (at 1.905 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 85 /SB_HEADERS/GRIDRELAY_0_5V) (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 48 BRIDGE0_HIN) (solder_mask_margin 0.1016)) + (pad 5 smd rect (at -0.635 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 82 /SB_HEADERS/GRIDRELAY_1_5V) (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -1.905 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 4 BRIDGE1_LIN) (solder_mask_margin 0.1016)) + (pad 3 smd rect (at -3.175 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 115 /SB_HEADERS/N$60) (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -4.445 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 13 BRIDGE0_LIN) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -5.715 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D087) + (at 124.2511 126.5036 90) + (descr CAPACITOR

) + (path /6303EA23/EE7D9419) + (fp_text reference C3 (at 0.73 -1.02 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:W237-4 (layer Top) (tedit 0) (tstamp 6303D095) + (at 80.0011 141.0036) + (descr "WAGO SCREW CLAMP") + (path /6303EA23/8679BB61) + (fp_text reference X1 (at -8.7446 7.4422) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value W237-4 (at -7.6524 5.0292) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_text user 4 (at 5.4286 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 3 (at 0.4756 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 2 (at -4.579 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 1 (at -9.532 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_circle (center 7.5114 -2.2098) (end 8.0194 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center 7.5114 1.27) (end 9.01 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center 2.5076 -2.2098) (end 3.0156 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center 2.5076 1.27) (end 4.0062 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center -2.4962 -2.2098) (end -1.9882 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center -2.4962 1.27) (end -0.9976 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center -7.5 -2.2098) (end -6.992 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center -7.5 1.27) (end -6.0014 1.27) (layer F.Fab) (width 0.1524)) + (fp_line (start 6.622 3.073) (end 8.4 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.619 3.073) (end 3.397 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start -3.385 3.073) (end -1.607 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start 10.001 -3.531) (end 10.001 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 -3.531) (end -9.989 -3.734) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 -3.531) (end 10.001 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 3.073) (end 10.001 5.461) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 3.073) (end -9.989 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.4 3.073) (end 10.001 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.397 3.073) (end 6.622 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.607 3.073) (end 1.619 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.611 3.073) (end -3.385 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.389 3.073) (end -6.611 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start -9.989 3.073) (end -8.389 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 5.461) (end -9.989 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 -3.734) (end -9.989 -3.734) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 -3.734) (end 10.001 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 5.461) (end 10.001 5.461) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.495 2.261) (end 8.477 0.254) (layer F.Fab) (width 0.254)) + (fp_line (start 1.517 2.286) (end 3.524 0.279) (layer F.Fab) (width 0.254)) + (fp_line (start -3.512 2.261) (end -1.531 0.254) (layer F.Fab) (width 0.254)) + (fp_line (start -8.491 2.286) (end -6.484 0.279) (layer F.Fab) (width 0.254)) + (pad 4 thru_hole oval (at 7.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (net 116 "Net-(X1-Pad4)") (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at 2.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (net 98 /SB_HEADERS/RS485_GND) (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -2.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (net 99 /SB_HEADERS/RS485_B) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -7.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (net 101 /SB_HEADERS/RS485_A) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D0BE) + (at 91.5011 135.0036 270) + (descr JUMPER) + (path /6303EA23/9B8C9E68) + (fp_text reference JP13 (at -1.651 2.54) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value JP1E (at 2.921 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27 270) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 102 /SB_HEADERS/120OHMTOA) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27 270) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 99 /SB_HEADERS/RS485_B) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D0D3) + (at 75.0011 105.5036 90) + (descr RESISTOR

) + (path /6303EA23/6C198247) + (fp_text reference R7 (at -0.635 -1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 110 /SB_HEADERS/RS485_RX_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 44 RS485_RX) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D0E1) + (at 81.2511 106.5036 90) + (descr RESISTOR

) + (path /6303EA23/D04B934E) + (fp_text reference R8 (at -0.885 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 44 RS485_RX) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SO08 (layer Top) (tedit 0) (tstamp 6303D0EF) + (at 171.5011 122.0036) + (descr "Small Outline Package 8
\nNS Package M08A") + (path /6303EA23/B686635D) + (fp_text reference IC3 (at 2.667 -1.905 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value LM358D (at 3.937 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -2.15 -2) (xy -1.66 -2) (xy -1.66 -3.1) (xy -2.15 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 -2) (xy -0.39 -2) (xy -0.39 -3.1) (xy -0.88 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 -2) (xy 0.88 -2) (xy 0.88 -3.1) (xy 0.39 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 -2) (xy 2.15 -2) (xy 2.15 -3.1) (xy 1.66 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 3.1) (xy 2.15 3.1) (xy 2.15 2) (xy 1.66 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 3.1) (xy 0.88 3.1) (xy 0.88 2) (xy 0.39 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 3.1) (xy -0.39 3.1) (xy -0.39 2) (xy -0.88 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.15 3.1) (xy -1.66 3.1) (xy -1.66 2) (xy -2.15 2)) (layer F.Fab) (width 0)) + (fp_line (start 2.4 1.4) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 -1.9) (end 2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.4) (end -2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.9) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.9) (end -2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.4) (end 2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 -1.9) (end 2.4 1.4) (layer F.Fab) (width 0.2032)) + (pad 5 smd rect (at 1.905 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 117 "Net-(C6-Pad1)") (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 34 VCC/2) (solder_mask_margin 0.1016)) + (pad 8 smd rect (at -1.905 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 32 +12V) (solder_mask_margin 0.1016)) + (pad 4 smd rect (at 1.905 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 33 -12V) (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 0.635 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 118 "Net-(IC3-Pad3)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -1.905 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 35 TRAFO) (solder_mask_margin 0.1016)) + (pad 7 smd rect (at -0.635 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 34 VCC/2) (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -0.635 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 119 "Net-(IC3-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D109) + (at 169.0011 115.0036 180) + (descr RESISTOR

) + (path /6303EA23/EE576B13) + (fp_text reference R9 (at -0.885 -1.02) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 3 +3V3) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 117 "Net-(C6-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D117) + (at 173.5011 115.0036 180) + (descr RESISTOR

) + (path /6303EA23/0C1A74F8) + (fp_text reference R10 (at -4.635 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 117 "Net-(C6-Pad1)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D125) + (at 167.0011 120.5036 270) + (descr CAPACITOR

) + (path /6303EA23/FC383928) + (fp_text reference C4 (at -1.02 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 33 -12V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 32 +12V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D133) + (at 175.0011 128.5036 90) + (descr RESISTOR

) + (path /6303EA23/7F05DB35) + (fp_text reference R11 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 33k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 118 "Net-(IC3-Pad3)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D141) + (at 167.5011 126.5036 270) + (descr RESISTOR

) + (path /6303EA23/F9C269AE) + (fp_text reference R12 (at 1.615 -0.02 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 35 TRAFO) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 118 "Net-(IC3-Pad3)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D14F) + (at 170.0011 129.0036 90) + (descr RESISTOR

) + (path /6303EA23/1F1C9F4C) + (fp_text reference R13 (at -4.385 -0.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 33k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 119 "Net-(IC3-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 80 /SB_HEADERS/TRAFO_5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D15D) + (at 172.5011 129.0036 270) + (descr RESISTOR

) + (path /6303EA23/5915D5B8) + (fp_text reference R14 (at 2.115 1.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 34 VCC/2) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 119 "Net-(IC3-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D16B) + (at 173.5011 112.5036) + (descr CAPACITOR

) + (path /6303EA23/7B9FEF3C) + (fp_text reference C6 (at -1.27 -1.02) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 117 "Net-(C6-Pad1)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SO08 (layer Top) (tedit 0) (tstamp 6303D179) + (at 159.0011 120.0036) + (descr "Small Outline Package 8
\nNS Package M08A") + (path /6303EA23/FA55F29D) + (fp_text reference IC4 (at 2.345 0.083) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value LM358D (at 3.937 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -2.15 -2) (xy -1.66 -2) (xy -1.66 -3.1) (xy -2.15 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 -2) (xy -0.39 -2) (xy -0.39 -3.1) (xy -0.88 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 -2) (xy 0.88 -2) (xy 0.88 -3.1) (xy 0.39 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 -2) (xy 2.15 -2) (xy 2.15 -3.1) (xy 1.66 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 3.1) (xy 2.15 3.1) (xy 2.15 2) (xy 1.66 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 3.1) (xy 0.88 3.1) (xy 0.88 2) (xy 0.39 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 3.1) (xy -0.39 3.1) (xy -0.39 2) (xy -0.88 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.15 3.1) (xy -1.66 3.1) (xy -1.66 2) (xy -2.15 2)) (layer F.Fab) (width 0)) + (fp_line (start 2.4 1.4) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 -1.9) (end 2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.4) (end -2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.9) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.9) (end -2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.4) (end 2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 -1.9) (end 2.4 1.4) (layer F.Fab) (width 0.2032)) + (pad 5 smd rect (at 1.905 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 120 "Net-(IC4-Pad5)") (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 121 "Net-(IC4-Pad6)") (solder_mask_margin 0.1016)) + (pad 8 smd rect (at -1.905 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 32 +12V) (solder_mask_margin 0.1016)) + (pad 4 smd rect (at 1.905 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 33 -12V) (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 0.635 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 122 "Net-(IC4-Pad3)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -1.905 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 36 CURSENS) (solder_mask_margin 0.1016)) + (pad 7 smd rect (at -0.635 -2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 45 ADC_IN0) (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -0.635 2.6) (size 0.6 2.2) (layers Top F.Paste F.Mask) + (net 123 "Net-(IC4-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D193) + (at 163.0011 123.5036 270) + (descr RESISTOR

) + (path /6303EA23/B3D49AF4) + (fp_text reference R15 (at -1.385 -1.02 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 39k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 122 "Net-(IC4-Pad3)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1A1) + (at 154.5011 121.5036 270) + (descr RESISTOR

) + (path /6303EA23/AC3F9421) + (fp_text reference R17 (at -1.135 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 36 CURSENS) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 122 "Net-(IC4-Pad3)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1AF) + (at 156.5011 127.5036) + (descr RESISTOR

) + (path /6303EA23/63FAAA44) + (fp_text reference R18 (at -1.385 -1.02) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 39k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 123 "Net-(IC4-Pad2)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 81 /SB_HEADERS/CURSENS_5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1BD) + (at 161.0011 127.5036) + (descr RESISTOR

) + (path /6303EA23/6A7A1984) + (fp_text reference R20 (at -1.135 -1.02) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 34 VCC/2) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 123 "Net-(IC4-Pad2)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D1CB) + (at 154.5011 117.0036 270) + (descr CAPACITOR

) + (path /6303EA23/3E93E688) + (fp_text reference C7 (at -0.27 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 33 -12V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 32 +12V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1D9) + (at 184.5011 139.5036 270) + (descr RESISTOR

) + (path /6303EA23/2694F2DF) + (fp_text reference R22 (at -0.635 -1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 79 /SB_HEADERS/TEMPHEAT_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 37 TEMPHEAT) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1E7) + (at 184.5011 135.5036 270) + (descr RESISTOR

) + (path /6303EA23/91DF45D8) + (fp_text reference R24 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 37 TEMPHEAT) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D1F5) + (at 190.5011 137.0036 270) + (descr RESISTOR

) + (path /6303EA23/4BEDBC02) + (fp_text reference R25 (at -0.635 -1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 78 /SB_HEADERS/VDCBUS_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 38 VDCBUS) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D203) + (at 192.0011 131.2536 270) + (descr RESISTOR

) + (path /6303EA23/B450C1B9) + (fp_text reference R27 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 38 VDCBUS) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D211) + (at 175.5011 138.5036 270) + (descr RESISTOR

) + (path /6303EA23/29F9BCC2) + (fp_text reference R28 (at -1.385 -1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 77 /SB_HEADERS/VARISTOR_SENSE_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 39 VARISTOR_SENSE) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D21F) + (at 175.5011 134.5036 270) + (descr RESISTOR

) + (path /6303EA23/2263213C) + (fp_text reference R29 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 39 VARISTOR_SENSE) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D22D) + (at 187.5011 135.5036 90) + (descr CAPACITOR

) + (path /6303EA23/5829BE1F) + (fp_text reference C8 (at 1.98 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 37 TEMPHEAT) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D23B) + (at 196.0011 131.2536 90) + (descr CAPACITOR

) + (path /6303EA23/0A27D8A0) + (fp_text reference C9 (at -1.52 -1.02 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 38 VDCBUS) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D249) + (at 179.0011 134.5036 90) + (descr CAPACITOR

) + (path /6303EA23/AB492345) + (fp_text reference C11 (at -2.77 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 39 VARISTOR_SENSE) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D257) + (at 199.7511 131.5036 270) + (descr RESISTOR

) + (path /6303EA23/2E51F248) + (fp_text reference R30 (at -4.885 0.23 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 83 /SB_HEADERS/RELAY1_CHECK_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 40 RELAY1_CHECK) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D265) + (at 202.7511 129.5036 270) + (descr RESISTOR

) + (path /6303EA23/4B16FDED) + (fp_text reference R32 (at 1.865 0.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 40 RELAY1_CHECK) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D273) + (at 206.0011 129.5036 90) + (descr CAPACITOR

) + (path /6303EA23/BE9088C3) + (fp_text reference C12 (at -1.02 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 40 RELAY1_CHECK) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D281) + (at 205.2511 140.2536 270) + (descr RESISTOR

) + (path /6303EA23/D2F8D55D) + (fp_text reference R33 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 84 /SB_HEADERS/RELAY0_CHECK_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 41 RELAY0_CHECK) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D28F) + (at 205.2511 135.7536 270) + (descr RESISTOR

) + (path /6303EA23/59BAB805) + (fp_text reference R34 (at -1.385 2.23 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 41 RELAY0_CHECK) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 270) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D29D) + (at 208.5011 135.7536 90) + (descr CAPACITOR

) + (path /6303EA23/966E58D5) + (fp_text reference C13 (at -4.52 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 41 RELAY0_CHECK) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2AB) + (at 189.5011 74.0036 90) + (descr RESISTOR

) + (path /6303EA23/DD09D05C) + (fp_text reference R35 (at -1.135 -1.02 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 113 /SB_HEADERS/LCD_MIC_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 42 LCD_MIC) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2B9) + (at 192.0011 78.0036 90) + (descr RESISTOR

) + (path /6303EA23/B26CA373) + (fp_text reference R36 (at -1.385 1.98 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 42 LCD_MIC) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D2C7) + (at 192.0011 74.0036 90) + (descr CAPACITOR

) + (path /6303EA23/53978D3B) + (fp_text reference C1 (at 1.98 0.48 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 42 LCD_MIC) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2D5) + (at 163.0011 115.5036 90) + (descr RESISTOR

) + (path /6303EA23/640072A7) + (fp_text reference R38 (at -0.635 -1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 39k (at -0.635 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 120 "Net-(IC4-Pad5)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 90) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2E3) + (at 159.5011 114.0036 180) + (descr RESISTOR

) + (path /6303EA23/352D39F6) + (fp_text reference R39 (at 1.615 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 45 ADC_IN0) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 120 "Net-(IC4-Pad5)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2F1) + (at 159.5011 111.5036 180) + (descr RESISTOR

) + (path /6303EA23/268917AA) + (fp_text reference R40 (at -2.635 1.98) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 39k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 121 "Net-(IC4-Pad6)") (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 124 /SB_HEADERS/ADC_IN0_5V) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D2FF) + (at 154.7511 111.5036 180) + (descr RESISTOR

) + (path /6303EA23/A2BF284D) + (fp_text reference R41 (at 1.615 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10k (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 34 VCC/2) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 121 "Net-(IC4-Pad6)") (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:SO20W (layer Top) (tedit 0) (tstamp 6303D30D) + (at 115.0011 96.5036 90) + (descr "Wide Small Outline package 300 mil") + (path /6303EA23/E24D3BEC) + (fp_text reference IC6 (at -6.858 3.175) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value "74HCT244DW OR 74VHCT541A" (at -3.81 1.778 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy 5.461 5.334) (xy 5.969 5.334) (xy 5.969 3.8608) (xy 5.461 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 5.334) (xy 4.699 5.334) (xy 4.699 3.8608) (xy 4.191 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 3.8608) (xy 5.969 3.8608) (xy 5.969 3.7338) (xy 5.461 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 3.8608) (xy 4.699 3.8608) (xy 4.699 3.7338) (xy 4.191 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.8608) (xy 5.969 -3.8608) (xy 5.969 -5.334) (xy 5.461 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.8608) (xy 4.699 -3.8608) (xy 4.699 -5.334) (xy 4.191 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.7338) (xy 5.969 -3.7338) (xy 5.969 -3.8608) (xy 5.461 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.7338) (xy 4.699 -3.7338) (xy 4.699 -3.8608) (xy 4.191 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.8608) (xy 3.429 -3.8608) (xy 3.429 -5.334) (xy 2.921 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.7338) (xy 3.429 -3.7338) (xy 3.429 -3.8608) (xy 2.921 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.8608) (xy 2.159 -3.8608) (xy 2.159 -5.334) (xy 1.651 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.7338) (xy 2.159 -3.7338) (xy 2.159 -3.8608) (xy 1.651 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.8608) (xy 0.889 -3.8608) (xy 0.889 -5.334) (xy 0.381 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.7338) (xy 0.889 -3.7338) (xy 0.889 -3.8608) (xy 0.381 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.8608) (xy -0.381 -3.8608) (xy -0.381 -5.334) (xy -0.889 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.7338) (xy -0.381 -3.7338) (xy -0.381 -3.8608) (xy -0.889 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.8608) (xy -1.651 -3.8608) (xy -1.651 -5.334) (xy -2.159 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.7338) (xy -1.651 -3.7338) (xy -1.651 -3.8608) (xy -2.159 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.8608) (xy -2.921 -3.8608) (xy -2.921 -5.334) (xy -3.429 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.7338) (xy -2.921 -3.7338) (xy -2.921 -3.8608) (xy -3.429 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.8608) (xy -4.191 -3.8608) (xy -4.191 -5.334) (xy -4.699 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.7338) (xy -4.191 -3.7338) (xy -4.191 -3.8608) (xy -4.699 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.7338) (xy -5.461 -3.7338) (xy -5.461 -3.8608) (xy -5.969 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.8608) (xy -5.461 -3.8608) (xy -5.461 -5.334) (xy -5.969 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 5.334) (xy 3.429 5.334) (xy 3.429 3.8608) (xy 2.921 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 3.8608) (xy 3.429 3.8608) (xy 3.429 3.7338) (xy 2.921 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 5.334) (xy 2.159 5.334) (xy 2.159 3.8608) (xy 1.651 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 3.8608) (xy 2.159 3.8608) (xy 2.159 3.7338) (xy 1.651 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 5.334) (xy 0.889 5.334) (xy 0.889 3.8608) (xy 0.381 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 3.8608) (xy 0.889 3.8608) (xy 0.889 3.7338) (xy 0.381 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 3.8608) (xy -0.381 3.8608) (xy -0.381 3.7338) (xy -0.889 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 5.334) (xy -0.381 5.334) (xy -0.381 3.8608) (xy -0.889 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 5.334) (xy -1.651 5.334) (xy -1.651 3.8608) (xy -2.159 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 3.8608) (xy -1.651 3.8608) (xy -1.651 3.7338) (xy -2.159 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 5.334) (xy -2.921 5.334) (xy -2.921 3.8608) (xy -3.429 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 3.8608) (xy -2.921 3.8608) (xy -2.921 3.7338) (xy -3.429 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 5.334) (xy -4.191 5.334) (xy -4.191 3.8608) (xy -4.699 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 3.8608) (xy -4.191 3.8608) (xy -4.191 3.7338) (xy -4.699 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 5.334) (xy -5.461 5.334) (xy -5.461 3.8608) (xy -5.969 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 3.8608) (xy -5.461 3.8608) (xy -5.461 3.7338) (xy -5.969 3.7338)) (layer F.Fab) (width 0)) + (fp_arc (start -6.5024 0) (end -6.5024 -1.27) (angle 180) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.477 3.3782) (end 6.477 3.3782) (layer F.SilkS) (width 0.0508)) + (fp_line (start -6.5024 1.27) (end -6.5024 3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -1.27) (end -6.5024 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -3.3528) (end -6.5024 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.5024 3.3528) (end 6.5024 -3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.1214 3.7338) (end 6.1214 3.7338) (layer F.Fab) (width 0.1524)) + (fp_arc (start -6.1214 3.3528) (end -6.5024 3.3528) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 6.1214 -3.3528) (end 6.1214 -3.7338) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -6.1214 -3.3528) (end -6.5024 -3.3528) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 6.1214 3.3528) (end 6.1214 3.7338) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.1214 -3.7338) (end -6.1214 -3.7338) (layer F.Fab) (width 0.1524)) + (pad 11 smd rect (at 5.715 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 12 smd rect (at 4.445 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 125 /SB_HEADERS/IO_OUT3_5V) (solder_mask_margin 0.1016)) + (pad 10 smd rect (at 5.715 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 9 smd rect (at 4.445 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 20 smd rect (at -5.715 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 5 +5V) (solder_mask_margin 0.1016)) + (pad 19 smd rect (at -4.445 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 18 smd rect (at -3.175 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 126 /SB_HEADERS/IO_OUT0_5V) (solder_mask_margin 0.1016)) + (pad 17 smd rect (at -1.905 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 16 smd rect (at -0.635 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 127 /SB_HEADERS/IO_OUT1_5V) (solder_mask_margin 0.1016)) + (pad 15 smd rect (at 0.635 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 14 smd rect (at 1.905 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 128 /SB_HEADERS/IO_OUT2_5V) (solder_mask_margin 0.1016)) + (pad 13 smd rect (at 3.175 -5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 8 smd rect (at 3.175 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 129 /SB_HEADERS/IO_OUT3) (solder_mask_margin 0.1016)) + (pad 7 smd rect (at 1.905 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 130 /SB_HEADERS/IO_OUT2) (solder_mask_margin 0.1016)) + (pad 5 smd rect (at -0.635 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -1.905 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 46 IO_OUT1) (solder_mask_margin 0.1016)) + (pad 3 smd rect (at -3.175 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -4.445 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 11 IO_OUT0) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -5.715 5.0292 90) (size 0.6604 2.032) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D358) + (at 216.7511 138.5036) + (descr RESISTOR

) + (path /6303EA23/AAA0E0FF) + (fp_text reference R46 (at -4.385 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 131 /SB_HEADERS/IO_IN0_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 10 IO_IN0) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D366) + (at 212.7511 141.7536) + (descr RESISTOR

) + (path /6303EA23/04D25D41) + (fp_text reference R47 (at -1.135 2.23) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 10 IO_IN0) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D374) + (at 216.7511 141.7536) + (descr CAPACITOR

) + (path /6303EA23/3995D0BB) + (fp_text reference C15 (at -1.27 2.23) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 10 IO_IN0) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D382) + (at 216.7511 132.0036) + (descr RESISTOR

) + (path /6303EA23/D8F974C6) + (fp_text reference R23 (at -4.385 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 10K (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 132 /SB_HEADERS/ADC_IN1_5V) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 43 ADC_IN1) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:R0805 (layer Top) (tedit 0) (tstamp 6303D390) + (at 216.7511 128.7536 180) + (descr RESISTOR

) + (path /6303EA23/B86A2902) + (fp_text reference R26 (at 1.865 0.73) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 43 ADC_IN1) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:C0805 (layer Top) (tedit 0) (tstamp 6303D39E) + (at 216.7511 135.0036) + (descr CAPACITOR

) + (path /6303EA23/A2277B5B) + (fp_text reference C16 (at -4.52 0.48) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 100n/35v (at -1.27 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (net 43 ADC_IN1) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D3AC) + (at 164.5011 111.5036 90) + (descr JUMPER) + (path /6303EA23/BBFD11B3) + (fp_text reference AIN0 (at 1.71 -0.401 90) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value JP1E (at 2.921 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 124 /SB_HEADERS/ADC_IN0_5V) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D3C1) + (at 221.7511 132.0036 90) + (descr JUMPER) + (path /6303EA23/4861989B) + (fp_text reference JP15 (at -1.651 2.54 180) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value JP1E (at 2.921 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 132 /SB_HEADERS/ADC_IN1_5V) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D3D6) + (at 221.7511 138.5036 90) + (descr JUMPER) + (path /6303EA23/5B0B6750) + (fp_text reference JP16 (at -1.651 2.54 180) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value JP1E (at 2.921 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 131 /SB_HEADERS/IO_IN0_5V) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:1X06 (layer Top) (tedit 0) (tstamp 6303D3EB) + (at 105.0011 93.5036 270) + (descr "PIN HEADER") + (path /6303EA23/2206741E) + (fp_text reference JP17 (at -7.6962 -1.8288 270) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value PINHD-1X6 (at -7.62 3.175 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 6.096 0.254) (xy 6.604 0.254) (xy 6.604 -0.254) (xy 6.096 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -6.604 0.254) (xy -6.096 0.254) (xy -6.096 -0.254) (xy -6.604 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.064 0.254) (xy -3.556 0.254) (xy -3.556 -0.254) (xy -4.064 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 3.556 0.254) (xy 4.064 0.254) (xy 4.064 -0.254) (xy 3.556 -0.254)) (layer F.Fab) (width 0)) + (fp_line (start 6.985 1.27) (end 5.715 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 0.635) (end 5.715 1.27) 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(size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 129 /SB_HEADERS/IO_OUT3) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at -6.35 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D425) + (at 206.0011 98.5036 90) + (descr JUMPER) + (path /6303E571/24BB3575) + (fp_text reference JP18 (at -1.651 2.54 180) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value JP1E (at 2.921 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 55 /Microcontroller/ISOLATION_SENSE) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27 90) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 51 /Microcontroller/IO_IN2) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:JP1 (layer Top) (tedit 0) (tstamp 6303D43A) + (at 182.751096 87.960707) + (descr JUMPER) + (path /6303E571/8C09E143) + (fp_text reference JP19 (at -1.651 2.54 90) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value JP1E (at 2.921 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 0 -1.27) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.1016)) + (pad 1 thru_hole oval (at 0 1.27) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (net 49 /Microcontroller/IO_IN1) (solder_mask_margin 0.1016)) + ) + + (module SB_LOGICBOARD_V01:MA03-1 (layer Top) (tedit 0) (tstamp 6303D44F) + (at 204.5011 114.5036 270) + (descr "PIN HEADER") + (path /6303E571/1FCB83CC) + (fp_text reference SV1 (at -3.81 -1.651 270) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value MA03-1 (at -3.81 2.921 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_poly (pts (xy 2.286 0.254) (xy 2.794 0.254) (xy 2.794 -0.254) (xy 2.286 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 0.254) (xy -2.286 0.254) (xy -2.286 -0.254) (xy -2.794 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 0.254) (xy 0.254 0.254) (xy 0.254 -0.254) (xy -0.254 -0.254)) (layer F.Fab) (width 0)) + (fp_text user 1 (at -5.08 0.635 270) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_line (start 3.81 -0.635) (end 3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 1.27) (end 1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 1.27) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 0.635) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -1.27) (end 3.81 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 3.175 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -0.635) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + 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(clearance 0.000001)) + (min_thickness 0.2032) + (fill (arc_segments 32) (thermal_gap 0.4564) (thermal_bridge_width 0.4564)) + (polygon + (pts + (xy 228.7043 147.2068) (xy 68.2979 147.2068) (xy 68.2979 62.8004) (xy 228.7043 62.8004) + ) + ) + ) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06.kicad_mod new file mode 100644 index 0000000..ee78d46 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06.kicad_mod @@ -0,0 +1,70 @@ +(module 1X06 (layer F.Cu) (tedit 0) + (descr "PIN HEADER") + (fp_text reference JP17 (at -7.6962 -1.8288) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value "" (at -7.62 3.175 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start 0.635 -1.27) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 2.54 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(layer F.SilkS) (width 0.1524)) + (fp_line (start 7.62 0.635) (end 6.985 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 -1.27) (end 5.08 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 0.635) (end 5.715 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 1.27) (end 5.715 1.27) (layer F.SilkS) (width 0.1524)) + (fp_poly (pts (xy 3.556 0.254) (xy 4.064 0.254) (xy 4.064 -0.254) (xy 3.556 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.064 0.254) (xy -3.556 0.254) (xy -3.556 -0.254) (xy -4.064 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -6.604 0.254) (xy -6.096 0.254) (xy -6.096 -0.254) (xy -6.604 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 6.096 0.254) (xy 6.604 0.254) (xy 6.604 -0.254) (xy 6.096 -0.254)) (layer F.Fab) (width 0)) + (pad 1 thru_hole oval (at -6.35 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at -1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 5 thru_hole oval (at 3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 6 thru_hole oval (at 6.35 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06_LOCK.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06_LOCK.kicad_mod new file mode 100644 index 0000000..c520143 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X06_LOCK.kicad_mod @@ -0,0 +1,70 @@ +(module 1X06_LOCK (layer F.Cu) (tedit 0) + (descr "This footprint was designed to help hold the alignment of a through-hole component (i.e. 6-pin header) while soldering it into place. \nYou may notice that each hole has been shifted either up or down by 0.005 of an inch from it's more standard position (which is a perfectly straight line). \nThis slight alteration caused the pins (the squares in the middle) to touch the edges of the holes. Because they are alternating, it causes a \"brace\" \nto hold the component in place. 0.005 has proven to be the perfect amount of \"off-center\" position when using our standard breakaway headers.\nAlthough looks a little odd when you look at the bare footprint, once you have a header in there, the alteration is very hard to notice. Also,\nif you push a header all the way into place, it is covered up entirely on the bottom side. This idea of altering the position of holes to aid alignment \nwill be further integrated into the Sparkfun Library for other footprints. It can help hold any component with 3 or more connection pins.") + (fp_text reference J1 (at -1.27 -1.778) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text value ZL201-06G (at -1.27 3.302) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -1.27 -0.508) (end -0.635 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.635 -1.143) (end 0.635 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.635 -1.143) (end 1.27 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.27 -0.508) (end 1.905 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 1.905 -1.143) (end 3.175 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.175 -1.143) (end 3.81 -0.508) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.81 -0.508) (end 4.445 -1.143) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.445 -1.143) (end 5.715 -1.143) (layer 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thru_hole oval (at -5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 5 thru_hole oval (at 2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 6 thru_hole oval (at 5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 7 thru_hole oval (at 7.62 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X20.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X20.kicad_mod new file mode 100644 index 0000000..6206fdc --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/1X20.kicad_mod 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(layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 7 thru_hole oval (at -8.89 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 8 thru_hole oval (at -6.35 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 9 thru_hole oval (at -3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 10 thru_hole oval (at -1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 11 thru_hole oval (at 1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 12 thru_hole oval (at 3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 13 thru_hole oval (at 6.35 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 14 thru_hole oval (at 8.89 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 15 thru_hole oval (at 11.43 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 16 thru_hole oval (at 13.97 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 17 thru_hole oval (at 16.51 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 18 thru_hole oval (at 19.05 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 19 thru_hole oval (at 21.59 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 20 thru_hole oval (at 24.13 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X06.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X06.kicad_mod new file mode 100644 index 0000000..3245838 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X06.kicad_mod @@ -0,0 +1,88 @@ +(module 2X06 (layer F.Cu) (tedit 0) + (descr "PIN HEADER") + (fp_text reference ISO (at -7.775 1.52 90) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_text value "" (at -7.62 4.445) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -7.62 1.905) (end -6.985 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 2.54) (end -5.08 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.08 1.905) (end -4.445 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 2.54) (end -2.54 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 1.905) (end -1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 2.54) (end 0 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 1.905) (end 0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 2.54) (end 2.54 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 1.905) (end 3.175 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 2.54) (end 5.08 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -7.62 1.905) (end -7.62 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -7.62 -1.905) (end -6.985 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 -2.54) (end -5.715 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 -2.54) (end -5.08 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.08 -1.905) (end -4.445 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 -2.54) (end -3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -2.54) (end -2.54 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 -1.905) (end -1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -2.54) (end -0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -2.54) (end 0 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -1.905) (end 0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -2.54) (end 1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -2.54) (end 2.54 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 -1.905) (end 3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -2.54) (end 4.445 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 -2.54) (end 5.08 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.08 -1.905) (end -5.08 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 -1.905) (end -2.54 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -1.905) (end 0 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 -1.905) (end 2.54 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 -1.905) (end 5.08 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 2.54) (end 4.445 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 2.54) (end 1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 2.54) (end -0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 2.54) (end -3.175 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 2.54) (end -5.715 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 1.905) (end 5.715 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 2.54) (end 7.62 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 -1.905) (end 5.715 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 -2.54) (end 6.985 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 -2.54) (end 7.62 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 7.62 -1.905) (end 7.62 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 2.54) (end 6.985 2.54) (layer F.SilkS) (width 0.1524)) + (fp_poly (pts (xy -6.604 1.524) (xy -6.096 1.524) (xy -6.096 1.016) (xy -6.604 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -6.604 -1.016) (xy -6.096 -1.016) (xy -6.096 -1.524) (xy -6.604 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.064 -1.016) (xy -3.556 -1.016) (xy -3.556 -1.524) (xy -4.064 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.064 1.524) (xy -3.556 1.524) (xy -3.556 1.016) (xy -4.064 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 -1.016) (xy -1.016 -1.016) (xy -1.016 -1.524) (xy -1.524 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 1.524) (xy -1.016 1.524) (xy -1.016 1.016) (xy -1.524 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.016 -1.016) (xy 1.524 -1.016) (xy 1.524 -1.524) (xy 1.016 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 3.556 -1.016) (xy 4.064 -1.016) (xy 4.064 -1.524) (xy 3.556 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.016 1.524) (xy 1.524 1.524) (xy 1.524 1.016) (xy 1.016 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 3.556 1.524) (xy 4.064 1.524) (xy 4.064 1.016) (xy 3.556 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 6.096 -1.016) (xy 6.604 -1.016) (xy 6.604 -1.524) (xy 6.096 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 6.096 1.524) (xy 6.604 1.524) (xy 6.604 1.016) (xy 6.096 1.016)) (layer F.Fab) (width 0)) + (pad 1 thru_hole circle (at -6.35 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole circle (at -6.35 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole circle (at -3.81 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole circle (at -3.81 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 5 thru_hole circle (at -1.27 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 6 thru_hole circle (at -1.27 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 7 thru_hole circle (at 1.27 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 8 thru_hole circle (at 1.27 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 9 thru_hole circle (at 3.81 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 10 thru_hole circle (at 3.81 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 11 thru_hole circle (at 6.35 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 12 thru_hole circle (at 6.35 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X07.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X07.kicad_mod new file mode 100644 index 0000000..8bf06bb --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X07.kicad_mod @@ -0,0 +1,101 @@ +(module 2X07 (layer F.Cu) (tedit 0) + (descr "PIN HEADER") + (fp_text reference LCD (at -9.275 1.79 90) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_text value "" (at -8.89 4.445) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -8.89 1.905) (end -8.255 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 2.54) (end -6.35 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 1.905) (end -5.715 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 2.54) (end -3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 1.905) (end -3.175 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 2.54) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 1.905) (end -0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 2.54) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 1.905) (end 1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 2.54) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 1.905) (end 4.445 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 2.54) (end 6.35 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.89 1.905) (end -8.89 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.89 -1.905) (end -8.255 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.255 -2.54) (end -6.985 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.985 -2.54) (end -6.35 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 -1.905) (end -5.715 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 -2.54) (end -4.445 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 -2.54) (end -3.81 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -1.905) (end -3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -2.54) (end -1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -2.54) (end -1.27 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -1.905) (end -0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -2.54) (end 0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -2.54) (end 1.27 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -1.905) (end 1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -2.54) (end 3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -2.54) (end 3.81 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -1.905) (end 4.445 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 -2.54) (end 5.715 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.715 -2.54) (end 6.35 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.35 -1.905) (end -6.35 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -1.905) (end -3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -1.905) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -1.905) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -1.905) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 -1.905) (end 6.35 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 2.54) (end 5.715 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 2.54) (end 3.175 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 2.54) (end 0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 2.54) (end -1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.715 2.54) (end -4.445 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.255 2.54) (end -6.985 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 1.905) (end 6.985 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.255 2.54) (end 8.89 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.35 -1.905) (end 6.985 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 -2.54) (end 8.255 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.255 -2.54) (end 8.89 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.89 -1.905) (end 8.89 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 6.985 2.54) (end 8.255 2.54) (layer F.SilkS) (width 0.1524)) + (fp_poly (pts (xy -7.874 1.524) (xy -7.366 1.524) (xy -7.366 1.016) (xy -7.874 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -7.874 -1.016) (xy -7.366 -1.016) (xy -7.366 -1.524) (xy -7.874 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.334 -1.016) (xy -4.826 -1.016) (xy -4.826 -1.524) (xy -5.334 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.334 1.524) (xy -4.826 1.524) (xy -4.826 1.016) (xy -5.334 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 -1.016) (xy -2.286 -1.016) (xy -2.286 -1.524) (xy -2.794 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 1.524) (xy -2.286 1.524) (xy -2.286 1.016) (xy -2.794 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 -1.016) (xy 0.254 -1.016) (xy 0.254 -1.524) (xy -0.254 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.286 -1.016) (xy 2.794 -1.016) (xy 2.794 -1.524) (xy 2.286 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.826 -1.016) (xy 5.334 -1.016) (xy 5.334 -1.524) (xy 4.826 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 1.524) (xy 0.254 1.524) (xy 0.254 1.016) (xy -0.254 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.286 1.524) (xy 2.794 1.524) (xy 2.794 1.016) (xy 2.286 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.826 1.524) (xy 5.334 1.524) (xy 5.334 1.016) (xy 4.826 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 7.366 -1.016) (xy 7.874 -1.016) (xy 7.874 -1.524) (xy 7.366 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 7.366 1.524) (xy 7.874 1.524) (xy 7.874 1.016) (xy 7.366 1.016)) (layer F.Fab) (width 0)) + (pad 1 thru_hole circle (at -7.62 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole circle (at -7.62 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole circle (at -5.08 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole circle (at -5.08 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 5 thru_hole circle (at -2.54 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 6 thru_hole circle (at -2.54 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 7 thru_hole circle (at 0 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 8 thru_hole circle (at 0 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 9 thru_hole circle (at 2.54 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 10 thru_hole circle (at 2.54 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 11 thru_hole circle (at 5.08 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 12 thru_hole circle (at 5.08 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 13 thru_hole circle (at 7.62 1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 14 thru_hole circle (at 7.62 -1.27) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X20_2MM.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X20_2MM.kicad_mod new file mode 100644 index 0000000..9d6f7f8 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/2X20_2MM.kicad_mod @@ -0,0 +1,94 @@ +(module 2X20_2MM (layer F.Cu) (tedit 0) + (descr "PIN HEADER") + (fp_text reference MAINB (at -5.195 1.27 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value "" (at -1.27 3.175) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -3.55 1.7) (end -3.55 -3.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.55 -3.7) (end 41.55 -3.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 41.55 -3.7) (end 41.55 1.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.55 1.7) (end 18 1.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 20 1.7) (end 41.55 1.7) (layer F.SilkS) (width 0.127)) + (pad 1 thru_hole circle (at 0 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole circle (at 0 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole circle (at 2 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole circle (at 2 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 5 thru_hole circle (at 4 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 6 thru_hole circle (at 4 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 7 thru_hole circle (at 6 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 8 thru_hole circle (at 6 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 9 thru_hole circle (at 8 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 10 thru_hole circle (at 8 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 11 thru_hole circle (at 10 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 12 thru_hole circle (at 10 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 13 thru_hole circle (at 12 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 14 thru_hole circle (at 12 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 15 thru_hole circle (at 14 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 16 thru_hole circle (at 14 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 17 thru_hole circle (at 16 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 18 thru_hole circle (at 16 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 19 thru_hole circle (at 18 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 20 thru_hole circle (at 18 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 21 thru_hole circle (at 20 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 22 thru_hole circle (at 20 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 23 thru_hole circle (at 22 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 24 thru_hole circle (at 22 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 25 thru_hole circle (at 24 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 26 thru_hole circle (at 24 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 27 thru_hole circle (at 26 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 28 thru_hole circle (at 26 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 29 thru_hole circle (at 28 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 30 thru_hole circle (at 28 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 31 thru_hole circle (at 30 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 32 thru_hole circle (at 30 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 33 thru_hole circle (at 32 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 34 thru_hole circle (at 32 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 35 thru_hole circle (at 34 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 36 thru_hole circle (at 34 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 37 thru_hole circle (at 36 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 38 thru_hole circle (at 36 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 39 thru_hole circle (at 38 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 40 thru_hole circle (at 38 -2) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/B2,54.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/B2,54.kicad_mod new file mode 100644 index 0000000..5ac9ed4 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/B2,54.kicad_mod @@ -0,0 +1,17 @@ +(module B2,54 (layer F.Cu) (tedit 0) + (descr "TEST PAD") + (fp_text reference 3V3 (at 3.024 2.295 -90) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value NC (at -1.27 1.397) (layer F.Fab) + (effects (font (size 0.02413 0.02413) (thickness 0.00193)) (justify left bottom)) + ) + (fp_line (start -0.635 0) (end 0.635 0) (layer Dwgs.User) (width 0.0024)) + (fp_line (start 0 0.635) (end 0 -0.635) (layer Dwgs.User) (width 0.0024)) + (fp_circle (center 0 0) (end 0.635 0) (layer Dwgs.User) (width 0.254)) + (fp_text user >TP_SIGNAL_NAME (at -1.27 3.175) (layer Dwgs.User) + (effects (font (size 0.95 0.95) (thickness 0.08)) (justify left bottom)) + ) + (pad TP smd roundrect (at 0 0) (size 2.54 2.54) (layers F.Cu F.Mask) (roundrect_rratio 0.5) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0603.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0603.kicad_mod new file mode 100644 index 0000000..d8124e3 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0603.kicad_mod @@ -0,0 +1,22 @@ +(module C0603 (layer F.Cu) (tedit 0) + (descr CAPACITOR) + (fp_text reference C42 (at 1.42 0.02 -180) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 2.2uf/6.3v/x7r (at -0.635 1.905 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) + (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (pad 1 smd rect (at -0.85 0) (size 1.1 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 0.85 0) (size 1.1 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0805.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0805.kicad_mod new file mode 100644 index 0000000..7ec369b --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C0805.kicad_mod @@ -0,0 +1,22 @@ +(module C0805 (layer F.Cu) (tedit 0) + (descr CAPACITOR

) + (fp_text reference C17 (at -3.52 2.23 -180) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_text value 100n (at -1.27 2.54 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C1206.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C1206.kicad_mod new file mode 100644 index 0000000..e3c1a87 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/C1206.kicad_mod @@ -0,0 +1,22 @@ +(module C1206 (layer F.Cu) (tedit 0) + (descr CAPACITOR) + (fp_text reference C26 (at 2.785 0.5) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 1206DD106KAT2A (at -1.27 2.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -2.473 -0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 -0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) + (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (pad 1 smd rect (at -1.4 0) (size 1.6 1.8) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 1.4 0) (size 1.6 1.8) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/CRYSTAL-SMD-5X3.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/CRYSTAL-SMD-5X3.kicad_mod new file mode 100644 index 0000000..bcbe554 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/CRYSTAL-SMD-5X3.kicad_mod @@ -0,0 +1,20 @@ +(module CRYSTAL-SMD-5X3 (layer F.Cu) (tedit 0) + (fp_text reference Y3 (at -4.345 -0.8175 90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 8.00M-CFPX104 (at -2.54 2.54) (layer F.Fab) + (effects (font (size 0.38608 0.38608) (thickness 0.030886)) (justify left bottom)) + ) + (fp_line (start -0.6 -1.6) (end 0.6 -1.6) (layer F.SilkS) (width 0.2032)) + (fp_line (start 2.5 -0.3) (end 2.5 0.3) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.6 1.6) (end -0.6 1.6) (layer F.SilkS) (width 0.2032)) + (fp_line (start -2.5 -0.3) (end -2.5 0.3) (layer F.SilkS) (width 0.2032)) + (pad 1 smd rect (at -1.85 1.15) (size 1.9 1.1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 1.85 -1.15) (size 1.9 1.1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -1.85 -1.15) (size 1.9 1.1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 1.85 1.15) (size 1.9 1.1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/JP1.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/JP1.kicad_mod new file mode 100644 index 0000000..5a595d1 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/JP1.kicad_mod @@ -0,0 +1,29 @@ +(module JP1 (layer F.Cu) (tedit 0) + (descr JUMPER) + (fp_text reference JP19 (at -1.651 2.54 90) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value "" (at 2.921 2.54 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_line (start -1.016 0) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 0) (end -1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 0) (end 1.27 0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.254) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 2.54) (end 1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -2.286) (end 1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.016 -2.54) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.016 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -2.286) (end -1.27 -0.254) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.254) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end -1.27 2.286) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.016 2.54) (end 1.016 2.54) (layer F.SilkS) (width 0.1524)) + (fp_poly (pts (xy -0.3048 -0.9652) (xy 0.3048 -0.9652) (xy 0.3048 -1.5748) (xy -0.3048 -1.5748)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.3048 1.5748) (xy 0.3048 1.5748) (xy 0.3048 0.9652) (xy -0.3048 0.9652)) (layer F.Fab) (width 0)) + (pad 1 thru_hole oval (at 0 1.27) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at 0 -1.27) (size 2.8448 1.4224) (drill 0.9144) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/L0805.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/L0805.kicad_mod new file mode 100644 index 0000000..3db53e8 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/L0805.kicad_mod @@ -0,0 +1,17 @@ +(module L0805 (layer F.Cu) (tedit 0) + (fp_text reference L8 (at -1.905 -1.143) (layer F.SilkS) hide + (effects (font (size 0.84455 0.84455) (thickness 0.09779)) (justify left bottom)) + ) + (fp_text value LCBB-601 (at -1.905 2.032) (layer F.Fab) + (effects (font (size 0.84455 0.84455) (thickness 0.0929)) (justify left bottom)) + ) + (fp_line (start 1.651 -0.889) (end 1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.889) (end -1.651 0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.889) (end -1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.889) (end 1.651 -0.889) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -1.4605 0.762) (xy 1.4605 0.762) (xy 1.4605 -0.762) (xy -1.4605 -0.762)) (layer Dwgs.User) (width 0)) + (pad 1 smd roundrect (at -0.889 0) (size 1.016 1.397) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.125) + (solder_mask_margin 0.1016)) + (pad 2 smd roundrect (at 0.889 0) (size 1.016 1.397) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.125) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/LED5MM.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/LED5MM.kicad_mod new file mode 100644 index 0000000..00acbca --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/LED5MM.kicad_mod @@ -0,0 +1,22 @@ +(module LED5MM (layer F.Cu) (tedit 0) + (descr "LED

\n5 mm, round") + (fp_text reference WARN (at 3.425 1.2166) (layer F.SilkS) + (effects (font (size 2.85 2.85) (thickness 0.342)) (justify left bottom)) + ) + (fp_text value "" (at 3.2004 1.8034) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_line (start 2.54 1.905) (end 2.54 -1.905) (layer F.SilkS) (width 0.2032)) + (fp_arc (start 0 0) (end 2.54 1.905) (angle 286.260205) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end -1.143 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.143) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.651 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 1.651) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -2.159 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 2.159) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_circle (center 0 0) (end 2.54 0) (layer F.SilkS) (width 0.1524)) + (pad A thru_hole circle (at -1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad K thru_hole circle (at 1.27 0) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/MA03-1.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/MA03-1.kicad_mod new file mode 100644 index 0000000..f0919bf --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/MA03-1.kicad_mod @@ -0,0 +1,41 @@ +(module MA03-1 (layer F.Cu) (tedit 0) + (descr "PIN HEADER") + (fp_text reference SV1 (at -3.81 -1.651) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top)) + ) + (fp_text value "" (at -3.81 2.921 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_line (start -3.175 -1.27) (end -1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -1.27) (end -1.27 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 0.635) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -1.27) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 0.635) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 1.27) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 1.27) (end -1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -0.635) (end -3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -1.27) (end -3.81 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 0.635) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 1.27) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -0.635) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 3.175 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -1.27) (end 3.81 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 0.635) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 1.27) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 1.27) (end 1.27 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -0.635) (end 3.81 0.635) (layer F.SilkS) (width 0.1524)) + (fp_text user 1 (at -5.08 0.635) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_poly (pts (xy -0.254 0.254) (xy 0.254 0.254) (xy 0.254 -0.254) (xy -0.254 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 0.254) (xy -2.286 0.254) (xy -2.286 -0.254) (xy -2.794 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.286 0.254) (xy 2.794 0.254) (xy 2.794 -0.254) (xy 2.286 -0.254)) (layer F.Fab) (width 0)) + (pad 1 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at 2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/R0805.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/R0805.kicad_mod new file mode 100644 index 0000000..9d1362e --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/R0805.kicad_mod @@ -0,0 +1,22 @@ +(module R0805 (layer F.Cu) (tedit 0) + (descr RESISTOR

) + (fp_text reference R26 (at 1.865 0.73 -180) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value 22K (at -0.635 2.54 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -0.41 -0.635) (end 0.41 -0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.41 0.635) (end 0.41 0.635) (layer F.Fab) (width 0.1524)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy 0.4064 0.6985) (xy 1.0564 0.6985) (xy 1.0564 -0.7015) (xy 0.4064 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0668 0.6985) (xy -0.4168 0.6985) (xy -0.4168 -0.7015) (xy -1.0668 -0.7015)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1999 0.5001) (xy 0.1999 0.5001) (xy 0.1999 -0.5001) (xy -0.1999 -0.5001)) (layer F.Adhes) (width 0)) + (pad 1 smd rect (at -0.95 0) (size 1.3 1.5) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 0.95 0) (size 1.3 1.5) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SB-PCB.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SB-PCB.kicad_mod new file mode 100644 index 0000000..11370e1 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SB-PCB.kicad_mod @@ -0,0 +1,61 @@ +(module SB-PCB (layer F.Cu) (tedit 0) + (fp_text reference U$1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_text value SB_LOGIC_PCB (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_line (start 160 -4) (end 160 -80) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 156 -80) (end 160 -80) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 156 -84) (end 4 -84) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 4 -80) (end 4 -84) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 0 -80) (end 0 -4) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 4 -4) (end 0 -4) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_line (start 4 0) (end 156 0) (layer Edge.Cuts) (width 0.05)) + (fp_arc (start 156 -4) (end 156 0) (angle -90) (layer Edge.Cuts) (width 0.05)) + (fp_circle (center 144 -23.5) (end 146.5 -23.5) (layer F.Fab) (width 0.127)) + (fp_circle (center 144 -38.5) (end 146.5 -38.5) (layer F.Fab) (width 0.127)) + (fp_circle (center 144 -53.5) (end 146.5 -53.5) (layer F.Fab) (width 0.127)) + (fp_text user LED (at 148 -53) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LED (at 148 -38) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LED (at 148 -23) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 113 -71) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 113 -25) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 51 -25) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user LCD (at 51 -71) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user MOUNT (at 21 -7) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user MOUNT (at 121 -7) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text user MOUNT (at 71 -63) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_circle (center 5 -16) (end 5.5 -16) (layer F.Fab) (width 0.127)) + (fp_circle (center 3.5 -50.75) (end 4 -50.75) (layer F.Fab) (width 0.127)) + (fp_circle (center 71 -71) (end 71.5 -71) (layer F.Fab) (width 0.127)) + (fp_circle (center 43.5 -6) (end 44 -6) (layer F.Fab) (width 0.127)) + (pad "" np_thru_hole circle (at 30 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 95 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 130 -8) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 110 -26) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 110 -72) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 48 -26) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 48 -72) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 80 -63.5) (size 4.2 4.2) (drill 4.2) (layers *.Cu *.Mask)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SML0805.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SML0805.kicad_mod new file mode 100644 index 0000000..f472b08 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SML0805.kicad_mod @@ -0,0 +1,22 @@ +(module SML0805 (layer F.Cu) (tedit 0) + (descr "SML0805-2CW-TR (0805 PROFILE) COOL WHITE

\nSource: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf") + (fp_text reference HB (at -1.25 2.5 -180) (layer F.SilkS) + (effects (font (size 1.425 1.425) (thickness 0.171)) (justify left bottom)) + ) + (fp_text value OSR50805C1E (at -1.5 2 -180) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start -0.95 0.55) (end 0.95 0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 0.55) (end 0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start 0.95 -0.55) (end -0.95 -0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.95 -0.55) (end -0.95 0.55) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.175 0.025) (end 0 -0.15) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0 -0.15) (end 0.15 0) (layer F.SilkS) (width 0.0634)) + (fp_line (start 0.15 0) (end -0.025 0.175) (layer F.SilkS) (width 0.0634)) + (fp_line (start -0.025 0.175) (end -0.175 0.025) (layer F.SilkS) (width 0.0634)) + (fp_circle (center -0.275 -0.4) (end -0.2125 -0.4) (layer F.SilkS) (width 0.125)) + (pad C smd rect (at -1.05 0) (size 1.2 1.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad A smd rect (at 1.05 0) (size 1.2 1.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO08.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO08.kicad_mod new file mode 100644 index 0000000..20b80c2 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO08.kicad_mod @@ -0,0 +1,40 @@ +(module SO08 (layer F.Cu) (tedit 0) + (descr "Small Outline Package 8
\nNS Package M08A") + (fp_text reference IC4 (at 2.345 0.083) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value LM358D (at 3.937 1.905 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start 2.4 -1.9) (end 2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.4) (end 2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.9) (end -2.4 1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.9) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 1.4) (end -2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start -2.4 -1.9) (end 2.4 -1.9) (layer F.Fab) (width 0.2032)) + (fp_line (start 2.4 1.4) (end -2.4 1.4) (layer F.Fab) (width 0.2032)) + (fp_poly (pts (xy -2.15 3.1) (xy -1.66 3.1) (xy -1.66 2) (xy -2.15 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 3.1) (xy -0.39 3.1) (xy -0.39 2) (xy -0.88 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 3.1) (xy 0.88 3.1) (xy 0.88 2) (xy 0.39 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 3.1) (xy 2.15 3.1) (xy 2.15 2) (xy 1.66 2)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.66 -2) (xy 2.15 -2) (xy 2.15 -3.1) (xy 1.66 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.39 -2) (xy 0.88 -2) (xy 0.88 -3.1) (xy 0.39 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.88 -2) (xy -0.39 -2) (xy -0.39 -3.1) (xy -0.88 -3.1)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.15 -2) (xy -1.66 -2) (xy -1.66 -3.1) (xy -2.15 -3.1)) (layer F.Fab) (width 0)) + (pad 2 smd rect (at -0.635 2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 7 smd rect (at -0.635 -2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -1.905 2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 0.635 2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at 1.905 2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 8 smd rect (at -1.905 -2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 -2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 5 smd rect (at 1.905 -2.6) (size 0.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO20W.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO20W.kicad_mod new file mode 100644 index 0000000..d0a249e --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SO20W.kicad_mod @@ -0,0 +1,101 @@ +(module SO20W (layer F.Cu) (tedit 0) + (descr "Wide Small Outline package 300 mil") + (fp_text reference IC6 (at -6.858 3.175 -90) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value "74HCT244DW OR 74VHCT541A" (at -3.81 1.778) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_line (start 6.1214 -3.7338) (end -6.1214 -3.7338) (layer F.Fab) (width 0.1524)) + (fp_arc (start 6.1214 3.3528) (end 6.1214 3.7338) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -6.1214 -3.3528) (end -6.5024 -3.3528) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 6.1214 -3.3528) (end 6.1214 -3.7338) (angle 90) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -6.1214 3.3528) (end -6.5024 3.3528) (angle -90) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.1214 3.7338) (end 6.1214 3.7338) (layer F.Fab) (width 0.1524)) + (fp_line (start 6.5024 3.3528) (end 6.5024 -3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -3.3528) (end -6.5024 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 -1.27) (end -6.5024 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.5024 1.27) (end -6.5024 3.3528) (layer F.SilkS) (width 0.1524)) + (fp_line (start -6.477 3.3782) (end 6.477 3.3782) (layer F.SilkS) (width 0.0508)) + (fp_arc (start -6.5024 0) (end -6.5024 -1.27) (angle 180) (layer F.SilkS) (width 0.1524)) + (fp_poly (pts (xy -5.969 3.8608) (xy -5.461 3.8608) (xy -5.461 3.7338) (xy -5.969 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 5.334) (xy -5.461 5.334) (xy -5.461 3.8608) (xy -5.969 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 3.8608) (xy -4.191 3.8608) (xy -4.191 3.7338) (xy -4.699 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 5.334) (xy -4.191 5.334) (xy -4.191 3.8608) (xy -4.699 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 3.8608) (xy -2.921 3.8608) (xy -2.921 3.7338) (xy -3.429 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 5.334) (xy -2.921 5.334) (xy -2.921 3.8608) (xy -3.429 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 3.8608) (xy -1.651 3.8608) (xy -1.651 3.7338) (xy -2.159 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 5.334) (xy -1.651 5.334) (xy -1.651 3.8608) (xy -2.159 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 5.334) (xy -0.381 5.334) (xy -0.381 3.8608) (xy -0.889 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 3.8608) (xy -0.381 3.8608) (xy -0.381 3.7338) (xy -0.889 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 3.8608) (xy 0.889 3.8608) (xy 0.889 3.7338) (xy 0.381 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 5.334) (xy 0.889 5.334) (xy 0.889 3.8608) (xy 0.381 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 3.8608) (xy 2.159 3.8608) (xy 2.159 3.7338) (xy 1.651 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 5.334) (xy 2.159 5.334) (xy 2.159 3.8608) (xy 1.651 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 3.8608) (xy 3.429 3.8608) (xy 3.429 3.7338) (xy 2.921 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 5.334) (xy 3.429 5.334) (xy 3.429 3.8608) (xy 2.921 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.8608) (xy -5.461 -3.8608) (xy -5.461 -5.334) (xy -5.969 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -5.969 -3.7338) (xy -5.461 -3.7338) (xy -5.461 -3.8608) (xy -5.969 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.7338) (xy -4.191 -3.7338) (xy -4.191 -3.8608) (xy -4.699 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.699 -3.8608) (xy -4.191 -3.8608) (xy -4.191 -5.334) (xy -4.699 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.7338) (xy -2.921 -3.7338) (xy -2.921 -3.8608) (xy -3.429 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -3.429 -3.8608) (xy -2.921 -3.8608) (xy -2.921 -5.334) (xy -3.429 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.7338) (xy -1.651 -3.7338) (xy -1.651 -3.8608) (xy -2.159 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.159 -3.8608) (xy -1.651 -3.8608) (xy -1.651 -5.334) (xy -2.159 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.7338) (xy -0.381 -3.7338) (xy -0.381 -3.8608) (xy -0.889 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.889 -3.8608) (xy -0.381 -3.8608) (xy -0.381 -5.334) (xy -0.889 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.7338) (xy 0.889 -3.7338) (xy 0.889 -3.8608) (xy 0.381 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.381 -3.8608) (xy 0.889 -3.8608) (xy 0.889 -5.334) (xy 0.381 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.7338) (xy 2.159 -3.7338) (xy 2.159 -3.8608) (xy 1.651 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.651 -3.8608) (xy 2.159 -3.8608) (xy 2.159 -5.334) (xy 1.651 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.7338) (xy 3.429 -3.7338) (xy 3.429 -3.8608) (xy 2.921 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.921 -3.8608) (xy 3.429 -3.8608) (xy 3.429 -5.334) (xy 2.921 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.7338) (xy 4.699 -3.7338) (xy 4.699 -3.8608) (xy 4.191 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.7338) (xy 5.969 -3.7338) (xy 5.969 -3.8608) (xy 5.461 -3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 -3.8608) (xy 4.699 -3.8608) (xy 4.699 -5.334) (xy 4.191 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 -3.8608) (xy 5.969 -3.8608) (xy 5.969 -5.334) (xy 5.461 -5.334)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 3.8608) (xy 4.699 3.8608) (xy 4.699 3.7338) (xy 4.191 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 3.8608) (xy 5.969 3.8608) (xy 5.969 3.7338) (xy 5.461 3.7338)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 4.191 5.334) (xy 4.699 5.334) (xy 4.699 3.8608) (xy 4.191 3.8608)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 5.461 5.334) (xy 5.969 5.334) (xy 5.969 3.8608) (xy 5.461 3.8608)) (layer F.Fab) (width 0)) + (pad 1 smd rect (at -5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at -3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 5 smd rect (at -0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 6 smd rect (at 0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 7 smd rect (at 1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 8 smd rect (at 3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 13 smd rect (at 3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 14 smd rect (at 1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 15 smd rect (at 0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 16 smd rect (at -0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 17 smd rect (at -1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 18 smd rect (at -3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 19 smd rect (at -4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 20 smd rect (at -5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 9 smd rect (at 4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 10 smd rect (at 5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 12 smd rect (at 4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 11 smd rect (at 5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SOT223.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SOT223.kicad_mod new file mode 100644 index 0000000..fb6e0b8 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/SOT223.kicad_mod @@ -0,0 +1,41 @@ +(module SOT223 (layer F.Cu) (tedit 0) + (descr "Small Outline Transistor") + (fp_text reference IC1 (at -2.54 -0.0508) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_text value MCP1826S-3302ED (at -2.54 1.3208) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start 3.2766 -1.778) (end 3.2766 1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.2766 1.778) (end -3.2766 1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start -3.2766 1.778) (end -3.2766 -1.778) (layer F.SilkS) (width 0.2032)) + (fp_line (start -3.2766 -1.778) (end 3.2766 -1.778) (layer F.SilkS) (width 0.2032)) + (fp_text user 3 (at 1.0208 4.318) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 4 (at 1.905 -2.54) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 1 (at -3.4526 4.318) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_text user 2 (at -1.2906 4.3274) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.097536)) (justify left bottom)) + ) + (fp_poly (pts (xy -1.6002 -1.8034) (xy 1.6002 -1.8034) (xy 1.6002 -3.6576) (xy -1.6002 -3.6576)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.4318 3.6576) (xy 0.4318 3.6576) (xy 0.4318 1.8034) (xy -0.4318 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.7432 3.6576) (xy -1.8796 3.6576) (xy -1.8796 1.8034) (xy -2.7432 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.8796 3.6576) (xy 2.7432 3.6576) (xy 2.7432 1.8034) (xy 1.8796 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.6002 -1.8034) (xy 1.6002 -1.8034) (xy 1.6002 -3.6576) (xy -1.6002 -3.6576)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.4318 3.6576) (xy 0.4318 3.6576) (xy 0.4318 1.8034) (xy -0.4318 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.7432 3.6576) (xy -1.8796 3.6576) (xy -1.8796 1.8034) (xy -2.7432 1.8034)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.8796 3.6576) (xy 2.7432 3.6576) (xy 2.7432 1.8034) (xy 1.8796 1.8034)) (layer F.Fab) (width 0)) + (pad 1 smd rect (at -2.3114 3.0988) (size 1.2192 2.2352) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at 0 3.0988) (size 1.2192 2.2352) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at 2.3114 3.0988) (size 1.2192 2.2352) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at 0 -3.099) (size 3.6 2.2) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/TQFP64.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/TQFP64.kicad_mod new file mode 100644 index 0000000..3291f85 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/TQFP64.kicad_mod @@ -0,0 +1,148 @@ +(module TQFP64 (layer F.Cu) (tedit 0) + (descr "64-Lead TQFP Plastic Thin Quad Flatpack - 10x10x1mm Body, 2mmFP") + (fp_text reference U$5 (at -2.75 -0.75) (layer F.SilkS) + (effects (font (size 0.95 0.95) (thickness 0.114)) (justify left bottom)) + ) + (fp_text value STM32F405RG (at -3 3) (layer F.Fab) + (effects (font (size 0.38608 0.38608) (thickness 0.030886)) (justify left bottom)) + ) + (fp_line (start 5 -5) (end 5 5) (layer F.Fab) (width 0.2032)) + (fp_line (start 5 5) (end -5 5) (layer F.Fab) (width 0.2032)) + (fp_line (start -5 5) (end -5 -5) (layer F.Fab) (width 0.2032)) + (fp_line (start -5 -5) (end 5 -5) (layer F.Fab) (width 0.2032)) + (fp_line (start -5.1 -4.1) (end -5.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5.1 -5.1) (end -4.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.1 -5.1) (end 5.1 -5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 5.1 -5.1) (end 5.1 -4.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -5.1 4.1) (end -4.1 5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.1 5.1) (end 5.1 5.1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 5.1 5.1) (end 5.1 4.1) (layer F.SilkS) (width 0.2032)) + (pad 8 smd rect (at -0.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 9 smd rect (at 0.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 6 smd rect (at -1.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 4 smd rect (at -2.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 2 smd rect (at -3.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 7 smd rect (at -0.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 5 smd rect (at -1.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 3 smd rect (at -2.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 1 smd rect (at -3.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 11 smd rect (at 1.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 13 smd rect (at 2.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 15 smd rect (at 3.25 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 16 smd rect (at 3.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 14 smd rect (at 2.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 12 smd rect (at 1.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 10 smd rect (at 0.75 5.75) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 24 smd rect (at 5.75 0.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 25 smd rect (at 5.75 -0.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 22 smd rect (at 5.75 1.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 20 smd rect (at 5.75 2.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 18 smd rect (at 5.75 3.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 23 smd rect (at 5.75 0.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 21 smd rect (at 5.75 1.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 19 smd rect (at 5.75 2.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 17 smd rect (at 5.75 3.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 27 smd rect (at 5.75 -1.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 29 smd rect (at 5.75 -2.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 31 smd rect (at 5.75 -3.25 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 32 smd rect (at 5.75 -3.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 30 smd rect (at 5.75 -2.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 28 smd rect (at 5.75 -1.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 26 smd rect (at 5.75 -0.75 90) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 40 smd rect (at 0.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 41 smd rect (at -0.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 38 smd rect (at 1.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 36 smd rect (at 2.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 34 smd rect (at 3.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 39 smd rect (at 0.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 37 smd rect (at 1.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 35 smd rect (at 2.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 33 smd rect (at 3.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 43 smd rect (at -1.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 45 smd rect (at -2.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 47 smd rect (at -3.25 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 48 smd rect (at -3.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 46 smd rect (at -2.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 44 smd rect (at -1.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 42 smd rect (at -0.75 -5.75 180) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 56 smd rect (at -5.75 -0.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 57 smd rect (at -5.75 0.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 54 smd rect (at -5.75 -1.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 52 smd rect (at -5.75 -2.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 50 smd rect (at -5.75 -3.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 55 smd rect (at -5.75 -0.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 53 smd rect (at -5.75 -1.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 51 smd rect (at -5.75 -2.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 49 smd rect (at -5.75 -3.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 59 smd rect (at -5.75 1.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 61 smd rect (at -5.75 2.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 63 smd rect (at -5.75 3.25 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 64 smd rect (at -5.75 3.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 62 smd rect (at -5.75 2.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 60 smd rect (at -5.75 1.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) + (pad 58 smd rect (at -5.75 0.75 270) (size 0.22 1) (layers F.Cu F.Paste F.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/W237-4.kicad_mod b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/W237-4.kicad_mod new file mode 100644 index 0000000..a3361d3 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pretty/W237-4.kicad_mod @@ -0,0 +1,59 @@ +(module W237-4 (layer F.Cu) (tedit 0) + (descr "WAGO SCREW CLAMP") + (fp_text reference X1 (at -8.7446 7.4422) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value "" (at -7.6524 5.0292) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + ) + (fp_line (start -8.491 2.286) (end -6.484 0.279) (layer F.Fab) (width 0.254)) + (fp_line (start -3.512 2.261) (end -1.531 0.254) (layer F.Fab) (width 0.254)) + (fp_line (start 1.517 2.286) (end 3.524 0.279) (layer F.Fab) (width 0.254)) + (fp_line (start 6.495 2.261) (end 8.477 0.254) (layer F.Fab) (width 0.254)) + (fp_line (start -9.989 5.461) (end 10.001 5.461) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 -3.734) (end 10.001 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 -3.734) (end -9.989 -3.734) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 5.461) (end -9.989 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 3.073) (end -8.389 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -8.389 3.073) (end -6.611 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start -6.611 3.073) (end -3.385 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.607 3.073) (end 1.619 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.397 3.073) (end 6.622 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start 8.4 3.073) (end 10.001 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 3.073) (end -9.989 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 3.073) (end 10.001 5.461) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 -3.531) (end 10.001 -3.531) (layer F.SilkS) (width 0.1524)) + (fp_line (start -9.989 -3.531) (end -9.989 -3.734) (layer F.SilkS) (width 0.1524)) + (fp_line (start 10.001 -3.531) (end 10.001 3.073) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.385 3.073) (end -1.607 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.619 3.073) (end 3.397 3.073) (layer F.Fab) (width 0.1524)) + (fp_line (start 6.622 3.073) (end 8.4 3.073) (layer F.Fab) (width 0.1524)) + (fp_circle (center -7.5 1.27) (end -6.0014 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center -7.5 -2.2098) (end -6.992 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center -2.4962 1.27) (end -0.9976 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center -2.4962 -2.2098) (end -1.9882 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center 2.5076 1.27) (end 4.0062 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center 2.5076 -2.2098) (end 3.0156 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_circle (center 7.5114 1.27) (end 9.01 1.27) (layer F.Fab) (width 0.1524)) + (fp_circle (center 7.5114 -2.2098) (end 8.0194 -2.2098) (layer F.SilkS) (width 0.1524)) + (fp_text user 1 (at -9.532 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 2 (at -4.579 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 3 (at 0.4756 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text user 4 (at 5.4286 -0.635) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (pad 1 thru_hole oval (at -7.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 2 thru_hole oval (at -2.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 3 thru_hole oval (at 2.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) + (pad 4 thru_hole oval (at 7.5 1.27 90) (size 3.5814 1.7907) (drill 1.1938) (layers *.Cu *.Mask) + (solder_mask_margin 0.1016)) +) diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pro b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pro new file mode 100644 index 0000000..3ff0ece --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.pro @@ -0,0 +1,43 @@ +update=22-8-2022 20:21:50 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile=empty.kicad_wks +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 diff --git a/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.sch b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.sch new file mode 100644 index 0000000..008cf64 --- /dev/null +++ b/PCB/kicad/logicBoard/SB_LOGICBOARD_V01.sch @@ -0,0 +1,34 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Sheet +S 1000 1000 500 150 +U 6303E571 +F0 "Microcontroller" 50 +F1 "Microcontroller.sch" 50 +$EndSheet +$Sheet +S 3000 1000 500 150 +U 6303E79D +F0 "Psup 5v and 3.3v" 50 +F1 "Psup_5v_and_3.3v.sch" 50 +$EndSheet +$Sheet +S 5000 1000 500 150 +U 6303EA23 +F0 "SB_HEADERS" 50 +F1 "SB_HEADERS.sch" 50 +$EndSheet +$EndSCHEMATC diff --git a/PCB/kicad/logicBoard/empty.kicad_wks b/PCB/kicad/logicBoard/empty.kicad_wks new file mode 100644 index 0000000..f50032b --- /dev/null +++ b/PCB/kicad/logicBoard/empty.kicad_wks @@ -0,0 +1,5 @@ +(page_layout +(setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15) +(left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10)) +(line (name segm1:Line) (start 0 0) (end 0 0)) +) diff --git a/PCB/kicad/logicBoard/fp-lib-table b/PCB/kicad/logicBoard/fp-lib-table new file mode 100644 index 0000000..2963070 --- /dev/null +++ b/PCB/kicad/logicBoard/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name SB_LOGICBOARD_V01)(type KiCad)(uri "$(KIPRJMOD)/SB_LOGICBOARD_V01.pretty")(options "")(descr "")) +) diff --git a/PCB/kicad/logicBoard/sym-lib-table b/PCB/kicad/logicBoard/sym-lib-table new file mode 100644 index 0000000..a47fbcb --- /dev/null +++ b/PCB/kicad/logicBoard/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name SB_LOGICBOARD_V01-eagle-import)(type Legacy)(uri ${KIPRJMOD}/SB_LOGICBOARD_V01-eagle-import.lib)(options "")(descr "")) +) diff --git a/PCB/kicad/DCBus.sch b/PCB/kicad/powerBoard/DCBus.sch similarity index 100% rename from PCB/kicad/DCBus.sch rename to PCB/kicad/powerBoard/DCBus.sch diff --git a/PCB/kicad/SB2500-battery.kicad_pcb b/PCB/kicad/powerBoard/SB2500-battery.kicad_pcb similarity index 100% rename from PCB/kicad/SB2500-battery.kicad_pcb rename to PCB/kicad/powerBoard/SB2500-battery.kicad_pcb diff --git a/PCB/kicad/SB2500-battery.pro b/PCB/kicad/powerBoard/SB2500-battery.pro similarity index 100% rename from PCB/kicad/SB2500-battery.pro rename to PCB/kicad/powerBoard/SB2500-battery.pro diff --git a/PCB/kicad/SB2500-battery.sch b/PCB/kicad/powerBoard/SB2500-battery.sch similarity index 100% rename from PCB/kicad/SB2500-battery.sch rename to PCB/kicad/powerBoard/SB2500-battery.sch diff --git a/PCB/kicad/logicboard.sch b/PCB/kicad/powerBoard/logicboard.sch similarity index 100% rename from PCB/kicad/logicboard.sch rename to PCB/kicad/powerBoard/logicboard.sch diff --git a/PCB/kicad/powerline.sch b/PCB/kicad/powerBoard/powerline.sch similarity index 100% rename from PCB/kicad/powerline.sch rename to PCB/kicad/powerBoard/powerline.sch