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architecture adapted

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uhi22 2022-11-08 23:33:12 +01:00
parent 13cd9378ce
commit 5bc10a5c49
2 changed files with 15 additions and 8 deletions
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23
doc/pyPlc_architecture.puml
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@ -4,7 +4,7 @@ header
green lines mean: at least stub functionality is working green lines mean: at least stub functionality is working
endheader endheader
package "pyPLC" { package "github.com/uhi22/pyPLC" {
package "pyPlcIPv6" { package "pyPlcIPv6" {
[miniIPv6] [miniIPv6]
[pyPlcUdp] [pyPlcUdp]
@ -17,8 +17,9 @@ package "pyPLC" {
[SLAC] [SLAC]
} }
[fsmEvse] [fsmEvse \nThe charger state machine.] as fsmEvse
[fsmPev] [fsmPev \nThe car state machine.] as fsmPev
[exiConnector.py] as exiConnector
package "pyPlcTcpSocket" { package "pyPlcTcpSocket" {
[pyPlcTcpServerSocket] [pyPlcTcpServerSocket]
@ -31,7 +32,10 @@ package "pyPLC" {
[HomeplugAdaptor] [HomeplugAdaptor]
[pcap DLL] as pcap [pcap DLL] as pcap
[wireshark] [wireshark]
[/FlUxIuS/V2Gdecoder or /Martin-P/OpenV2G] as dec
package "github.com/uhi22/OpenV2Gx" {
[OpenV2Gx.exe \nEncodes and Decodes EXI data via command line interface.] as dec
}
package "WindowsOS or Linux" { package "WindowsOS or Linux" {
[OS_Ethernet] [OS_Ethernet]
@ -41,6 +45,7 @@ package "WindowsOS or Linux" {
} }
[ControlPilotLine] <-[#green]up-> [HomeplugAdaptor] [ControlPilotLine] <-[#green]up-> [HomeplugAdaptor]
[ControlPilotLine] <-[#green]up-> [PWM-Generator]
[HomeplugAdaptor] <-[#green]up-> [OS_Ethernet] [HomeplugAdaptor] <-[#green]up-> [OS_Ethernet]
[OS_Ethernet] <-[#green]up-> [pcap] [OS_Ethernet] <-[#green]up-> [pcap]
[OS_Ethernet] <-[#green]up-> [OS_IPv6] [OS_Ethernet] <-[#green]up-> [OS_IPv6]
@ -56,9 +61,11 @@ package "WindowsOS or Linux" {
[miniIPv6] -up-> [pyPlcTcpExiSniff] [miniIPv6] -up-> [pyPlcTcpExiSniff]
[pyPlcUdp] <-[#green]up-> [pyPlcSDP] [pyPlcUdp] <-[#green]up-> [pyPlcSDP]
[OS_TCP] <-[#green]up-> [pyPlcTcpServerSocket] [OS_TCP] <-[#green]up-> [pyPlcTcpServerSocket]
[OS_TCP] <-up-> [pyPlcTcpClientSocket] [OS_TCP] <-[#green]up-> [pyPlcTcpClientSocket]
[pyPlcTcpServerSocket] <-[#green]up-> [fsmEvse] [pyPlcTcpServerSocket] <-[#green]up-> [fsmEvse]
[pyPlcTcpClientSocket] <-up-> [fsmPev] [pyPlcTcpClientSocket] <-[#green]up-> [fsmPev]
[fsmEvse] <-r-> [dec] [fsmEvse] <-[#green]r-> [exiConnector]
[pyPlcTcpExiSniff] -r-> [dec] [fsmPev] <-[#green]r-> [exiConnector]
[dec] <-[#green]up-> [exiConnector]
[dec] -l-> [pyPlcTcpExiSniff]
@enduml @enduml