From b5e65245948647b94dfd60c1288f030a76c69a83 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Wed, 10 Sep 2014 21:27:14 -0400
Subject: [PATCH 1/5] ARM: Reorganized file structure to move shared SkyEye
code to a more common area.
Removed s_ prefix
---
src/citra_qt/debugger/disassembler.cpp | 2 +-
src/core/CMakeLists.txt | 30 ++++++++---------
src/core/arm/interpreter/arm_interpreter.cpp | 4 +--
src/core/arm/interpreter/arm_interpreter.h | 4 +--
src/core/arm/interpreter/armcopro.cpp | 8 ++---
src/core/arm/interpreter/armemu.cpp | 6 ++--
src/core/arm/interpreter/arminit.cpp | 4 +--
src/core/arm/interpreter/armmmu.cpp | 4 +--
src/core/arm/interpreter/armos.cpp | 8 ++---
src/core/arm/interpreter/armvirt.cpp | 4 +--
.../arm/interpreter/mmu/arm1176jzf_s_mmu.cpp | 4 +--
src/core/arm/interpreter/mmu/cache.cpp | 2 +-
src/core/arm/interpreter/mmu/maverick.cpp | 4 +--
src/core/arm/interpreter/mmu/rb.cpp | 2 +-
src/core/arm/interpreter/mmu/sa_mmu.cpp | 2 +-
src/core/arm/interpreter/mmu/tlb.cpp | 2 +-
src/core/arm/interpreter/mmu/wb.cpp | 2 +-
src/core/arm/interpreter/mmu/xscale_copro.cpp | 4 +--
src/core/arm/interpreter/thumbemu.cpp | 8 ++---
.../arm_regformat.h | 0
.../{interpreter => skyeye_common}/armcpu.h | 0
.../{interpreter => skyeye_common}/armdefs.h | 4 +--
.../{interpreter => skyeye_common}/armemu.h | 2 +-
.../{interpreter => skyeye_common}/armmmu.h | 0
.../{interpreter => skyeye_common}/armos.h | 0
.../skyeye_defs.h | 0
.../vfp/asm_vfp.h | 0
.../vfp/vfp.cpp | 32 +++++++++----------
.../{interpreter => skyeye_common}/vfp/vfp.h | 2 +-
.../vfp/vfp_helper.h | 2 +-
.../vfp/vfpdouble.cpp | 6 ++--
.../vfp/vfpinstr.cpp | 0
.../vfp/vfpsingle.cpp | 6 ++--
src/core/core.h | 2 +-
34 files changed, 80 insertions(+), 80 deletions(-)
rename src/core/arm/{interpreter => skyeye_common}/arm_regformat.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/armcpu.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/armdefs.h (99%)
rename src/core/arm/{interpreter => skyeye_common}/armemu.h (99%)
rename src/core/arm/{interpreter => skyeye_common}/armmmu.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/armos.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/skyeye_defs.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/asm_vfp.h (100%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfp.cpp (91%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfp.h (97%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfp_helper.h (99%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfpdouble.cpp (99%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfpinstr.cpp (100%)
rename src/core/arm/{interpreter => skyeye_common}/vfp/vfpsingle.cpp (99%)
diff --git a/src/citra_qt/debugger/disassembler.cpp b/src/citra_qt/debugger/disassembler.cpp
index 856baf63dc..2ee8777434 100644
--- a/src/citra_qt/debugger/disassembler.cpp
+++ b/src/citra_qt/debugger/disassembler.cpp
@@ -9,7 +9,7 @@
#include "core/core.h"
#include "common/break_points.h"
#include "common/symbols.h"
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/disassembler/arm_disasm.h"
DisassemblerModel::DisassemblerModel(QObject* parent) : QAbstractItemModel(parent), base_address(0), code_size(0), program_counter(0), selection(QModelIndex()) {
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index 06df9a6773..d87e5ad49c 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -9,10 +9,6 @@ set(SRCS
arm/interpreter/mmu/tlb.cpp
arm/interpreter/mmu/wb.cpp
arm/interpreter/mmu/xscale_copro.cpp
- arm/interpreter/vfp/vfp.cpp
- arm/interpreter/vfp/vfpdouble.cpp
- arm/interpreter/vfp/vfpinstr.cpp
- arm/interpreter/vfp/vfpsingle.cpp
arm/interpreter/arm_interpreter.cpp
arm/interpreter/armcopro.cpp
arm/interpreter/armemu.cpp
@@ -22,6 +18,10 @@ set(SRCS
arm/interpreter/armsupp.cpp
arm/interpreter/armvirt.cpp
arm/interpreter/thumbemu.cpp
+ arm/skyeye_common/vfp/vfp.cpp
+ arm/skyeye_common/vfp/vfpdouble.cpp
+ arm/skyeye_common/vfp/vfpinstr.cpp
+ arm/skyeye_common/vfp/vfpsingle.cpp
file_sys/archive_romfs.cpp
file_sys/archive_sdmc.cpp
file_sys/file_romfs.cpp
@@ -63,23 +63,23 @@ set(SRCS
set(HEADERS
arm/disassembler/arm_disasm.h
arm/disassembler/load_symbol_map.h
+ arm/interpreter/arm_interpreter.h
arm/interpreter/mmu/arm1176jzf_s_mmu.h
arm/interpreter/mmu/cache.h
arm/interpreter/mmu/rb.h
arm/interpreter/mmu/sa_mmu.h
arm/interpreter/mmu/tlb.h
arm/interpreter/mmu/wb.h
- arm/interpreter/vfp/asm_vfp.h
- arm/interpreter/vfp/vfp.h
- arm/interpreter/vfp/vfp_helper.h
- arm/interpreter/arm_interpreter.h
- arm/interpreter/arm_regformat.h
- arm/interpreter/armcpu.h
- arm/interpreter/armdefs.h
- arm/interpreter/armemu.h
- arm/interpreter/armmmu.h
- arm/interpreter/armos.h
- arm/interpreter/skyeye_defs.h
+ arm/skyeye_common/vfp/asm_vfp.h
+ arm/skyeye_common/vfp/vfp.h
+ arm/skyeye_common/vfp/vfp_helper.h
+ arm/skyeye_common/arm_regformat.h
+ arm/skyeye_common/armcpu.h
+ arm/skyeye_common/armdefs.h
+ arm/skyeye_common/armemu.h
+ arm/skyeye_common/armmmu.h
+ arm/skyeye_common/armos.h
+ arm/skyeye_common/skyeye_defs.h
arm/arm_interface.h
file_sys/archive.h
file_sys/archive_romfs.h
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 0842d2f8ec..6f6a5913cb 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -4,7 +4,7 @@
#include "core/arm/interpreter/arm_interpreter.h"
-const static cpu_config_t s_arm11_cpu_info = {
+const static cpu_config_t arm11_cpu_info = {
"armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
};
@@ -17,7 +17,7 @@ ARM_Interpreter::ARM_Interpreter() {
ARMul_NewState(state);
state->abort_model = 0;
- state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
+ state->cpu = (cpu_config_t*)&arm11_cpu_info;
state->bigendSig = LOW;
ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 1e82883a22..64760500ce 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -7,8 +7,8 @@
#include "common/common.h"
#include "core/arm/arm_interface.h"
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armemu.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
class ARM_Interpreter : virtual public ARM_Interface {
public:
diff --git a/src/core/arm/interpreter/armcopro.cpp b/src/core/arm/interpreter/armcopro.cpp
index 6a75e66015..ee9fa255ae 100644
--- a/src/core/arm/interpreter/armcopro.cpp
+++ b/src/core/arm/interpreter/armcopro.cpp
@@ -16,10 +16,10 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armos.h"
-#include "core/arm/interpreter/armemu.h"
-#include "core/arm/interpreter/vfp/vfp.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armos.h"
+#include "core/arm/skyeye_common/armemu.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
//chy 2005-07-08
//#include "ansidecl.h"
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index f9130ef88c..7ffc164294 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -18,9 +18,9 @@
//#include <util.h> // DEBUG()
-#include "arm_regformat.h"
-#include "armdefs.h"
-#include "armemu.h"
+#include "core/arm/skyeye_common/arm_regformat.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
#include "core/hle/hle.h"
//#include "svc.h"
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 6fbab3bfb5..03bca28702 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -17,8 +17,8 @@
//#include <unistd.h>
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armemu.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
/***************************************************************************\
* Definitions for the emulator architecture *
diff --git a/src/core/arm/interpreter/armmmu.cpp b/src/core/arm/interpreter/armmmu.cpp
index 242e6a83c6..98fc17ddb3 100644
--- a/src/core/arm/interpreter/armmmu.cpp
+++ b/src/core/arm/interpreter/armmmu.cpp
@@ -20,10 +20,10 @@
#include <assert.h>
#include <string.h>
-#include "armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
/* two header for arm disassemble */
//#include "skyeye_arch.h"
-#include "armcpu.h"
+#include "core/arm/skyeye_common/armcpu.h"
extern mmu_ops_t xscale_mmu_ops;
diff --git a/src/core/arm/interpreter/armos.cpp b/src/core/arm/interpreter/armos.cpp
index 43484ee5fc..90eb20acc9 100644
--- a/src/core/arm/interpreter/armos.cpp
+++ b/src/core/arm/interpreter/armos.cpp
@@ -28,7 +28,7 @@ fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
#include <time.h>
#include <errno.h>
#include <string.h>
-#include "skyeye_defs.h"
+#include "core/arm/skyeye_common/skyeye_defs.h"
#ifndef __USE_LARGEFILE64
#define __USE_LARGEFILE64 /* When use 64 bit large file need define it! for stat64*/
#endif
@@ -74,9 +74,9 @@ extern int _fisatty (FILE *);
#endif
#endif
-#include "armdefs.h"
-#include "armos.h"
-#include "armemu.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armos.h"
+#include "core/arm/skyeye_common/armemu.h"
#ifndef NOOS
#ifndef VALIDATE
diff --git a/src/core/arm/interpreter/armvirt.cpp b/src/core/arm/interpreter/armvirt.cpp
index a072b73be5..eb3c86cb43 100644
--- a/src/core/arm/interpreter/armvirt.cpp
+++ b/src/core/arm/interpreter/armvirt.cpp
@@ -23,8 +23,8 @@ table. The routines PutWord and GetWord implement this. Pages are never
freed as they might be needed again. A single area of memory may be
defined to generate aborts. */
-#include "armdefs.h"
-#include "skyeye_defs.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/skyeye_defs.h"
//#include "code_cov.h"
#ifdef VALIDATE /* for running the validate suite */
diff --git a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp b/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
index a32f076b9d..07951e0e6c 100644
--- a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
+++ b/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
@@ -24,9 +24,9 @@
#include "core/mem_map.h"
-#include "core/arm/interpreter/skyeye_defs.h"
+#include "core/arm/skyeye_common/skyeye_defs.h"
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
//#include "bank_defs.h"
#if 0
#define TLB_SIZE 1024 * 1024
diff --git a/src/core/arm/interpreter/mmu/cache.cpp b/src/core/arm/interpreter/mmu/cache.cpp
index f3c4e0531e..cfbc31f1ed 100644
--- a/src/core/arm/interpreter/mmu/cache.cpp
+++ b/src/core/arm/interpreter/mmu/cache.cpp
@@ -1,4 +1,4 @@
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
/* mmu cache init
*
diff --git a/src/core/arm/interpreter/mmu/maverick.cpp b/src/core/arm/interpreter/mmu/maverick.cpp
index adcc2efb5a..a07d4742b5 100644
--- a/src/core/arm/interpreter/mmu/maverick.cpp
+++ b/src/core/arm/interpreter/mmu/maverick.cpp
@@ -18,8 +18,8 @@
#include <assert.h>
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armemu.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
/*#define CIRRUS_DEBUG 1 */
diff --git a/src/core/arm/interpreter/mmu/rb.cpp b/src/core/arm/interpreter/mmu/rb.cpp
index 07b11e311f..600c9d8c8b 100644
--- a/src/core/arm/interpreter/mmu/rb.cpp
+++ b/src/core/arm/interpreter/mmu/rb.cpp
@@ -1,4 +1,4 @@
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
/*chy 2004-06-06, fix bug found by wenye@cs.ucsb.edu*/
ARMword rb_masks[] = {
diff --git a/src/core/arm/interpreter/mmu/sa_mmu.cpp b/src/core/arm/interpreter/mmu/sa_mmu.cpp
index eff5002de8..27f9ec8e0e 100644
--- a/src/core/arm/interpreter/mmu/sa_mmu.cpp
+++ b/src/core/arm/interpreter/mmu/sa_mmu.cpp
@@ -21,7 +21,7 @@
#include <assert.h>
#include <string.h>
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
/**
* The interface of read data from bus
diff --git a/src/core/arm/interpreter/mmu/tlb.cpp b/src/core/arm/interpreter/mmu/tlb.cpp
index ca60ac1a1d..88c2a8bc54 100644
--- a/src/core/arm/interpreter/mmu/tlb.cpp
+++ b/src/core/arm/interpreter/mmu/tlb.cpp
@@ -1,6 +1,6 @@
#include <assert.h>
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
ARMword tlb_masks[] = {
0x00000000, /* TLB_INVALID */
diff --git a/src/core/arm/interpreter/mmu/wb.cpp b/src/core/arm/interpreter/mmu/wb.cpp
index 82c0cec025..5ddda41ee3 100644
--- a/src/core/arm/interpreter/mmu/wb.cpp
+++ b/src/core/arm/interpreter/mmu/wb.cpp
@@ -1,4 +1,4 @@
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
/* wb_init
* @wb_t :wb_t to init
diff --git a/src/core/arm/interpreter/mmu/xscale_copro.cpp b/src/core/arm/interpreter/mmu/xscale_copro.cpp
index 433ce8e026..cf91fd9330 100644
--- a/src/core/arm/interpreter/mmu/xscale_copro.cpp
+++ b/src/core/arm/interpreter/mmu/xscale_copro.cpp
@@ -21,8 +21,8 @@
#include <assert.h>
#include <string.h>
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armemu.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
/*#include "pxa.h" */
diff --git a/src/core/arm/interpreter/thumbemu.cpp b/src/core/arm/interpreter/thumbemu.cpp
index 032d84b653..f7f11f7148 100644
--- a/src/core/arm/interpreter/thumbemu.cpp
+++ b/src/core/arm/interpreter/thumbemu.cpp
@@ -19,7 +19,7 @@
instruction into its corresponding ARM instruction, and using the
existing ARM simulator. */
-#include "skyeye_defs.h"
+#include "core/arm/skyeye_common/skyeye_defs.h"
#ifndef MODET /* required for the Thumb instruction support */
#if 1
@@ -29,9 +29,9 @@ existing ARM simulator. */
#endif
#endif
-#include "armdefs.h"
-#include "armemu.h"
-#include "armos.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
+#include "core/arm/skyeye_common/armos.h"
/* Decode a 16bit Thumb instruction. The instruction is in the low
diff --git a/src/core/arm/interpreter/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
similarity index 100%
rename from src/core/arm/interpreter/arm_regformat.h
rename to src/core/arm/skyeye_common/arm_regformat.h
diff --git a/src/core/arm/interpreter/armcpu.h b/src/core/arm/skyeye_common/armcpu.h
similarity index 100%
rename from src/core/arm/interpreter/armcpu.h
rename to src/core/arm/skyeye_common/armcpu.h
diff --git a/src/core/arm/interpreter/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
similarity index 99%
rename from src/core/arm/interpreter/armdefs.h
rename to src/core/arm/skyeye_common/armdefs.h
index dd5983be3a..fd574a7a16 100644
--- a/src/core/arm/interpreter/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -31,7 +31,7 @@
#include "arm_regformat.h"
#include "common/platform.h"
-#include "skyeye_defs.h"
+#include "core/arm/skyeye_common/skyeye_defs.h"
//AJ2D--------------------------------------------------------------------------
@@ -130,7 +130,7 @@ typedef unsigned long long uint64_t;
#endif
*/
-#include "armmmu.h"
+#include "core/arm/skyeye_common/armmmu.h"
//#include "lcd/skyeye_lcd.h"
diff --git a/src/core/arm/interpreter/armemu.h b/src/core/arm/skyeye_common/armemu.h
similarity index 99%
rename from src/core/arm/interpreter/armemu.h
rename to src/core/arm/skyeye_common/armemu.h
index 36fb2d09bc..c0f0270fe7 100644
--- a/src/core/arm/interpreter/armemu.h
+++ b/src/core/arm/skyeye_common/armemu.h
@@ -18,7 +18,7 @@
#define __ARMEMU_H__
-#include "armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
//#include "skyeye.h"
//extern ARMword isize;
diff --git a/src/core/arm/interpreter/armmmu.h b/src/core/arm/skyeye_common/armmmu.h
similarity index 100%
rename from src/core/arm/interpreter/armmmu.h
rename to src/core/arm/skyeye_common/armmmu.h
diff --git a/src/core/arm/interpreter/armos.h b/src/core/arm/skyeye_common/armos.h
similarity index 100%
rename from src/core/arm/interpreter/armos.h
rename to src/core/arm/skyeye_common/armos.h
diff --git a/src/core/arm/interpreter/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
similarity index 100%
rename from src/core/arm/interpreter/skyeye_defs.h
rename to src/core/arm/skyeye_common/skyeye_defs.h
diff --git a/src/core/arm/interpreter/vfp/asm_vfp.h b/src/core/arm/skyeye_common/vfp/asm_vfp.h
similarity index 100%
rename from src/core/arm/interpreter/vfp/asm_vfp.h
rename to src/core/arm/skyeye_common/vfp/asm_vfp.h
diff --git a/src/core/arm/interpreter/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
similarity index 91%
rename from src/core/arm/interpreter/vfp/vfp.cpp
rename to src/core/arm/skyeye_common/vfp/vfp.cpp
index eea5e24a9a..e4fa3c20a9 100644
--- a/src/core/arm/interpreter/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -25,8 +25,8 @@
#include "common/common.h"
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/vfp/vfp.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
@@ -62,7 +62,7 @@ VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
if (CoProc == 10 || CoProc == 11)
{
#define VFP_MRC_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MRC_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
@@ -88,7 +88,7 @@ VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
if (CoProc == 10 || CoProc == 11)
{
#define VFP_MCR_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MCR_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
@@ -110,7 +110,7 @@ VFPMRRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value1, AR
if (CoProc == 10 || CoProc == 11)
{
#define VFP_MRRC_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MRRC_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
@@ -136,7 +136,7 @@ VFPMCRR (ARMul_State * state, unsigned type, ARMword instr, ARMword value1, ARMw
if (CoProc == 11 || CoProc == 10)
{
#define VFP_MCRR_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MCRR_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
@@ -179,7 +179,7 @@ VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
#endif
#define VFP_STC_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_STC_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
@@ -210,7 +210,7 @@ VFPLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
if (CoProc == 10 || CoProc == 11)
{
#define VFP_LDC_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_LDC_TRANS
}
DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
@@ -237,7 +237,7 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
if (CoProc == 10 || CoProc == 11)
{
#define VFP_CDP_TRANS
- #include "core/arm/interpreter/vfp/vfpinstr.cpp"
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_CDP_TRANS
int exceptions = 0;
@@ -257,21 +257,21 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
/* ----------- MRC ------------ */
#define VFP_MRC_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MRC_IMPL
#define VFP_MRRC_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MRRC_IMPL
/* ----------- MCR ------------ */
#define VFP_MCR_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MCR_IMPL
#define VFP_MCRR_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_MCRR_IMPL
/* Memory operation are not inlined, as old Interpreter and Fast interpreter
@@ -283,19 +283,19 @@ VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
/* ----------- STC ------------ */
#define VFP_STC_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_STC_IMPL
/* ----------- LDC ------------ */
#define VFP_LDC_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_LDC_IMPL
/* ----------- CDP ------------ */
#define VFP_CDP_IMPL
-#include "core/arm/interpreter/vfp/vfpinstr.cpp"
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_CDP_IMPL
/* Miscellaneous functions */
diff --git a/src/core/arm/interpreter/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
similarity index 97%
rename from src/core/arm/interpreter/vfp/vfp.h
rename to src/core/arm/skyeye_common/vfp/vfp.h
index bbf4caeb02..ed627d41f1 100644
--- a/src/core/arm/interpreter/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -25,7 +25,7 @@
#define vfpdebug //printf
-#include "core/arm/interpreter/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
+#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
unsigned VFPInit (ARMul_State *state);
unsigned VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value);
diff --git a/src/core/arm/interpreter/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
similarity index 99%
rename from src/core/arm/interpreter/vfp/vfp_helper.h
rename to src/core/arm/skyeye_common/vfp/vfp_helper.h
index b222e79f18..a55bf875c8 100644
--- a/src/core/arm/interpreter/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -38,7 +38,7 @@
#include <stdint.h>
#include <stdio.h>
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
#define u16 uint16_t
#define u32 uint32_t
diff --git a/src/core/arm/interpreter/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
similarity index 99%
rename from src/core/arm/interpreter/vfp/vfpdouble.cpp
rename to src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index 5ae99b88ac..13411ad80c 100644
--- a/src/core/arm/interpreter/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -51,9 +51,9 @@
* ===========================================================================
*/
-#include "core/arm/interpreter/vfp/vfp.h"
-#include "core/arm/interpreter/vfp/vfp_helper.h"
-#include "core/arm/interpreter/vfp/asm_vfp.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
+#include "core/arm/skyeye_common/vfp/vfp_helper.h"
+#include "core/arm/skyeye_common/vfp/asm_vfp.h"
static struct vfp_double vfp_double_default_qnan = {
//.exponent = 2047,
diff --git a/src/core/arm/interpreter/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
similarity index 100%
rename from src/core/arm/interpreter/vfp/vfpinstr.cpp
rename to src/core/arm/skyeye_common/vfp/vfpinstr.cpp
diff --git a/src/core/arm/interpreter/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
similarity index 99%
rename from src/core/arm/interpreter/vfp/vfpsingle.cpp
rename to src/core/arm/skyeye_common/vfp/vfpsingle.cpp
index 0fcc852661..8bcbd4fe9a 100644
--- a/src/core/arm/interpreter/vfp/vfpsingle.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
@@ -51,9 +51,9 @@
* ===========================================================================
*/
-#include "core/arm/interpreter/vfp/vfp_helper.h"
-#include "core/arm/interpreter/vfp/asm_vfp.h"
-#include "core/arm/interpreter/vfp/vfp.h"
+#include "core/arm/skyeye_common/vfp/vfp_helper.h"
+#include "core/arm/skyeye_common/vfp/asm_vfp.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
static struct vfp_single vfp_single_default_qnan = {
//.exponent = 255,
diff --git a/src/core/core.h b/src/core/core.h
index 9c72c8b3f9..87da252b83 100644
--- a/src/core/core.h
+++ b/src/core/core.h
@@ -5,7 +5,7 @@
#pragma once
#include "core/arm/arm_interface.h"
-#include "core/arm/interpreter/armdefs.h"
+#include "core/arm/skyeye_common/armdefs.h"
////////////////////////////////////////////////////////////////////////////////////////////////////
From 53a22b84da9690865954f666694de885ccb7c286 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Fri, 12 Sep 2014 18:34:51 -0400
Subject: [PATCH 2/5] ARM: Integrate SkyEye faster "dyncom" interpreter.
Fixed typo (make protected member public)
Added license header back in. I originally removed this because I mostly rewrote the file, but meh
ARM: Fixed a type error in dyncom interpreter.
ARM: Updated dyncom to use unique_ptr for internal ARM state.
---
src/core/CMakeLists.txt | 19 +-
src/core/arm/dyncom/arm_dyncom.cpp | 164 +
src/core/arm/dyncom/arm_dyncom.h | 90 +
src/core/arm/dyncom/arm_dyncom_dec.cpp | 402 +
src/core/arm/dyncom/arm_dyncom_dec.h | 155 +
.../arm/dyncom/arm_dyncom_interpreter.cpp | 6559 +++++++++++++++++
src/core/arm/dyncom/arm_dyncom_interpreter.h | 7 +
src/core/arm/dyncom/arm_dyncom_run.cpp | 120 +
src/core/arm/dyncom/arm_dyncom_run.h | 55 +
src/core/arm/dyncom/arm_dyncom_thumb.cpp | 521 ++
src/core/arm/dyncom/arm_dyncom_thumb.h | 51 +
src/core/arm/interpreter/arm_interpreter.h | 2 +-
src/core/arm/interpreter/armsupp.cpp | 15 +-
src/core/arm/skyeye_common/arm_regformat.h | 4 +-
src/core/arm/skyeye_common/armcpu.h | 5 +-
src/core/arm/skyeye_common/armos.h | 9 +-
src/core/arm/skyeye_common/skyeye_defs.h | 4 +-
src/core/arm/skyeye_common/skyeye_types.h | 55 +
src/core/arm/skyeye_common/vfp/vfpinstr.cpp | 48 +-
src/core/hle/coprocessor.h | 20 -
20 files changed, 8230 insertions(+), 75 deletions(-)
create mode 100644 src/core/arm/dyncom/arm_dyncom.cpp
create mode 100644 src/core/arm/dyncom/arm_dyncom.h
create mode 100644 src/core/arm/dyncom/arm_dyncom_dec.cpp
create mode 100644 src/core/arm/dyncom/arm_dyncom_dec.h
create mode 100644 src/core/arm/dyncom/arm_dyncom_interpreter.cpp
create mode 100644 src/core/arm/dyncom/arm_dyncom_interpreter.h
create mode 100644 src/core/arm/dyncom/arm_dyncom_run.cpp
create mode 100644 src/core/arm/dyncom/arm_dyncom_run.h
create mode 100644 src/core/arm/dyncom/arm_dyncom_thumb.cpp
create mode 100644 src/core/arm/dyncom/arm_dyncom_thumb.h
create mode 100644 src/core/arm/skyeye_common/skyeye_types.h
delete mode 100644 src/core/hle/coprocessor.h
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index d87e5ad49c..9f08277a12 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -1,6 +1,11 @@
set(SRCS
arm/disassembler/arm_disasm.cpp
arm/disassembler/load_symbol_map.cpp
+ arm/dyncom/arm_dyncom.cpp
+ arm/dyncom/arm_dyncom_dec.cpp
+ arm/dyncom/arm_dyncom_interpreter.cpp
+ arm/dyncom/arm_dyncom_run.cpp
+ arm/dyncom/arm_dyncom_thumb.cpp
arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
arm/interpreter/mmu/cache.cpp
arm/interpreter/mmu/maverick.cpp
@@ -43,7 +48,6 @@ set(SRCS
hle/service/service.cpp
hle/service/srv.cpp
hle/config_mem.cpp
- hle/coprocessor.cpp
hle/hle.cpp
hle/svc.cpp
hw/gpu.cpp
@@ -63,6 +67,11 @@ set(SRCS
set(HEADERS
arm/disassembler/arm_disasm.h
arm/disassembler/load_symbol_map.h
+ arm/dyncom/arm_dyncom.h
+ arm/dyncom/arm_dyncom_dec.h
+ arm/dyncom/arm_dyncom_interpreter.h
+ arm/dyncom/arm_dyncom_run.h
+ arm/dyncom/arm_dyncom_thumb.h
arm/interpreter/arm_interpreter.h
arm/interpreter/mmu/arm1176jzf_s_mmu.h
arm/interpreter/mmu/cache.h
@@ -70,9 +79,6 @@ set(HEADERS
arm/interpreter/mmu/sa_mmu.h
arm/interpreter/mmu/tlb.h
arm/interpreter/mmu/wb.h
- arm/skyeye_common/vfp/asm_vfp.h
- arm/skyeye_common/vfp/vfp.h
- arm/skyeye_common/vfp/vfp_helper.h
arm/skyeye_common/arm_regformat.h
arm/skyeye_common/armcpu.h
arm/skyeye_common/armdefs.h
@@ -80,6 +86,10 @@ set(HEADERS
arm/skyeye_common/armmmu.h
arm/skyeye_common/armos.h
arm/skyeye_common/skyeye_defs.h
+ arm/skyeye_common/skyeye_types.h
+ arm/skyeye_common/vfp/asm_vfp.h
+ arm/skyeye_common/vfp/vfp.h
+ arm/skyeye_common/vfp/vfp_helper.h
arm/arm_interface.h
file_sys/archive.h
file_sys/archive_romfs.h
@@ -105,7 +115,6 @@ set(HEADERS
hle/service/service.h
hle/service/srv.h
hle/config_mem.h
- hle/coprocessor.h
hle/function_wrappers.h
hle/hle.h
hle/svc.h
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
new file mode 100644
index 0000000000..7a65669ef1
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -0,0 +1,164 @@
+// Copyright 2014 Citra Emulator Project
+// Licensed under GPLv2
+// Refer to the license.txt file included.
+
+#include "core/arm/skyeye_common/armcpu.h"
+#include "core/arm/skyeye_common/armemu.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
+
+#include "core/arm/dyncom/arm_dyncom.h"
+#include "core/arm/dyncom/arm_dyncom_interpreter.h"
+
+const static cpu_config_t s_arm11_cpu_info = {
+ "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
+};
+
+ARM_DynCom::ARM_DynCom() : ticks(0) {
+ state = std::unique_ptr<ARMul_State>(new ARMul_State);
+
+ ARMul_EmulateInit();
+ memset(state.get(), 0, sizeof(ARMul_State));
+
+ ARMul_NewState((ARMul_State*)state.get());
+
+ state->abort_model = 0;
+ state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
+ state->bigendSig = LOW;
+
+ ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
+ state->lateabtSig = LOW;
+ mmu_init(state);
+
+ // Reset the core to initial state
+ ARMul_CoProInit(state.get());
+ ARMul_Reset(state.get());
+ state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
+ state->Emulate = 3;
+
+ state->pc = state->Reg[15] = 0x00000000;
+ state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
+ state->servaddr = 0xFFFF0000;
+ state->NirqSig = HIGH;
+
+ VFPInit(state.get()); // Initialize the VFP
+
+ ARMul_EmulateInit();
+}
+
+ARM_DynCom::~ARM_DynCom() {
+}
+
+/**
+ * Set the Program Counter to an address
+ * @param addr Address to set PC to
+ */
+void ARM_DynCom::SetPC(u32 pc) {
+ state->pc = state->Reg[15] = pc;
+}
+
+/*
+ * Get the current Program Counter
+ * @return Returns current PC
+ */
+u32 ARM_DynCom::GetPC() const {
+ return state->pc;
+}
+
+/**
+ * Get an ARM register
+ * @param index Register index (0-15)
+ * @return Returns the value in the register
+ */
+u32 ARM_DynCom::GetReg(int index) const {
+ return state->Reg[index];
+}
+
+/**
+ * Set an ARM register
+ * @param index Register index (0-15)
+ * @param value Value to set register to
+ */
+void ARM_DynCom::SetReg(int index, u32 value) {
+ state->Reg[index] = value;
+}
+
+/**
+ * Get the current CPSR register
+ * @return Returns the value of the CPSR register
+ */
+u32 ARM_DynCom::GetCPSR() const {
+ return state->Cpsr;
+}
+
+/**
+ * Set the current CPSR register
+ * @param cpsr Value to set CPSR to
+ */
+void ARM_DynCom::SetCPSR(u32 cpsr) {
+ state->Cpsr = cpsr;
+}
+
+/**
+ * Returns the number of clock ticks since the last reset
+ * @return Returns number of clock ticks
+ */
+u64 ARM_DynCom::GetTicks() const {
+ return ticks;
+}
+
+/**
+ * Executes the given number of instructions
+ * @param num_instructions Number of instructions to executes
+ */
+void ARM_DynCom::ExecuteInstructions(int num_instructions) {
+ ticks += num_instructions;
+ state->NumInstrsToExecute = num_instructions;
+ InterpreterMainLoop(state.get());
+}
+
+/**
+ * Saves the current CPU context
+ * @param ctx Thread context to save
+ * @todo Do we need to save Reg[15] and NextInstr?
+ */
+void ARM_DynCom::SaveContext(ThreadContext& ctx) {
+ memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
+ memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
+
+ ctx.sp = state->Reg[13];
+ ctx.lr = state->Reg[14];
+ ctx.pc = state->pc;
+ ctx.cpsr = state->Cpsr;
+
+ ctx.fpscr = state->VFP[1];
+ ctx.fpexc = state->VFP[2];
+
+ ctx.reg_15 = state->Reg[15];
+ ctx.mode = state->NextInstr;
+}
+
+/**
+ * Loads a CPU context
+ * @param ctx Thread context to load
+ * @param Do we need to load Reg[15] and NextInstr?
+ */
+void ARM_DynCom::LoadContext(const ThreadContext& ctx) {
+ memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
+ memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
+
+ state->Reg[13] = ctx.sp;
+ state->Reg[14] = ctx.lr;
+ state->pc = ctx.pc;
+ state->Cpsr = ctx.cpsr;
+
+ state->VFP[1] = ctx.fpscr;
+ state->VFP[2] = ctx.fpexc;
+
+ state->Reg[15] = ctx.reg_15;
+ state->NextInstr = ctx.mode;
+}
+
+/// Prepare core for thread reschedule (if needed to correctly handle state)
+void ARM_DynCom::PrepareReschedule() {
+ state->NumInstrsToExecute = 0;
+}
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
new file mode 100644
index 0000000000..9f88dd139e
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -0,0 +1,90 @@
+// Copyright 2014 Citra Emulator Project
+// Licensed under GPLv2
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <memory>
+
+#include "common/common_types.h"
+
+#include "core/arm/arm_interface.h"
+#include "core/arm/skyeye_common/armdefs.h"
+
+class ARM_DynCom final : virtual public ARM_Interface {
+public:
+
+ ARM_DynCom();
+ ~ARM_DynCom();
+
+ /**
+ * Set the Program Counter to an address
+ * @param addr Address to set PC to
+ */
+ void SetPC(u32 pc);
+
+ /*
+ * Get the current Program Counter
+ * @return Returns current PC
+ */
+ u32 GetPC() const;
+
+ /**
+ * Get an ARM register
+ * @param index Register index (0-15)
+ * @return Returns the value in the register
+ */
+ u32 GetReg(int index) const;
+
+ /**
+ * Set an ARM register
+ * @param index Register index (0-15)
+ * @param value Value to set register to
+ */
+ void SetReg(int index, u32 value);
+
+ /**
+ * Get the current CPSR register
+ * @return Returns the value of the CPSR register
+ */
+ u32 GetCPSR() const;
+
+ /**
+ * Set the current CPSR register
+ * @param cpsr Value to set CPSR to
+ */
+ void SetCPSR(u32 cpsr);
+
+ /**
+ * Returns the number of clock ticks since the last reset
+ * @return Returns number of clock ticks
+ */
+ u64 GetTicks() const;
+
+ /**
+ * Saves the current CPU context
+ * @param ctx Thread context to save
+ */
+ void SaveContext(ThreadContext& ctx);
+
+ /**
+ * Loads a CPU context
+ * @param ctx Thread context to load
+ */
+ void LoadContext(const ThreadContext& ctx);
+
+ /// Prepare core for thread reschedule (if needed to correctly handle state)
+ void PrepareReschedule();
+
+ /**
+ * Executes the given number of instructions
+ * @param num_instructions Number of instructions to executes
+ */
+ void ExecuteInstructions(int num_instructions);
+
+private:
+
+ std::unique_ptr<ARMul_State> state;
+ u64 ticks;
+
+};
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
new file mode 100644
index 0000000000..5d174a08f4
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -0,0 +1,402 @@
+/* Copyright (C)
+* 2012 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+/**
+* @file arm_dyncom_dec.cpp
+* @brief Some common utility for arm decoder
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 7849
+* @date 2012-03-15
+*/
+
+#include "core/arm/skyeye_common/arm_regformat.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/dyncom/arm_dyncom_dec.h"
+
+const ISEITEM arm_instruction[] = {
+ #define VFP_DECODE
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+ #undef VFP_DECODE
+ {"srs" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005},
+ {"rfe" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a},
+ {"bkpt" , 2 , 3 , 20, 31, 0x00000e12, 4, 7, 0x00000007},
+ {"blx" , 1 , 3 , 25, 31, 0x0000007d},
+ {"cps" , 3 , 6 , 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000},
+ {"pld" , 4 , 4 , 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f},
+ {"setend" , 2 , 6 , 16, 31, 0x0000f101, 4, 7, 0x00000000},
+ {"clrex" , 1 , 6 , 0, 31, 0xf57ff01f},
+ {"rev16" , 2 , 6 , 16, 27, 0x000006bf, 4, 11, 0x000000fb},
+ {"usad8" , 3 , 6 , 20, 27, 0x00000078, 12, 15, 0x0000000f, 4, 7, 0x00000001},
+ {"sxtb" , 2 , 6 , 16, 27, 0x000006af, 4, 7, 0x00000007},
+ {"uxtb" , 2 , 6 , 16, 27, 0x000006ef, 4, 7, 0x00000007},
+ {"sxth" , 2 , 6 , 16, 27, 0x000006bf, 4, 7, 0x00000007},
+ {"sxtb16" , 2 , 6 , 16, 27, 0x0000068f, 4, 7, 0x00000007},
+ {"uxth" , 2 , 6 , 16, 27, 0x000006ff, 4, 7, 0x00000007},
+ {"uxtb16" , 2 , 6 , 16, 27, 0x000006cf, 4, 7, 0x00000007},
+ {"cpy" , 2 , 6 , 20, 27, 0x0000001a, 4, 11, 0x00000000},
+ {"uxtab" , 2 , 6 , 20, 27, 0x0000006e, 4, 9, 0x00000007},
+ {"ssub8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x0000000f},
+ {"shsub8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x0000000f},
+ {"ssubaddx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000005},
+ {"strex" , 2 , 6 , 20, 27, 0x00000018, 4, 7, 0x00000009},
+ {"strexb" , 2 , 7 , 20, 27, 0x0000001c, 4, 7, 0x00000009},
+ {"swp" , 2 , 0 , 20, 27, 0x00000010, 4, 7, 0x00000009},
+ {"swpb" , 2 , 0 , 20, 27, 0x00000014, 4, 7, 0x00000009},
+ {"ssub16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000007},
+ {"ssat16" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000003},
+ {"shsubaddx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000005},
+ {"qsubaddx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000005},
+ {"shaddsubx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000003},
+ {"shadd8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000009},
+ {"shadd16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000001},
+ {"sel" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x0000000b},
+ {"saddsubx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000003},
+ {"sadd8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000009},
+ {"sadd16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000001},
+ {"shsub16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000007},
+ {"umaal" , 2 , 6 , 20, 27, 0x00000004, 4, 7, 0x00000009},
+ {"uxtab16" , 2 , 6 , 20, 27, 0x0000006c, 4, 7, 0x00000007},
+ {"usubaddx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000005},
+ {"usub8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x0000000f},
+ {"usub16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000007},
+ {"usat16" , 2 , 6 , 20, 27, 0x0000006e, 4, 7, 0x00000003},
+ {"usada8" , 2 , 6 , 20, 27, 0x00000078, 4, 7, 0x00000001},
+ {"uqsubaddx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000005},
+ {"uqsub8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x0000000f},
+ {"uqsub16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000007},
+ {"uqaddsubx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000003},
+ {"uqadd8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000009},
+ {"uqadd16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000001},
+ {"sxtab" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000007},
+ {"uhsubaddx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000005},
+ {"uhsub8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x0000000f},
+ {"uhsub16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000007},
+ {"uhaddsubx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000003},
+ {"uhadd8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000009},
+ {"uhadd16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000001},
+ {"uaddsubx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000003},
+ {"uadd8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000009},
+ {"uadd16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000001},
+ {"sxtah" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000007},
+ {"sxtab16" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x00000007},
+ {"qadd8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000009},
+ {"bxj" , 2 , 5 , 20, 27, 0x00000012, 4, 7, 0x00000002},
+ {"clz" , 2 , 3 , 20, 27, 0x00000016, 4, 7, 0x00000001},
+ {"uxtah" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x00000007},
+ {"bx" , 2 , 2 , 20, 27, 0x00000012, 4, 7, 0x00000001},
+ {"rev" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000003},
+ {"blx" , 2 , 3 , 20, 27, 0x00000012, 4, 7, 0x00000003},
+ {"revsh" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x0000000b},
+ {"qadd" , 2 , 4 , 20, 27, 0x00000010, 4, 7, 0x00000005},
+ {"qadd16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000001},
+ {"qaddsubx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000003},
+ {"ldrex" , 2 , 0 , 20, 27, 0x00000019, 4, 7, 0x00000009},
+ {"qdadd" , 2 , 4 , 20, 27, 0x00000014, 4, 7, 0x00000005},
+ {"qdsub" , 2 , 4 , 20, 27, 0x00000016, 4, 7, 0x00000005},
+ {"qsub" , 2 , 4 , 20, 27, 0x00000012, 4, 7, 0x00000005},
+ {"ldrexb" , 2 , 7 , 20, 27, 0x0000001d, 4, 7, 0x00000009},
+ {"qsub8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x0000000f},
+ {"qsub16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000007},
+ {"smuad" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001},
+ {"smmul" , 4 , 6 , 20, 27, 0x00000075, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001},
+ {"smusd" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000001, 4, 4, 0x00000001},
+ {"smlsd" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000001, 4, 4, 0x00000001},
+ {"smlsld" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000001, 4, 4, 0x00000001},
+ {"smmla" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000000, 4, 4, 0x00000001},
+ {"smmls" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000003, 4, 4, 0x00000001},
+ {"smlald" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000000, 4, 4, 0x00000001},
+ {"smlad" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000000, 4, 4, 0x00000001},
+ {"smlaw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000000},
+ {"smulw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000002},
+ {"pkhtb" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000005},
+ {"pkhbt" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000001},
+ {"smul" , 3 , 4 , 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000},
+ {"smlalxy" , 3 , 4 , 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000},
+// {"smlal" , 2 , 4 , 21, 27, 0x00000007, 4, 7, 0x00000009},
+ {"smla" , 3 , 4 , 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000},
+ {"mcrr" , 1 , 6 , 20, 27, 0x000000c4},
+ {"mrrc" , 1 , 6 , 20, 27, 0x000000c5},
+ {"cmp" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000015},
+ {"tst" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000011},
+ {"teq" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000013},
+ {"cmn" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000017},
+ {"smull" , 2 , 0 , 21, 27, 0x00000006, 4, 7, 0x00000009},
+ {"umull" , 2 , 0 , 21, 27, 0x00000004, 4, 7, 0x00000009},
+ {"umlal" , 2 , 0 , 21, 27, 0x00000005, 4, 7, 0x00000009},
+ {"smlal" , 2 , 0 , 21, 27, 0x00000007, 4, 7, 0x00000009},
+ {"mul" , 2 , 0 , 21, 27, 0x00000000, 4, 7, 0x00000009},
+ {"mla" , 2 , 0 , 21, 27, 0x00000001, 4, 7, 0x00000009},
+ {"ssat" , 2 , 6 , 21, 27, 0x00000035, 4, 5, 0x00000001},
+ {"usat" , 2 , 6 , 21, 27, 0x00000037, 4, 5, 0x00000001},
+ {"mrs" , 4 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000000, 16, 19, 0x0000000f, 0, 11, 0x00000000},
+ {"msr" , 3 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000002, 4, 7, 0x00000000},
+ {"and" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000000},
+ {"bic" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000e},
+ {"ldm" , 3 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000005, 15, 15, 0x00000000},
+ {"eor" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000001},
+ {"add" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000004},
+ {"rsb" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000003},
+ {"rsc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000007},
+ {"sbc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000006},
+ {"adc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000005},
+ {"sub" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000002},
+ {"orr" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000c},
+ {"mvn" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000f},
+ {"mov" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000d},
+ {"stm" , 2 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000004},
+ {"ldm" , 4 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000001, 20, 20, 0x00000001, 15, 15, 0x00000001},
+ {"ldrsh" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000f},
+ {"stm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000000},
+ {"ldm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000001},
+ {"ldrsb" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000d},
+ {"strd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000f},
+ {"ldrh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000b},
+ {"strh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000b},
+ {"ldrd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000d},
+ {"strt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000002},
+ {"strbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000006},
+ {"ldrbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000007},
+ {"ldrt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003},
+ {"mrc" , 3 , 6 , 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001},
+ {"mcr" , 3 , 0 , 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001},
+ {"msr" , 2 , 0 , 23, 27, 0x00000006, 20, 21, 0x00000002},
+ {"ldrb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001},
+ {"strb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000},
+ {"ldr" , 4 , 0 , 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001},
+ {"ldrcond" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001},
+ {"str" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000000},
+ {"cdp" , 2 , 0 , 24, 27, 0x0000000e, 4, 4, 0x00000000},
+ {"stc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000000},
+ {"ldc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000001},
+ {"swi" , 1 , 0 , 24, 27, 0x0000000f},
+ {"bbl" , 1 , 0 , 25, 27, 0x00000005},
+};
+
+const ISEITEM arm_exclusion_code[] = {
+ #define VFP_DECODE_EXCLUSION
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+ #undef VFP_DECODE_EXCLUSION
+ {"srs" , 0 , 6 , 0},
+ {"rfe" , 0 , 6 , 0},
+ {"bkpt" , 0 , 3 , 0},
+ {"blx" , 0 , 3 , 0},
+ {"cps" , 0 , 6 , 0},
+ {"pld" , 0 , 4 , 0},
+ {"setend" , 0 , 6 , 0},
+ {"clrex" , 0 , 6 , 0},
+ {"rev16" , 0 , 6 , 0},
+ {"usad8" , 0 , 6 , 0},
+ {"sxtb" , 0 , 6 , 0},
+ {"uxtb" , 0 , 6 , 0},
+ {"sxth" , 0 , 6 , 0},
+ {"sxtb16" , 0 , 6 , 0},
+ {"uxth" , 0 , 6 , 0},
+ {"uxtb16" , 0 , 6 , 0},
+ {"cpy" , 0 , 6 , 0},
+ {"uxtab" , 0 , 6 , 0},
+ {"ssub8" , 0 , 6 , 0},
+ {"shsub8" , 0 , 6 , 0},
+ {"ssubaddx" , 0 , 6 , 0},
+ {"strex" , 0 , 6 , 0},
+ {"strexb" , 0 , 7 , 0},
+ {"swp" , 0 , 0 , 0},
+ {"swpb" , 0 , 0 , 0},
+ {"ssub16" , 0 , 6 , 0},
+ {"ssat16" , 0 , 6 , 0},
+ {"shsubaddx" , 0 , 6 , 0},
+ {"qsubaddx" , 0 , 6 , 0},
+ {"shaddsubx" , 0 , 6 , 0},
+ {"shadd8" , 0 , 6 , 0},
+ {"shadd16" , 0 , 6 , 0},
+ {"sel" , 0 , 6 , 0},
+ {"saddsubx" , 0 , 6 , 0},
+ {"sadd8" , 0 , 6 , 0},
+ {"sadd16" , 0 , 6 , 0},
+ {"shsub16" , 0 , 6 , 0},
+ {"umaal" , 0 , 6 , 0},
+ {"uxtab16" , 0 , 6 , 0},
+ {"usubaddx" , 0 , 6 , 0},
+ {"usub8" , 0 , 6 , 0},
+ {"usub16" , 0 , 6 , 0},
+ {"usat16" , 0 , 6 , 0},
+ {"usada8" , 0 , 6 , 0},
+ {"uqsubaddx" , 0 , 6 , 0},
+ {"uqsub8" , 0 , 6 , 0},
+ {"uqsub16" , 0 , 6 , 0},
+ {"uqaddsubx" , 0 , 6 , 0},
+ {"uqadd8" , 0 , 6 , 0},
+ {"uqadd16" , 0 , 6 , 0},
+ {"sxtab" , 0 , 6 , 0},
+ {"uhsubaddx" , 0 , 6 , 0},
+ {"uhsub8" , 0 , 6 , 0},
+ {"uhsub16" , 0 , 6 , 0},
+ {"uhaddsubx" , 0 , 6 , 0},
+ {"uhadd8" , 0 , 6 , 0},
+ {"uhadd16" , 0 , 6 , 0},
+ {"uaddsubx" , 0 , 6 , 0},
+ {"uadd8" , 0 , 6 , 0},
+ {"uadd16" , 0 , 6 , 0},
+ {"sxtah" , 0 , 6 , 0},
+ {"sxtab16" , 0 , 6 , 0},
+ {"qadd8" , 0 , 6 , 0},
+ {"bxj" , 0 , 5 , 0},
+ {"clz" , 0 , 3 , 0},
+ {"uxtah" , 0 , 6 , 0},
+ {"bx" , 0 , 2 , 0},
+ {"rev" , 0 , 6 , 0},
+ {"blx" , 0 , 3 , 0},
+ {"revsh" , 0 , 6 , 0},
+ {"qadd" , 0 , 4 , 0},
+ {"qadd16" , 0 , 6 , 0},
+ {"qaddsubx" , 0 , 6 , 0},
+ {"ldrex" , 0 , 0 , 0},
+ {"qdadd" , 0 , 4 , 0},
+ {"qdsub" , 0 , 4 , 0},
+ {"qsub" , 0 , 4 , 0},
+ {"ldrexb" , 0 , 7 , 0},
+ {"qsub8" , 0 , 6 , 0},
+ {"qsub16" , 0 , 6 , 0},
+ {"smuad" , 0 , 6 , 0},
+ {"smmul" , 0 , 6 , 0},
+ {"smusd" , 0 , 6 , 0},
+ {"smlsd" , 0 , 6 , 0},
+ {"smlsld" , 0 , 6 , 0},
+ {"smmla" , 0 , 6 , 0},
+ {"smmls" , 0 , 6 , 0},
+ {"smlald" , 0 , 6 , 0},
+ {"smlad" , 0 , 6 , 0},
+ {"smlaw" , 0 , 4 , 0},
+ {"smulw" , 0 , 4 , 0},
+ {"pkhtb" , 0 , 6 , 0},
+ {"pkhbt" , 0 , 6 , 0},
+ {"smul" , 0 , 4 , 0},
+ {"smlal" , 0 , 4 , 0},
+ {"smla" , 0 , 4 , 0},
+ {"mcrr" , 0 , 6 , 0},
+ {"mrrc" , 0 , 6 , 0},
+ {"cmp" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"tst" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"teq" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"cmn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"smull" , 0 , 0 , 0},
+ {"umull" , 0 , 0 , 0},
+ {"umlal" , 0 , 0 , 0},
+ {"smlal" , 0 , 0 , 0},
+ {"mul" , 0 , 0 , 0},
+ {"mla" , 0 , 0 , 0},
+ {"ssat" , 0 , 6 , 0},
+ {"usat" , 0 , 6 , 0},
+ {"mrs" , 0 , 0 , 0},
+ {"msr" , 0 , 0 , 0},
+ {"and" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"bic" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"ldm" , 0 , 0 , 0},
+ {"eor" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"add" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"rsb" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"rsc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"sbc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"adc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"sub" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"orr" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"mvn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"mov" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000},
+ {"stm" , 0 , 0 , 0},
+ {"ldm" , 0 , 0 , 0},
+ {"ldrsh" , 0 , 2 , 0},
+ {"stm" , 0 , 0 , 0},
+ {"ldm" , 0 , 0 , 0},
+ {"ldrsb" , 0 , 2 , 0},
+ {"strd" , 0 , 4 , 0},
+ {"ldrh" , 0 , 0 , 0},
+ {"strh" , 0 , 0 , 0},
+ {"ldrd" , 0 , 4 , 0},
+ {"strt" , 0 , 0 , 0},
+ {"strbt" , 0 , 0 , 0},
+ {"ldrbt" , 0 , 0 , 0},
+ {"ldrt" , 0 , 0 , 0},
+ {"mrc" , 0 , 6 , 0},
+ {"mcr" , 0 , 0 , 0},
+ {"msr" , 0 , 0 , 0},
+ {"ldrb" , 0 , 0 , 0},
+ {"strb" , 0 , 0 , 0},
+ {"ldr" , 0 , 0 , 0},
+ {"ldrcond" , 1 , 0 , 28, 31, 0x0000000e},
+ {"str" , 0 , 0 , 0},
+ {"cdp" , 0 , 0 , 0},
+ {"stc" , 0 , 0 , 0},
+ {"ldc" , 0 , 0 , 0},
+ {"swi" , 0 , 0 , 0},
+ {"bbl" , 0 , 0 , 0},
+ {"bl_1_thumb", 0, INVALID, 0},/* should be table[-4] */
+ {"bl_2_thumb", 0, INVALID, 0}, /* should be located at the end of the table[-3] */
+ {"blx_1_thumb", 0, INVALID, 0}, /* should be located at table[-2] */
+ {"invalid", 0, INVALID, 0}
+};
+
+int decode_arm_instr(uint32_t instr, int32_t *idx)
+{
+ int n = 0;
+ int base = 0;
+ int ret = DECODE_FAILURE;
+ int i = 0;
+ int instr_slots = sizeof(arm_instruction)/sizeof(ISEITEM);
+ for (i = 0; i < instr_slots; i++)
+ {
+// ret = DECODE_SUCCESS;
+ n = arm_instruction[i].attribute_value;
+ base = 0;
+ while (n) {
+ if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) {
+ /* clrex */
+ if (instr != arm_instruction[i].content[base + 2]) {
+ break;
+ }
+ } else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) {
+ break;
+ }
+ base += 3;
+ n --;
+ }
+ //All conditions is satisfied.
+ if (n == 0)
+ ret = DECODE_SUCCESS;
+
+ if (ret == DECODE_SUCCESS) {
+ n = arm_exclusion_code[i].attribute_value;
+ if (n != 0) {
+ base = 0;
+ while (n) {
+ if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) {
+ break; }
+ base += 3;
+ n --;
+ }
+ //All conditions is satisfied.
+ if (n == 0)
+ ret = DECODE_FAILURE;
+ }
+ }
+
+ if (ret == DECODE_SUCCESS) {
+ *idx = i;
+ return ret;
+ }
+ }
+ return ret;
+}
+
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
new file mode 100644
index 0000000000..19d94f3694
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -0,0 +1,155 @@
+/* Copyright (C)
+* 2012 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+
+/**
+* @file arm_dyncom_dec.h
+* @brief Some common utility for arm instruction decoder
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 7849
+* @date 2012-03-15
+*/
+
+#ifndef __ARM_DYNCOM_DEC__
+#define __ARM_DYNCOM_DEC__
+
+#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
+#define BIT(n) ((instr >> (n)) & 1)
+#define BAD do{printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); /*exit(0);*/}while(0);
+#define ptr_N cpu->ptr_N
+#define ptr_Z cpu->ptr_Z
+#define ptr_C cpu->ptr_C
+#define ptr_V cpu->ptr_V
+#define ptr_I cpu->ptr_I
+#define ptr_T cpu->ptr_T
+#define ptr_CPSR cpu->ptr_gpr[16]
+
+/* for MUL instructions */
+/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
+#define RDHi ((instr >> 16) & 0xF)
+/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
+#define RDLo ((instr >> 12) & 0xF)
+/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
+#define MUL_RD ((instr >> 16) & 0xF)
+/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
+#define MUL_RN ((instr >> 12) & 0xF)
+/*xxxx xxxx xxxx xxxx xxxx 1111 xxxx xxxx */
+#define RS ((instr >> 8) & 0xF)
+
+/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */
+#define RD ((instr >> 12) & 0xF)
+/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */
+#define RN ((instr >> 16) & 0xF)
+/*xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 */
+#define RM (instr & 0xF)
+#define BIT(n) ((instr >> (n)) & 1)
+#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
+
+/* CP15 registers */
+#define OPCODE_1 BITS(21, 23)
+#define CRn BITS(16, 19)
+#define CRm BITS(0, 3)
+#define OPCODE_2 BITS(5, 7)
+
+/*xxxx xx1x xxxx xxxx xxxx xxxx xxxx xxxx */
+#define I BIT(25)
+/*xxxx xxxx xxx1 xxxx xxxx xxxx xxxx xxxx */
+#define S BIT(20)
+
+#define SHIFT BITS(5,6)
+#define SHIFT_IMM BITS(7,11)
+#define IMMH BITS(8,11)
+#define IMML BITS(0,3)
+
+#define LSPBIT BIT(24)
+#define LSUBIT BIT(23)
+#define LSBBIT BIT(22)
+#define LSWBIT BIT(21)
+#define LSLBIT BIT(20)
+#define LSSHBITS BITS(5,6)
+#define OFFSET12 BITS(0,11)
+#define SBIT BIT(20)
+#define DESTReg (BITS (12, 15))
+
+/* they are in unused state, give a corrent value when using */
+#define IS_V5E 0
+#define IS_V5 0
+#define IS_V6 0
+#define LHSReg 0
+
+/* temp define the using the pc reg need implement a flow */
+#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2))
+
+#define OPERAND operand(cpu,instr,bb,NULL)
+#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco)
+#define BOPERAND boperand(instr)
+
+#define CHECK_RN_PC (RN==15? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)):R(RN))
+#define CHECK_RN_PC_WA (RN==15? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)):R(RN))
+
+#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE))))
+
+int decode_arm_instr(uint32_t instr, int32_t *idx);
+
+enum DECODE_STATUS {
+ DECODE_SUCCESS,
+ DECODE_FAILURE
+};
+
+struct instruction_set_encoding_item {
+ const char *name;
+ int attribute_value;
+ int version;
+ u32 content[21];
+};
+
+typedef struct instruction_set_encoding_item ISEITEM;
+
+#define RECORD_WB(value, flag) {cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag;}
+#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag)
+
+#define EXECUTE_WB(base_reg) {if(cpu->dyncom_engine->wb_flag) \
+ LET(base_reg, cpu->dyncom_engine->wb_value);}
+inline int get_reg_count(uint32_t instr){
+ int i = BITS(0,15);
+ int count = 0;
+ while(i){
+ if(i & 1)
+ count ++;
+ i = i >> 1;
+ }
+ return count;
+}
+
+enum ARMVER {
+ INVALID = 0,
+ ARMALL,
+ ARMV4,
+ ARMV4T,
+ ARMV5T,
+ ARMV5TE,
+ ARMV5TEJ,
+ ARMV6,
+ ARM1176JZF_S,
+ ARMVFP2,
+ ARMVFP3
+};
+
+//extern const INSTRACT arm_instruction_action[];
+extern const ISEITEM arm_instruction[];
+
+#endif
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
new file mode 100644
index 0000000000..8739b8c14e
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -0,0 +1,6559 @@
+/* Copyright (C)
+* 2012 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+/**
+* @file arm_dyncom_interpreter.cpp
+* @brief The fast interpreter for arm
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 7849
+* @date 2012-03-15
+*/
+
+#define CITRA_IGNORE_EXIT(x)
+
+#include <algorithm>
+#include <map>
+#include <stdio.h>
+#include <assert.h>
+#include <cstdio>
+#include <vector>
+
+using namespace std;
+
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armmmu.h"
+#include "arm_dyncom_thumb.h"
+#include "arm_dyncom_run.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
+/* shenoubang 2012-6-14 */
+#ifdef __WIN32__
+#include "bank_defs.h"
+#endif
+
+#include "core/mem_map.h"
+#include "core/hle/hle.h"
+
+enum {
+ COND = (1 << 0),
+ NON_BRANCH = (1 << 1),
+ DIRECT_BRANCH = (1 << 2),
+ INDIRECT_BRANCH = (1 << 3),
+ CALL = (1 << 4),
+ RET = (1 << 5),
+ END_OF_PAGE = (1 << 6),
+ THUMB = (1 << 7)
+};
+
+#define USER_MODE_OPT 1
+#define HYBRID_MODE 0 // Enable for JIT mode
+
+#define THRESHOLD 1000
+#define DURATION 500
+//#define PRINT_PROFILE_INFO
+
+#define CHECK_RS if(RS == 15) rs += 8
+#define CHECK_RM if(RM == 15) rm += 8
+
+//#define BITS(s, a, b) (((s) >> (a)) & ((1 << (1 + (b) - (a))) - 1))
+#undef BITS
+#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
+#define BIT(s, n) ((s >> (n)) & 1)
+#define RM BITS(sht_oper, 0, 3)
+#define RS BITS(sht_oper, 8, 11)
+
+#define glue(x, y) x ## y
+#define DPO(s) glue(DataProcessingOperands, s)
+#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i))
+#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i))
+#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32)
+#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32)
+
+//#define rotr(x,n) ((((x)>>(n))&((1<<(sizeof(x) * 8)-1))|(x<<(sizeof(x)*8-n))))
+//#define rotl(x,n) ((((x)<<(n))&(-(1<<(n))))|(((x)>>(sizeof(x)*8-n))&((1<<(n))-1)))
+#define rotr(x,n) ( (x >> n) | ((x & ((1 << (n + 1)) - 1)) << (32 - n)) )
+
+extern void switch_mode(arm_core_t *core, uint32_t mode);
+//extern bool InAPrivilegedMode(arm_core_t *core);
+
+typedef arm_core_t arm_processor;
+typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper);
+
+/* exclusive memory access */
+static int exclusive_detect(ARMul_State* state, ARMword addr){
+ int i;
+ #if 0
+ for(i = 0; i < 128; i++){
+ if(state->exclusive_tag_array[i] == addr)
+ return 0;
+ }
+ #endif
+ if(state->exclusive_tag == addr)
+ return 0;
+ else
+ return -1;
+}
+
+static void add_exclusive_addr(ARMul_State* state, ARMword addr){
+ int i;
+ #if 0
+ for(i = 0; i < 128; i++){
+ if(state->exclusive_tag_array[i] == 0xffffffff){
+ state->exclusive_tag_array[i] = addr;
+ //DEBUG_LOG(ARM11, "In %s, add addr 0x%x\n", __func__, addr);
+ return;
+ }
+ }
+ DEBUG_LOG(ARM11, "In %s ,can not monitor the addr, out of array\n", __FUNCTION__);
+ #endif
+ state->exclusive_tag = addr;
+ return;
+}
+
+static void remove_exclusive(ARMul_State* state, ARMword addr){
+ #if 0
+ int i;
+ for(i = 0; i < 128; i++){
+ if(state->exclusive_tag_array[i] == addr){
+ state->exclusive_tag_array[i] = 0xffffffff;
+ //DEBUG_LOG(ARM11, "In %s, remove addr 0x%x\n", __func__, addr);
+ return;
+ }
+ }
+ #endif
+ state->exclusive_tag = 0xFFFFFFFF;
+}
+
+
+unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int immed_8 = BITS(sht_oper, 0, 7);
+ unsigned int rotate_imm = BITS(sht_oper, 8, 11);
+// DEBUG_LOG(ARM11, "immed_8 is %x\n", immed_8);
+// DEBUG_LOG(ARM11, "rotate_imm is %x\n", rotate_imm);
+ unsigned int shifter_operand = ROTATE_RIGHT_32(immed_8, rotate_imm * 2);//ROTATE_RIGHT_32(immed_8, rotate_imm * 2);
+// DEBUG_LOG(ARM11, "shifter_operand : %x\n", shifter_operand);
+ /* set c flag */
+ if (rotate_imm == 0)
+ cpu->shifter_carry_out = cpu->CFlag;
+ else
+ cpu->shifter_carry_out = BIT(shifter_operand, 31);
+ return shifter_operand;
+}
+
+unsigned int DPO(Register)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ return shifter_operand;
+}
+
+unsigned int DPO(LogicalShiftLeftByImmediate)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ int shift_imm = BITS(sht_oper, 7, 11);
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand;
+ if (shift_imm == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ } else {
+ shifter_operand = rm << shift_imm;
+ cpu->shifter_carry_out = BIT(rm, 32 - shift_imm);
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(LogicalShiftLeftByRegister)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ int shifter_operand;
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ unsigned int rs = CHECK_READ_REG15(cpu, RS);
+ //if (RM == 15) rm += 8;
+ //if (RS == 15) rs += 8;
+ if (BITS(rs, 0, 7) == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ } else if (BITS(rs, 0, 7) < 32) {
+ shifter_operand = rm << BITS(rs, 0, 7);
+ cpu->shifter_carry_out = BIT(rm, 32 - BITS(rs, 0, 7));
+ } else if (BITS(rs, 0, 7) == 32) {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = BIT(rm, 0);
+ } else {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = 0;
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(LogicalShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ //unsigned int rm = cpu->Reg[RM];
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand;
+ int shift_imm = BITS(sht_oper, 7, 11);
+ if (shift_imm == 0) {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ } else {
+ shifter_operand = rm >> shift_imm;
+ cpu->shifter_carry_out = BIT(rm, shift_imm - 1);
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(LogicalShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int rs = CHECK_READ_REG15(cpu, RS);
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RS == 15) rs += 8;
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand;
+ if (BITS(rs, 0, 7) == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ } else if (BITS(rs, 0, 7) < 32) {
+ shifter_operand = rm >> BITS(rs, 0, 7);
+ cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 7) - 1);
+ } else if (BITS(rs, 0, 7) == 32) {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ } else {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = 0;
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ //unsigned int rm = cpu->Reg[RM];
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand;
+ int shift_imm = BITS(sht_oper, 7, 11);
+ if (shift_imm == 0) {
+ if (BIT(rm, 31)) {
+ shifter_operand = 0;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ } else {
+ shifter_operand = 0xFFFFFFFF;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ }
+ } else {
+ shifter_operand = static_cast<int>(rm) >> shift_imm;
+ cpu->shifter_carry_out = BIT(rm, shift_imm - 1);
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(ArithmeticShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ //unsigned int rs = cpu->Reg[RS];
+ unsigned int rs = CHECK_READ_REG15(cpu, RS);
+ //unsigned int rm = cpu->Reg[RM];
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RS == 15) rs += 8;
+ //if (RM == 15) rm += 8;
+ unsigned int shifter_operand;
+ if (BITS(rs, 0, 7) == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ } else if (BITS(rs, 0, 7) < 32) {
+ shifter_operand = static_cast<int>(rm) >> BITS(rs, 0, 7);
+ cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 7) - 1);
+ } else {
+ if (BIT(rm, 31) == 0) {
+ shifter_operand = 0;
+ } else
+ shifter_operand = 0xffffffff;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(RotateRightByImmediate)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int shifter_operand;
+ //unsigned int rm = cpu->Reg[RM];
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ int shift_imm = BITS(sht_oper, 7, 11);
+ if (shift_imm == 0) {
+ shifter_operand = (cpu->CFlag << 31) |
+ (rm >> 1);
+ cpu->shifter_carry_out = BIT(rm, 0);
+ } else {
+ shifter_operand = ROTATE_RIGHT_32(rm, shift_imm);
+ cpu->shifter_carry_out = BIT(rm, shift_imm - 1);
+ }
+ return shifter_operand;
+}
+
+unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_oper)
+{
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int rm = CHECK_READ_REG15(cpu, RM);
+ //if (RM == 15) rm += 8;
+ unsigned int rs = CHECK_READ_REG15(cpu, RS);
+ //if (RS == 15) rs += 8;
+ unsigned int shifter_operand;
+ if (BITS(rs, 0, 7) == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = cpu->CFlag;
+ } else if (BITS(rs, 0, 4) == 0) {
+ shifter_operand = rm;
+ cpu->shifter_carry_out = BIT(rm, 31);
+ } else {
+ shifter_operand = ROTATE_RIGHT_32(rm, BITS(rs, 0, 4));
+ cpu->shifter_carry_out = BIT(rm, BITS(rs, 0, 4) - 1);
+ }
+ #if 0
+ if (cpu->icounter >= 20371544) {
+ DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ DEBUG_LOG(ARM11, "RM:%d\nRS:%d\n", RM, RS);
+ DEBUG_LOG(ARM11, "rm:0x%08x\nrs:0x%08x\n", cpu->Reg[RM], cpu->Reg[RS]);
+ }
+ #endif
+ return shifter_operand;
+}
+
+//typedef unsigned int (*get_addr_fp_t)(arm_processor *cpu);
+typedef struct _MiscImmeData {
+ unsigned int U;
+ unsigned int Rn;
+ unsigned int offset_8;
+} MiscLSData;
+
+typedef struct _MiscRegData {
+ unsigned int U;
+ unsigned int Rn;
+ unsigned int Rm;
+} MiscRegData;
+
+typedef struct _MiscImmePreIdx {
+ unsigned int offset_8;
+ unsigned int U;
+ unsigned int Rn;
+} MiscImmePreIdx;
+
+typedef struct _MiscRegPreIdx {
+ unsigned int U;
+ unsigned int Rn;
+ unsigned int Rm;
+} MiscRegPreIdx;
+
+typedef struct _MiscImmePstIdx {
+ unsigned int offset_8;
+ unsigned int U;
+ unsigned int Rn;
+} MIscImmePstIdx;
+
+typedef struct _MiscRegPstIdx {
+ unsigned int Rn;
+ unsigned int Rm;
+ unsigned int U;
+} MiscRegPstIdx;
+
+typedef struct _LSWordorUnsignedByte {
+} LDnST;
+
+#if USER_MODE_OPT
+static inline fault_t interpreter_read_memory(addr_t virt_addr, addr_t phys_addr, uint32_t &value, uint32_t size){
+ switch(size) {
+ case 8:
+ value = Memory::Read8(virt_addr);
+ break;
+ case 16:
+ value = Memory::Read16(virt_addr);
+ break;
+ case 32:
+ value = Memory::Read32(virt_addr);
+ break;
+ }
+ return NO_FAULT;
+}
+
+//static inline void interpreter_write_memory(void *mem_ptr, uint32_t offset, uint32_t value, int size)
+static inline fault_t interpreter_write_memory(addr_t virt_addr, addr_t phys_addr, uint32_t value, uint32_t size)
+{
+ switch(size) {
+ case 8:
+ Memory::Write8(virt_addr, value & 0xff);
+ break;
+ case 16:
+ Memory::Write16(virt_addr, value & 0xffff);
+ break;
+ case 32:
+ Memory::Write32(virt_addr, value);
+ break;
+ }
+ return NO_FAULT;
+}
+
+static inline fault_t check_address_validity(arm_core_t *core, addr_t virt_addr, addr_t *phys_addr, uint32_t rw){
+ *phys_addr = virt_addr;
+ return NO_FAULT;
+}
+
+#else
+fault_t interpreter_read_memory(cpu_t *cpu, addr_t virt_addr, addr_t phys_addr, uint32_t &value, uint32_t size);
+fault_t interpreter_write_memory(cpu_t *cpu, addr_t virt_addr, addr_t phys_addr, uint32_t value, uint32_t size);
+fault_t interpreter_fetch(cpu_t *cpu, addr_t virt_addr, uint32_t &value, uint32_t size);
+fault_t check_address_validity(arm_core_t *core, addr_t virt_addr, addr_t *phys_addr, uint32_t rw, tlb_type_t access_type = DATA_TLB);
+#endif
+
+typedef fault_t (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw);
+
+typedef struct _ldst_inst {
+ unsigned int inst;
+ get_addr_fp_t get_addr;
+} ldst_inst;
+#define DEBUG_MSG DEBUG_LOG(ARM11, "in %s %d\n", __FUNCTION__, __LINE__); \
+ DEBUG_LOG(ARM11, "inst is %x\n", inst); \
+ CITRA_IGNORE_EXIT(0)
+
+int CondPassed(arm_processor *cpu, unsigned int cond);
+#define LnSWoUB(s) glue(LnSWoUB, s)
+#define MLnS(s) glue(MLnS, s)
+#define LdnStM(s) glue(LdnStM, s)
+
+#define W_BIT BIT(inst, 21)
+#define U_BIT BIT(inst, 23)
+#define I_BIT BIT(inst, 25)
+#define P_BIT BIT(inst, 24)
+#define OFFSET_12 BITS(inst, 0, 11)
+fault_t LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int addr;
+ fault_t fault;
+ if (U_BIT) {
+ addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12;
+ } else {
+ addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12;
+ }
+ //if (Rn == 15) rn += 8;
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ return fault;
+// return addr;
+}
+
+fault_t LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rm == 15) rm += 8;
+ unsigned int addr;
+ if (U_BIT) {
+ addr = rn + rm;
+ } else {
+ addr = rn - rm;
+ }
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ return fault;
+}
+
+fault_t LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) addr += 8;
+
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (U_BIT) {
+ cpu->Reg[Rn] += OFFSET_12;
+ } else {
+ cpu->Reg[Rn] -= OFFSET_12;
+ }
+ return fault;
+}
+
+fault_t LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int addr;
+ if (U_BIT) {
+ addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12;
+ } else {
+ addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12;
+ }
+ #if 0
+ if (Rn == 15) {
+ addr += 8;
+ }
+ #endif
+
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ cpu->Reg[Rn] = addr;
+ }
+ return fault;
+}
+
+fault_t MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int addr;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rn == 15) rn += 8;
+ //if (Rm == 15) rm += 8;
+ if (U_BIT) {
+ addr = rn + rm;
+ } else
+ addr = rn - rm;
+ if(BIT(inst, 20)){ /* L BIT */
+ }
+ if(BIT(inst, 6)){ /* Sign Bit */
+ }
+ if(BIT(inst, 5)){ /* Half Bit */
+ }
+
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ cpu->Reg[Rn] = addr;
+ }
+ return fault;
+}
+
+fault_t LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rm == 15) rm += 8;
+ unsigned int addr;
+ if (U_BIT) {
+ addr = rn + rm;
+ } else {
+ addr = rn - rm;
+ }
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if(fault)
+ return fault;
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ cpu->Reg[Rn] = addr;
+ }
+ return fault;
+}
+fault_t LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int shift = BITS(inst, 5, 6);
+ unsigned int shift_imm = BITS(inst, 7, 11);
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int index;
+ unsigned int addr;
+
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rm == 15) rm += 8;
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ switch (shift) {
+ case 0:
+ //DEBUG_MSG;
+ index = rm << shift_imm;
+ break;
+ case 1:
+// DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = 0;
+ } else {
+ index = rm >> shift_imm;
+ }
+ break;
+ case 2:
+ DEBUG_MSG;
+ break;
+ case 3:
+ DEBUG_MSG;
+ break;
+ }
+ if (U_BIT) {
+ addr = rn + index;
+ } else
+ addr = rn - index;
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if(fault)
+ return fault;
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ cpu->Reg[Rn] = addr;
+ }
+
+ return fault;
+}
+
+fault_t LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int shift = BITS(inst, 5, 6);
+ unsigned int shift_imm = BITS(inst, 7, 11);
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int index;
+ unsigned int addr;
+
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rm == 15) rm += 8;
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ addr = rn;
+ switch (shift) {
+ case 0:
+ //DEBUG_MSG;
+ index = rm << shift_imm;
+ break;
+ case 1:
+// DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = 0;
+ } else {
+ index = rm >> shift_imm;
+ }
+ break;
+ case 2:
+ DEBUG_MSG;
+ break;
+ case 3:
+ DEBUG_MSG;
+ break;
+ }
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if(fault)
+ return fault;
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ if (U_BIT)
+ cpu->Reg[Rn] += index;
+ else
+ cpu->Reg[Rn] -= index;
+ }
+
+ return fault;
+}
+
+fault_t LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+
+ unsigned int addr = rn;
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ if (U_BIT) {
+ cpu->Reg[Rn] += rm;
+ } else {
+ cpu->Reg[Rn] -= rm;
+ }
+ }
+ return fault;
+}
+
+fault_t MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int immedL = BITS(inst, 0, 3);
+ unsigned int immedH = BITS(inst, 8, 11);
+
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int addr;
+
+ unsigned int offset_8 = (immedH << 4) | immedL;
+ if (U_BIT) {
+ addr = CHECK_READ_REG15_WA(cpu, Rn) + offset_8;
+ } else
+ addr = CHECK_READ_REG15_WA(cpu, Rn) - offset_8;
+ #if 0
+ if (Rn == 15) {
+ addr += 8;
+ }
+ #endif
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ return fault;
+}
+
+fault_t MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int addr;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rn == 15) rn += 8;
+ //if (Rm == 15) rm += 8;
+ if (U_BIT) {
+ addr = rn + rm;
+ } else
+ addr = rn - rm;
+ if(BIT(inst, 20)){ /* L BIT */
+ }
+ if(BIT(inst, 6)){ /* Sign Bit */
+ }
+ if(BIT(inst, 5)){ /* Half Bit */
+ }
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ return fault;
+}
+
+fault_t MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int immedH = BITS(inst, 8, 11);
+ unsigned int immedL = BITS(inst, 0, 3);
+ unsigned int addr;
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+
+// DEBUG_LOG(ARM11, "in %s\n", __FUNCTION__);
+ unsigned int offset_8 = (immedH << 4) | immedL;
+ if (U_BIT) {
+ addr = rn + offset_8;
+ } else
+ addr = rn - offset_8;
+
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ cpu->Reg[Rn] = addr;
+ }
+ return fault;
+}
+
+fault_t MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int immedH = BITS(inst, 8, 11);
+ unsigned int immedL = BITS(inst, 0, 3);
+ unsigned int addr;
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ addr = rn;
+
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ unsigned int offset_8 = (immedH << 4) | immedL;
+ if (U_BIT) {
+ rn += offset_8;
+ } else {
+ rn -= offset_8;
+ }
+ cpu->Reg[Rn] = rn;
+ }
+
+ return fault;
+}
+fault_t MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+
+ unsigned int addr = rn;
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31))) {
+ if (U_BIT) {
+ cpu->Reg[Rn] += rm;
+ } else {
+ cpu->Reg[Rn] -= rm;
+ }
+ }
+ return fault;
+}
+
+fault_t LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int i = BITS(inst, 0, 15);
+ int count = 0;
+ while(i) {
+ if(i & 1) count ++;
+ i = i >> 1;
+ }
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ unsigned int start_addr = rn - count * 4;
+ unsigned int end_addr = rn - 4;
+
+ fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
+ virt_addr = end_addr;
+ if (fault) return fault;
+
+ fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
+ virt_addr = start_addr;
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
+ cpu->Reg[Rn] -= count * 4;
+ }
+
+ return fault;
+}
+
+fault_t LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int i = BITS(inst, 0, 15);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ int count = 0;
+ while(i) {
+ if(i & 1) count ++;
+ i = i >> 1;
+ }
+
+ unsigned int start_addr = rn + 4;
+ unsigned int end_addr = rn + count * 4;
+
+ fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
+ virt_addr = end_addr;
+ if (fault) return fault;
+
+ fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
+ virt_addr = start_addr;
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
+ cpu->Reg[Rn] += count * 4;
+ }
+ return fault;
+}
+
+fault_t LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int i = BITS(inst, 0, 15);
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ int count = 0;
+ while(i) {
+ if(i & 1) count ++;
+ i = i >> 1;
+ }
+ //if (Rn == 15) rn += 8;
+ unsigned int start_addr = rn;
+ unsigned int end_addr = rn + count * 4 - 4;
+
+ fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
+ virt_addr = end_addr;
+ if (fault) return fault;
+
+ fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
+ virt_addr = start_addr;
+ if (fault) return fault;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
+ cpu->Reg[Rn] += count * 4;
+ }
+ return fault;
+}
+
+fault_t LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int i = BITS(inst, 0, 15);
+ int count = 0;
+ while(i) {
+ if(i & 1) count ++;
+ i = i >> 1;
+ }
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ unsigned int start_addr = rn - count * 4 + 4;
+ unsigned int end_addr = rn;
+
+ fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
+ virt_addr = end_addr;
+ if (fault) return fault;
+
+ fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
+ if (fault) return fault;
+ virt_addr = start_addr;
+
+ if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
+ cpu->Reg[Rn] -= count * 4;
+ }
+ return fault;
+}
+
+fault_t LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw)
+{
+ fault_t fault;
+ unsigned int shift = BITS(inst, 5, 6);
+ unsigned int shift_imm = BITS(inst, 7, 11);
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int Rm = BITS(inst, 0, 3);
+ unsigned int index;
+ unsigned int addr;
+
+ unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
+ //if (Rm == 15) rm += 8;
+ unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
+ //if (Rn == 15) rn += 8;
+ switch (shift) {
+ case 0:
+ //DEBUG_MSG;
+ index = rm << shift_imm;
+ break;
+ case 1:
+// DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = 0;
+ } else {
+ index = rm >> shift_imm;
+ }
+ break;
+ case 2:
+ if (shift_imm == 0){ /* ASR #32 */
+ if (rm >> 31)
+ index = 0xFFFFFFFF;
+ else
+ index = 0;
+ }
+ else {
+ index = static_cast<int>(rm) >> shift_imm;
+ }
+ break;
+ case 3:
+ DEBUG_MSG;
+ break;
+ }
+ if (U_BIT) {
+ addr = rn + index;
+ } else
+ addr = rn - index;
+ virt_addr = addr;
+ fault = check_address_validity(cpu, addr, &phys_addr, rw);
+ return fault;
+}
+
+#define ISNEG(n) (n < 0)
+#define ISPOS(n) (n >= 0)
+
+//enum {
+// COND = (1 << 0),
+// NON_BRANCH = (1 << 1),
+// DIRECT_BRANCH = (1 << 2),
+// INDIRECT_BRANCH = (1 << 3),
+// CALL = (1 << 4),
+// RET = (1 << 5),
+// END_OF_PAGE = (1 << 6),
+// THUMB = (1 << 7)
+//};
+
+typedef struct _arm_inst {
+ unsigned int idx;
+ unsigned int cond;
+ int br;
+ int load_r15;
+ char component[0];
+} arm_inst;
+
+typedef struct _adc_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} adc_inst;
+
+typedef struct _add_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} add_inst;
+
+typedef struct _orr_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} orr_inst;
+
+typedef struct _and_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} and_inst;
+
+typedef struct _eor_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} eor_inst;
+
+typedef struct _bbl_inst {
+ unsigned int L;
+ int signed_immed_24;
+ unsigned int next_addr;
+ unsigned int jmp_addr;
+} bbl_inst;
+
+typedef struct _bx_inst {
+ unsigned int Rm;
+} bx_inst;
+
+typedef struct _blx_inst {
+ union {
+ int32_t signed_immed_24;
+ uint32_t Rm;
+ } val;
+ unsigned int inst;
+} blx_inst;
+
+typedef struct _clz_inst {
+ unsigned int Rm;
+ unsigned int Rd;
+} clz_inst;
+
+typedef struct _cps_inst {
+ unsigned int imod0;
+ unsigned int imod1;
+ unsigned int mmod;
+ unsigned int A, I, F;
+ unsigned int mode;
+} cps_inst;
+
+typedef struct _clrex_inst {
+} clrex_inst;
+
+typedef struct _cpy_inst {
+ unsigned int Rm;
+ unsigned int Rd;
+} cpy_inst;
+
+typedef struct _bic_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} bic_inst;
+
+typedef struct _sub_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} sub_inst;
+
+typedef struct _tst_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} tst_inst;
+
+typedef struct _cmn_inst {
+ unsigned int I;
+ //unsigned int S;
+ unsigned int Rn;
+ //unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} cmn_inst;
+
+typedef struct _teq_inst {
+ unsigned int I;
+ unsigned int Rn;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} teq_inst;
+
+typedef struct _stm_inst {
+ unsigned int inst;
+} stm_inst;
+
+struct bkpt_inst {
+};
+
+struct blx1_inst {
+ unsigned int addr;
+};
+
+struct blx2_inst {
+ unsigned int Rm;
+};
+
+typedef struct _stc_inst {
+} stc_inst;
+
+typedef struct _ldc_inst {
+} ldc_inst;
+
+typedef struct _swi_inst {
+ unsigned int num;
+} swi_inst;
+
+typedef struct _cmp_inst {
+ unsigned int I;
+ unsigned int Rn;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} cmp_inst;
+
+typedef struct _mov_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} mov_inst;
+
+typedef struct _mvn_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} mvn_inst;
+
+typedef struct _rev_inst {
+ unsigned int Rd;
+ unsigned int Rm;
+} rev_inst;
+
+typedef struct _rsb_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} rsb_inst;
+
+typedef struct _rsc_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} rsc_inst;
+
+typedef struct _sbc_inst {
+ unsigned int I;
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int shifter_operand;
+ shtop_fp_t shtop_func;
+} sbc_inst;
+
+typedef struct _mul_inst {
+ unsigned int S;
+ unsigned int Rd;
+ unsigned int Rs;
+ unsigned int Rm;
+} mul_inst;
+
+typedef struct _smul_inst {
+ unsigned int Rd;
+ unsigned int Rs;
+ unsigned int Rm;
+ unsigned int x;
+ unsigned int y;
+} smul_inst;
+
+typedef struct _umull_inst {
+ unsigned int S;
+ unsigned int RdHi;
+ unsigned int RdLo;
+ unsigned int Rs;
+ unsigned int Rm;
+} umull_inst;
+typedef struct _smlad_inst {
+ unsigned int m;
+ unsigned int Rm;
+ unsigned int Rd;
+ unsigned int Ra;
+ unsigned int Rn;
+} smlad_inst;
+
+typedef struct _smla_inst {
+ unsigned int x;
+ unsigned int y;
+ unsigned int Rm;
+ unsigned int Rd;
+ unsigned int Rs;
+ unsigned int Rn;
+} smla_inst;
+
+typedef struct _umlal_inst {
+ unsigned int S;
+ unsigned int Rm;
+ unsigned int Rs;
+ unsigned int RdHi;
+ unsigned int RdLo;
+} umlal_inst;
+
+typedef struct _smlal_inst {
+ unsigned int S;
+ unsigned int Rm;
+ unsigned int Rs;
+ unsigned int RdHi;
+ unsigned int RdLo;
+} smlal_inst;
+
+typedef struct _mla_inst {
+ unsigned int S;
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int Rs;
+ unsigned int Rm;
+} mla_inst;
+
+typedef struct _mrc_inst {
+ unsigned int opcode_1;
+ unsigned int opcode_2;
+ unsigned int cp_num;
+ unsigned int crn;
+ unsigned int crm;
+ unsigned int Rd;
+ unsigned int inst;
+} mrc_inst;
+
+typedef struct _mcr_inst {
+ unsigned int opcode_1;
+ unsigned int opcode_2;
+ unsigned int cp_num;
+ unsigned int crn;
+ unsigned int crm;
+ unsigned int Rd;
+ unsigned int inst;
+} mcr_inst;
+
+typedef struct _mrs_inst {
+ unsigned int R;
+ unsigned int Rd;
+} mrs_inst;
+
+typedef struct _msr_inst {
+ unsigned int field_mask;
+ unsigned int R;
+ unsigned int inst;
+} msr_inst;
+
+typedef struct _pld_inst {
+} pld_inst;
+
+typedef struct _sxtb_inst {
+ unsigned int Rd;
+ unsigned int Rm;
+ unsigned int rotate;
+} sxtb_inst;
+
+typedef struct _sxtab_inst {
+ unsigned int Rd;
+ unsigned int Rn;
+ unsigned int Rm;
+ unsigned rotate;
+} sxtab_inst;
+
+typedef struct _sxtah_inst {
+ unsigned int Rd;
+ unsigned int Rn;
+ unsigned int Rm;
+ unsigned int rotate;
+} sxtah_inst;
+
+typedef struct _sxth_inst {
+ unsigned int Rd;
+ unsigned int Rm;
+ unsigned int rotate;
+} sxth_inst;
+
+typedef struct _uxtab_inst {
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int rotate;
+ unsigned int Rm;
+} uxtab_inst;
+
+typedef struct _uxtah_inst {
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int rotate;
+ unsigned int Rm;
+} uxtah_inst;
+
+typedef struct _uxth_inst {
+ unsigned int Rd;
+ unsigned int Rm;
+ unsigned int rotate;
+} uxth_inst;
+
+typedef struct _cdp_inst {
+ unsigned int opcode_1;
+ unsigned int CRn;
+ unsigned int CRd;
+ unsigned int cp_num;
+ unsigned int opcode_2;
+ unsigned int CRm;
+ uint32 inst;
+}cdp_inst;
+
+typedef struct _uxtb_inst {
+ unsigned int Rd;
+ unsigned int Rm;
+ unsigned int rotate;
+} uxtb_inst;
+
+typedef struct _swp_inst {
+ unsigned int Rn;
+ unsigned int Rd;
+ unsigned int Rm;
+} swp_inst;
+
+typedef struct _b_2_thumb {
+ unsigned int imm;
+}b_2_thumb;
+typedef struct _b_cond_thumb {
+ unsigned int imm;
+ unsigned int cond;
+}b_cond_thumb;
+
+typedef struct _bl_1_thumb {
+ unsigned int imm;
+}bl_1_thumb;
+typedef struct _bl_2_thumb {
+ unsigned int imm;
+}bl_2_thumb;
+typedef struct _blx_1_thumb {
+ unsigned int imm;
+ unsigned int instr;
+}blx_1_thumb;
+
+typedef arm_inst * ARM_INST_PTR;
+
+#define CACHE_BUFFER_SIZE (64 * 1024 * 2000)
+char inst_buf[CACHE_BUFFER_SIZE];
+int top = 0;
+inline void *AllocBuffer(unsigned int size)
+{
+ int start = top;
+ top += size;
+ if (top > CACHE_BUFFER_SIZE) {
+ DEBUG_LOG(ARM11, "inst_buf is full\n");
+ CITRA_IGNORE_EXIT(-1);
+ }
+ return (void *)&inst_buf[start];
+}
+
+int CondPassed(arm_processor *cpu, unsigned int cond)
+{
+ #define NFLAG cpu->NFlag
+ #define ZFLAG cpu->ZFlag
+ #define CFLAG cpu->CFlag
+ #define VFLAG cpu->VFlag
+ int temp;
+ switch (cond) {
+ case 0x0:
+ temp = ZFLAG;
+ break;
+ case 0x1: /* NE */
+ temp = !ZFLAG;
+ break;
+ case 0x6: /* VS */
+ temp = VFLAG;
+ break;
+ case 0x7: /* VC */
+ temp = !VFLAG;
+ break;
+ case 0x4: /* MI */
+ temp = NFLAG;
+ break;
+ case 0x5: /* PL */
+ temp = !NFLAG;
+ break;
+ case 0x2: /* CS */
+ temp = CFLAG;
+ break;
+ case 0x3: /* CC */
+ temp = !CFLAG;
+ break;
+ case 0x8: /* HI */
+ temp = (CFLAG && !ZFLAG);
+ break;
+ case 0x9: /* LS */
+ temp = (!CFLAG || ZFLAG);
+ break;
+ case 0xa: /* GE */
+ temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
+ break;
+ case 0xb: /* LT */
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
+ break;
+ case 0xc: /* GT */
+ temp = ((!NFLAG && !VFLAG && !ZFLAG)
+ || (NFLAG && VFLAG && !ZFLAG));
+ break;
+ case 0xd: /* LE */
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG))
+ || ZFLAG;
+ break;
+ case 0xe: /* AL */
+ temp = 1;
+ break;
+ case 0xf:
+// DEBUG_LOG(ARM11, "inst is %x\n");
+// DEBUG_LOG(ARM11, "icounter is %lld\n", cpu->icounter);
+// CITRA_IGNORE_EXIT(-1);
+ temp = 1;
+ break;
+ }
+ return temp;
+}
+
+enum DECODE_STATUS {
+ DECODE_SUCCESS,
+ DECODE_FAILURE
+};
+
+int decode_arm_instr(uint32_t instr, int32_t *idx);
+
+shtop_fp_t get_shtop(unsigned int inst)
+{
+ if (BIT(inst, 25)) {
+ return DPO(Immediate);
+ } else if (BITS(inst, 4, 11) == 0) {
+ return DPO(Register);
+ } else if (BITS(inst, 4, 6) == 0) {
+ return DPO(LogicalShiftLeftByImmediate);
+ } else if (BITS(inst, 4, 7) == 1) {
+ return DPO(LogicalShiftLeftByRegister);
+ } else if (BITS(inst, 4, 6) == 2) {
+ return DPO(LogicalShiftRightByImmediate);
+ } else if (BITS(inst, 4, 7) == 3) {
+ return DPO(LogicalShiftRightByRegister);
+ } else if (BITS(inst, 4, 6) == 4) {
+ return DPO(ArithmeticShiftRightByImmediate);
+ } else if (BITS(inst, 4, 7) == 5) {
+ return DPO(ArithmeticShiftRightByRegister);
+ } else if (BITS(inst, 4, 6) == 6) {
+ return DPO(RotateRightByImmediate);
+ } else if (BITS(inst, 4, 7) == 7) {
+ return DPO(RotateRightByRegister);
+ }
+ return NULL;
+}
+
+get_addr_fp_t get_calc_addr_op(unsigned int inst)
+{
+ /* 1 */
+ if (BITS(inst, 24, 27) == 5 && BIT(inst, 21) == 0) {
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LnSWoUB(ImmediateOffset);
+ } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 0 && BITS(inst, 4, 11) == 0) {
+// DEBUG_MSG;
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LnSWoUB(RegisterOffset);
+ } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) {
+// DEBUG_MSG;
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LnSWoUB(ScaledRegisterOffset);
+ } else if (BITS(inst, 24, 27) == 5 && BIT(inst, 21) == 1) {
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LnSWoUB(ImmediatePreIndexed);
+ } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 1 && BITS(inst, 4, 11) == 0) {
+ return LnSWoUB(RegisterPreIndexed);
+ } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 1 && BIT(inst, 4) == 0) {
+ return LnSWoUB(ScaledRegisterPreIndexed);
+ } else if (BITS(inst, 24, 27) == 4 && BIT(inst, 21) == 0) {
+ return LnSWoUB(ImmediatePostIndexed);
+ } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BITS(inst, 4, 11) == 0) {
+// DEBUG_MSG;
+ return LnSWoUB(RegisterPostIndexed);
+ } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) {
+ return LnSWoUB(ScaledRegisterPostIndexed);
+// DEBUG_MSG;
+ } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+ /* 2 */
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return MLnS(ImmediateOffset);
+// DEBUG_MSG;
+ } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+// DEBUG_LOG(ARM11, "line is %d\n", __LINE__);
+ return MLnS(RegisterOffset);
+// DEBUG_MSG;
+ } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+// DEBUG_LOG(ARM11, "line is %d\n", __LINE__);
+ return MLnS(ImmediatePreIndexed);
+// DEBUG_MSG;
+ } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+ return MLnS(RegisterPreIndexed);
+ } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+// DEBUG_MSG;
+ return MLnS(ImmediatePostIndexed);
+ } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) {
+ //DEBUG_MSG;
+ return MLnS(RegisterPostIndexed);
+ } else if (BITS(inst, 23, 27) == 0x11) {
+ /* 3 */
+// DEBUG_MSG;
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LdnStM(IncrementAfter);
+ } else if (BITS(inst, 23, 27) == 0x13) {
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LdnStM(IncrementBefore);
+// DEBUG_MSG;
+ } else if (BITS(inst, 23, 27) == 0x10) {
+// DEBUG_MSG;
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LdnStM(DecrementAfter);
+ } else if (BITS(inst, 23, 27) == 0x12) {
+// DEBUG_MSG;
+// DEBUG_LOG(ARM11, "line is %d", __LINE__);
+ return LdnStM(DecrementBefore);
+ }
+ #if 0
+ DEBUG_LOG(ARM11, "In %s Unknown addressing mode\n", __FUNCTION__);
+ DEBUG_LOG(ARM11, "inst:%x\n", inst);
+ CITRA_IGNORE_EXIT(-1);
+ #endif
+ return NULL;
+}
+
+#define INTERPRETER_TRANSLATE(s) glue(InterpreterTranslate_, s)
+
+#define CHECK_RN (inst_cream->Rn == 15)
+#define CHECK_RM (inst_cream->Rm == 15)
+#define CHECK_RS (inst_cream->Rs == 15)
+
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst));
+ adc_inst *inst_cream = (adc_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst));
+ add_inst *inst_cream = (add_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst));
+ and_inst *inst_cream = (and_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15)
+ inst_base->br = INDIRECT_BRANCH;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index)
+{
+ #define POSBRANCH ((inst & 0x7fffff) << 2)
+ #define NEGBRANCH ((0xff000000 |(inst & 0xffffff)) << 2)
+
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst));
+ bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = DIRECT_BRANCH;
+
+ if (BIT(inst, 24))
+ inst_base->br = CALL;
+ if (BITS(inst, 28, 31) <= 0xe)
+ inst_base->br |= COND;
+
+ inst_cream->L = BIT(inst, 24);
+ inst_cream->signed_immed_24 = BIT(inst, 23) ? NEGBRANCH : POSBRANCH;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst));
+ bic_inst *inst_cream = (bic_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (inst_cream->Rd == 15)
+ inst_base->br = INDIRECT_BRANCH;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst));
+ blx_inst *inst_cream = (blx_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = INDIRECT_BRANCH;
+
+ inst_cream->inst = inst;
+ if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
+ inst_cream->val.Rm = BITS(inst, 0, 3);
+ } else {
+ inst_cream->val.signed_immed_24 = BITS(inst, 0, 23);
+ //DEBUG_LOG(ARM11, " blx inst is %x\n", inst);
+ //CITRA_IGNORE_EXIT(-1);
+// DEBUG_MSG;
+ }
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst));
+ bx_inst *inst_cream = (bx_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = INDIRECT_BRANCH;
+
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst));
+ cdp_inst *inst_cream = (cdp_inst *)inst_base->component;
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->CRm = BITS(inst, 0, 3);
+ inst_cream->CRd = BITS(inst, 12, 15);
+ inst_cream->CRn = BITS(inst, 16, 19);
+ inst_cream->cp_num = BITS(inst, 8, 11);
+ inst_cream->opcode_2 = BITS(inst, 5, 7);
+ inst_cream->opcode_1 = BITS(inst, 20, 23);
+ inst_cream->inst = inst;
+
+ DEBUG_LOG(ARM11, "in func %s inst %x index %x\n", __FUNCTION__, inst, index);
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst));
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst));
+ clz_inst *inst_cream = (clz_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RM)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst));
+ cmn_inst *inst_cream = (cmn_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ //inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ //inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst));
+ cmp_inst *inst_cream = (cmp_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst));
+ cps_inst *inst_cream = (cps_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->imod0 = BIT(inst, 18);
+ inst_cream->imod1 = BIT(inst, 19);
+ inst_cream->mmod = BIT(inst, 17);
+ inst_cream->A = BIT(inst, 8);
+ inst_cream->I = BIT(inst, 7);
+ inst_cream->F = BIT(inst, 6);
+ inst_cream->mode = BITS(inst, 0, 4);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst));
+ mov_inst *inst_cream = (mov_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst));
+ eor_inst *inst_cream = (eor_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst));
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BIT(inst, 15)) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst));
+ sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ if (CHECK_RM)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst));
+ uxth_inst *inst_cream = (uxth_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ if (CHECK_RM)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst));
+ uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ if (CHECK_RM || CHECK_RN)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ if (I_BIT == 0) {
+ inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+ } else {
+ DEBUG_MSG;
+ }
+ #if 0
+ inst_cream->get_addr = get_calc_addr_op(inst);
+ if(inst == 0x54f13001) {
+ DEBUG_LOG(ARM11, "get_calc_addr_op:%llx\n", inst_cream->get_addr);
+ }
+ #endif
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ //inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ if (I_BIT == 0) {
+ inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+ } else {
+ DEBUG_MSG;
+ }
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst));
+ mcr_inst *inst_cream = (mcr_inst *)inst_base->component;
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->crn = BITS(inst, 16, 19);
+ inst_cream->crm = BITS(inst, 0, 3);
+ inst_cream->opcode_1 = BITS(inst, 21, 23);
+ inst_cream->opcode_2 = BITS(inst, 5, 7);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->cp_num = BITS(inst, 8, 11);
+ inst_cream->inst = inst;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst));
+ mla_inst *inst_cream = (mla_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 12, 15);
+ inst_cream->Rd = BITS(inst, 16, 19);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ if (CHECK_RM || CHECK_RN || CHECK_RS)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst));
+ mov_inst *inst_cream = (mov_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst));
+ mrc_inst *inst_cream = (mrc_inst *)inst_base->component;
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->crn = BITS(inst, 16, 19);
+ inst_cream->crm = BITS(inst, 0, 3);
+ inst_cream->opcode_1 = BITS(inst, 21, 23);
+ inst_cream->opcode_2 = BITS(inst, 5, 7);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->cp_num = BITS(inst, 8, 11);
+ inst_cream->inst = inst;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst));
+ mrs_inst *inst_cream = (mrs_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->R = BIT(inst, 22);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst));
+ msr_inst *inst_cream = (msr_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->field_mask = BITS(inst, 16, 19);
+ inst_cream->R = BIT(inst, 22);
+ inst_cream->inst = inst;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst));
+ mul_inst *inst_cream = (mul_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->Rd = BITS(inst, 16, 19);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst));
+ mvn_inst *inst_cream = (mvn_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst));
+ orr_inst *inst_cream = (orr_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
+ rev_inst *inst_cream = (rev_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rd = BITS(inst, 12, 15);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
+ rev_inst *inst_cream = (rev_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rd = BITS(inst, 12, 15);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst));
+ rsb_inst *inst_cream = (rsb_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst));
+ rsc_inst *inst_cream = (rsc_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst));
+ sbc_inst *inst_cream = (sbc_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst));
+ smla_inst *inst_cream = (smla_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->x = BIT(inst, 5);
+ inst_cream->y = BIT(inst, 6);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->Rd = BITS(inst, 16, 19);
+ inst_cream->Rn = BITS(inst, 12, 15);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
+ smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->m = BIT(inst, 4);
+ inst_cream->Rn = BITS(inst, 0, 3);
+ inst_cream->Rm = BITS(inst, 8, 11);
+ inst_cream->Rd = BITS(inst, 16, 19);
+ inst_cream->Ra = BITS(inst, 12, 15);
+
+ if (CHECK_RM )
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst));
+ umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->RdHi = BITS(inst, 16, 19);
+ inst_cream->RdLo = BITS(inst, 12, 15);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst));
+ smul_inst *inst_cream = (smul_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 16, 19);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ inst_cream->x = BIT(inst, 5);
+ inst_cream->y = BIT(inst, 6);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst));
+ umull_inst *inst_cream = (umull_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->RdHi = BITS(inst, 16, 19);
+ inst_cream->RdLo = BITS(inst, 12, 15);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
+ smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->m = BIT(inst, 6);
+ inst_cream->Rm = BITS(inst, 8, 11);
+ inst_cream->Rn = BITS(inst, 0, 3);
+ inst_cream->Rd = BITS(inst, 16, 19);
+
+ if (CHECK_RM || CHECK_RN)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst));
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst));
+ sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->rotate = BITS(inst, 10, 11);
+
+ if (CHECK_RM)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst));
+ uxth_inst *inst_cream = (uxth_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ if (CHECK_RM)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst));
+ uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rn = BITS(inst, 16, 19);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+// inst_cream->get_addr = get_calc_addr_op(inst);
+ if (I_BIT == 0) {
+ inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+ } else {
+ DEBUG_MSG;
+ }
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->inst = inst;
+ if (I_BIT == 0) {
+ inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+ } else {
+ DEBUG_MSG;
+ }
+
+ if (BITS(inst, 12, 15) == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst));
+ sub_inst *inst_cream = (sub_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst));
+ swi_inst *inst_cream = (swi_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->num = BITS(inst, 0, 23);
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst));
+ swp_inst *inst_cream = (swp_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst));
+ swp_inst *inst_cream = (swp_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rm = BITS(inst, 0, 3);
+
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst));
+ sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rn = BITS(inst, 16, 19);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){
+ DEBUG_LOG(ARM11, "in func %s, SXTAH untested\n", __func__);
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst));
+ sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->rotate = BITS(inst, 10, 11);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rn = BITS(inst, 16, 19);
+
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst));
+ teq_inst *inst_cream = (teq_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst));
+ tst_inst *inst_cream = (tst_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->I = BIT(inst, 25);
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rn = BITS(inst, 16, 19);
+ inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->shifter_operand = BITS(inst, 0, 11);
+ inst_cream->shtop_func = get_shtop(inst);
+ if (inst_cream->Rd == 15) {
+ inst_base->br = INDIRECT_BRANCH;
+ }
+
+ if (CHECK_RN)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst));
+ umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->RdHi = BITS(inst, 16, 19);
+ inst_cream->RdLo = BITS(inst, 12, 15);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst));
+ umull_inst *inst_cream = (umull_inst *)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->S = BIT(inst, 20);
+ inst_cream->Rm = BITS(inst, 0, 3);
+ inst_cream->Rs = BITS(inst, 8, 11);
+ inst_cream->RdHi = BITS(inst, 16, 19);
+ inst_cream->RdLo = BITS(inst, 12, 15);
+
+ if (CHECK_RM || CHECK_RS)
+ inst_base->load_r15 = 1;
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb));
+ b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component;
+
+ inst_cream->imm =((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0);
+ //DEBUG_LOG(ARM11, "In %s, tinst=0x%x, imm=0x%x\n", __FUNCTION__, tinst, inst_cream->imm);
+ inst_base->idx = index;
+ inst_base->br = DIRECT_BRANCH;
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb));
+ b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component;
+
+ inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0));
+ inst_cream->cond = ((tinst >> 8) & 0xf);
+ //DEBUG_LOG(ARM11, "In %s, tinst=0x%x, imm=0x%x, cond=0x%x\n", __FUNCTION__, tinst, inst_cream->imm, inst_cream->cond);
+ inst_base->idx = index;
+ inst_base->br = DIRECT_BRANCH;
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb));
+ bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component;
+
+ inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0));
+ //DEBUG_LOG(ARM11, "In %s, tinst=0x%x, imm=0x%x\n", __FUNCTION__, tinst, inst_cream->imm);
+
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb));
+ bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component;
+
+ inst_cream->imm = (tinst & 0x07FF) << 1;
+ //DEBUG_LOG(ARM11, "In %s, tinst=0x%x, imm=0x%x\n", __FUNCTION__, tinst, inst_cream->imm);
+ inst_base->idx = index;
+ inst_base->br = DIRECT_BRANCH;
+ return inst_base;
+}
+ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index)
+{
+ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb));
+ blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component;
+
+ inst_cream->imm = (tinst & 0x07FF) << 1;
+ //DEBUG_LOG(ARM11, "In %s, tinst=0x%x, imm=0x%x\n", __FUNCTION__, tinst, inst_cream->imm);
+ inst_cream->instr = tinst;
+ inst_base->idx = index;
+ inst_base->br = DIRECT_BRANCH;
+ return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index){DEBUG_LOG(ARM11, "in func %s\n", __FUNCTION__);CITRA_IGNORE_EXIT(-1); return nullptr;}
+
+
+
+/* Floating point VFPv3 structures and instructions */
+
+#define VFP_INTERPRETER_STRUCT
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+#undef VFP_INTERPRETER_STRUCT
+
+#define VFP_INTERPRETER_TRANS
+#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+#undef VFP_INTERPRETER_TRANS
+
+
+
+typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
+
+const transop_fp_t arm_instruction_trans[] = {
+ #define VFP_INTERPRETER_TABLE
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+ #undef VFP_INTERPRETER_TABLE
+ INTERPRETER_TRANSLATE(srs),
+ INTERPRETER_TRANSLATE(rfe),
+ INTERPRETER_TRANSLATE(bkpt),
+ INTERPRETER_TRANSLATE(blx),
+ INTERPRETER_TRANSLATE(cps),
+ INTERPRETER_TRANSLATE(pld),
+ INTERPRETER_TRANSLATE(setend),
+ INTERPRETER_TRANSLATE(clrex),
+ INTERPRETER_TRANSLATE(rev16),
+ INTERPRETER_TRANSLATE(usad8),
+ INTERPRETER_TRANSLATE(sxtb),
+ INTERPRETER_TRANSLATE(uxtb),
+ INTERPRETER_TRANSLATE(sxth),
+ INTERPRETER_TRANSLATE(sxtb16),
+ INTERPRETER_TRANSLATE(uxth),
+ INTERPRETER_TRANSLATE(uxtb16),
+ INTERPRETER_TRANSLATE(cpy),
+ INTERPRETER_TRANSLATE(uxtab),
+ INTERPRETER_TRANSLATE(ssub8),
+ INTERPRETER_TRANSLATE(shsub8),
+ INTERPRETER_TRANSLATE(ssubaddx),
+ INTERPRETER_TRANSLATE(strex),
+ INTERPRETER_TRANSLATE(strexb),
+ INTERPRETER_TRANSLATE(swp),
+ INTERPRETER_TRANSLATE(swpb),
+ INTERPRETER_TRANSLATE(ssub16),
+ INTERPRETER_TRANSLATE(ssat16),
+ INTERPRETER_TRANSLATE(shsubaddx),
+ INTERPRETER_TRANSLATE(qsubaddx),
+ INTERPRETER_TRANSLATE(shaddsubx),
+ INTERPRETER_TRANSLATE(shadd8),
+ INTERPRETER_TRANSLATE(shadd16),
+ INTERPRETER_TRANSLATE(sel),
+ INTERPRETER_TRANSLATE(saddsubx),
+ INTERPRETER_TRANSLATE(sadd8),
+ INTERPRETER_TRANSLATE(sadd16),
+ INTERPRETER_TRANSLATE(shsub16),
+ INTERPRETER_TRANSLATE(umaal),
+ INTERPRETER_TRANSLATE(uxtab16),
+ INTERPRETER_TRANSLATE(usubaddx),
+ INTERPRETER_TRANSLATE(usub8),
+ INTERPRETER_TRANSLATE(usub16),
+ INTERPRETER_TRANSLATE(usat16),
+ INTERPRETER_TRANSLATE(usada8),
+ INTERPRETER_TRANSLATE(uqsubaddx),
+ INTERPRETER_TRANSLATE(uqsub8),
+ INTERPRETER_TRANSLATE(uqsub16),
+ INTERPRETER_TRANSLATE(uqaddsubx),
+ INTERPRETER_TRANSLATE(uqadd8),
+ INTERPRETER_TRANSLATE(uqadd16),
+ INTERPRETER_TRANSLATE(sxtab),
+ INTERPRETER_TRANSLATE(uhsubaddx),
+ INTERPRETER_TRANSLATE(uhsub8),
+ INTERPRETER_TRANSLATE(uhsub16),
+ INTERPRETER_TRANSLATE(uhaddsubx),
+ INTERPRETER_TRANSLATE(uhadd8),
+ INTERPRETER_TRANSLATE(uhadd16),
+ INTERPRETER_TRANSLATE(uaddsubx),
+ INTERPRETER_TRANSLATE(uadd8),
+ INTERPRETER_TRANSLATE(uadd16),
+ INTERPRETER_TRANSLATE(sxtah),
+ INTERPRETER_TRANSLATE(sxtab16),
+ INTERPRETER_TRANSLATE(qadd8),
+ INTERPRETER_TRANSLATE(bxj),
+ INTERPRETER_TRANSLATE(clz),
+ INTERPRETER_TRANSLATE(uxtah),
+ INTERPRETER_TRANSLATE(bx),
+ INTERPRETER_TRANSLATE(rev),
+ INTERPRETER_TRANSLATE(blx),
+ INTERPRETER_TRANSLATE(revsh),
+ INTERPRETER_TRANSLATE(qadd),
+ INTERPRETER_TRANSLATE(qadd16),
+ INTERPRETER_TRANSLATE(qaddsubx),
+ INTERPRETER_TRANSLATE(ldrex),
+ INTERPRETER_TRANSLATE(qdadd),
+ INTERPRETER_TRANSLATE(qdsub),
+ INTERPRETER_TRANSLATE(qsub),
+ INTERPRETER_TRANSLATE(ldrexb),
+ INTERPRETER_TRANSLATE(qsub8),
+ INTERPRETER_TRANSLATE(qsub16),
+ INTERPRETER_TRANSLATE(smuad),
+ INTERPRETER_TRANSLATE(smmul),
+ INTERPRETER_TRANSLATE(smusd),
+ INTERPRETER_TRANSLATE(smlsd),
+ INTERPRETER_TRANSLATE(smlsld),
+ INTERPRETER_TRANSLATE(smmla),
+ INTERPRETER_TRANSLATE(smmls),
+ INTERPRETER_TRANSLATE(smlald),
+ INTERPRETER_TRANSLATE(smlad),
+ INTERPRETER_TRANSLATE(smlaw),
+ INTERPRETER_TRANSLATE(smulw),
+ INTERPRETER_TRANSLATE(pkhtb),
+ INTERPRETER_TRANSLATE(pkhbt),
+ INTERPRETER_TRANSLATE(smul),
+ INTERPRETER_TRANSLATE(smlalxy),
+ INTERPRETER_TRANSLATE(smla),
+ INTERPRETER_TRANSLATE(mcrr),
+ INTERPRETER_TRANSLATE(mrrc),
+ INTERPRETER_TRANSLATE(cmp),
+ INTERPRETER_TRANSLATE(tst),
+ INTERPRETER_TRANSLATE(teq),
+ INTERPRETER_TRANSLATE(cmn),
+ INTERPRETER_TRANSLATE(smull),
+ INTERPRETER_TRANSLATE(umull),
+ INTERPRETER_TRANSLATE(umlal),
+ INTERPRETER_TRANSLATE(smlal),
+ INTERPRETER_TRANSLATE(mul),
+ INTERPRETER_TRANSLATE(mla),
+ INTERPRETER_TRANSLATE(ssat),
+ INTERPRETER_TRANSLATE(usat),
+ INTERPRETER_TRANSLATE(mrs),
+ INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(and),
+ INTERPRETER_TRANSLATE(bic),
+ INTERPRETER_TRANSLATE(ldm),
+ INTERPRETER_TRANSLATE(eor),
+ INTERPRETER_TRANSLATE(add),
+ INTERPRETER_TRANSLATE(rsb),
+ INTERPRETER_TRANSLATE(rsc),
+ INTERPRETER_TRANSLATE(sbc),
+ INTERPRETER_TRANSLATE(adc),
+ INTERPRETER_TRANSLATE(sub),
+ INTERPRETER_TRANSLATE(orr),
+ INTERPRETER_TRANSLATE(mvn),
+ INTERPRETER_TRANSLATE(mov),
+ INTERPRETER_TRANSLATE(stm),
+ INTERPRETER_TRANSLATE(ldm),
+ INTERPRETER_TRANSLATE(ldrsh),
+ INTERPRETER_TRANSLATE(stm),
+ INTERPRETER_TRANSLATE(ldm),
+ INTERPRETER_TRANSLATE(ldrsb),
+ INTERPRETER_TRANSLATE(strd),
+ INTERPRETER_TRANSLATE(ldrh),
+ INTERPRETER_TRANSLATE(strh),
+ INTERPRETER_TRANSLATE(ldrd),
+ INTERPRETER_TRANSLATE(strt),
+ INTERPRETER_TRANSLATE(strbt),
+ INTERPRETER_TRANSLATE(ldrbt),
+ INTERPRETER_TRANSLATE(ldrt),
+ INTERPRETER_TRANSLATE(mrc),
+ INTERPRETER_TRANSLATE(mcr),
+ INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(ldrb),
+ INTERPRETER_TRANSLATE(strb),
+ INTERPRETER_TRANSLATE(ldr),
+ INTERPRETER_TRANSLATE(ldrcond),
+ INTERPRETER_TRANSLATE(str),
+ INTERPRETER_TRANSLATE(cdp),
+ INTERPRETER_TRANSLATE(stc),
+ INTERPRETER_TRANSLATE(ldc),
+ INTERPRETER_TRANSLATE(swi),
+ INTERPRETER_TRANSLATE(bbl),
+ /* All the thumb instructions should be placed the end of table */
+ INTERPRETER_TRANSLATE(b_2_thumb),
+ INTERPRETER_TRANSLATE(b_cond_thumb),
+ INTERPRETER_TRANSLATE(bl_1_thumb),
+ INTERPRETER_TRANSLATE(bl_2_thumb),
+ INTERPRETER_TRANSLATE(blx_1_thumb)
+};
+
+typedef map<unsigned int, int> bb_map;
+bb_map CreamCache[65536];
+bb_map ProfileCache[65536];
+
+//#define USE_DUMMY_CACHE
+
+#ifdef USE_DUMMY_CACHE
+unsigned int DummyCache[0x100000];
+#endif
+
+#define HASH(x) ((x + (x << 3) + (x >> 6)) % 65536)
+void insert_bb(unsigned int addr, int start)
+{
+#ifdef USE_DUMMY_CACHE
+ DummyCache[addr] = start;
+#else
+// CreamCache[addr] = start;
+ CreamCache[HASH(addr)][addr] = start;
+#endif
+}
+
+#define TRANS_THRESHOLD 65000
+int find_bb(unsigned int addr, int &start)
+{
+ int ret = -1;
+#ifdef USE_DUMMY_CACHE
+ start = DummyCache[addr];
+ if (start) {
+ ret = 0;
+ } else
+ ret = -1;
+#else
+ bb_map::const_iterator it = CreamCache[HASH(addr)].find(addr);
+ if (it != CreamCache[HASH(addr)].end()) {
+ start = static_cast<int>(it->second);
+ ret = 0;
+#if HYBRID_MODE
+#if PROFILE
+#else
+ /* increase the bb counter */
+ if(get_bb_prof(cpu, addr, 1) == TRANS_THRESHOLD){
+ push_to_compiled(cpu, addr);
+ }
+#endif
+#endif
+ } else {
+ ret = -1;
+ }
+#endif
+ return ret;
+}
+
+
+enum {
+ FETCH_SUCCESS,
+ FETCH_FAILURE
+};
+static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr, uint32_t *arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){
+ /* Check if in Thumb mode. */
+ tdstate ret;
+ ret = thumb_translate (addr, inst, arm_inst, inst_size);
+ if(ret == t_branch){
+ /* FIXME, endian should be judged */
+ uint32 tinstr;
+ if((addr & 0x3) != 0)
+ tinstr = inst >> 16;
+ else
+ tinstr = inst & 0xFFFF;
+
+ //tinstr = inst & 0xFFFF;
+ int inst_index;
+ /* table_length */
+ int table_length = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);
+
+ switch((tinstr & 0xF800) >> 11){
+ /* we will translate the thumb instruction directly here */
+ /* we will translate the thumb instruction directly here */
+ case 26:
+ case 27:
+ if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){
+ uint32 cond = (tinstr & 0x0F00) >> 8;
+ inst_index = table_length - 4;
+ //DEBUG_LOG(ARM11, "In %s, tinstr=0x%x, blx 1 thumb index=%d\n", __FUNCTION__, tinstr, inst_index);
+ *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
+ }
+ else{
+ /* something wrong */
+ DEBUG_LOG(ARM11, "In %s, thumb decoder error\n", __FUNCTION__);
+ }
+ break;
+ case 28:
+ /* Branch 2, unconditional branch */
+ inst_index = table_length - 5;
+ //DEBUG_LOG(ARM11, "In %s, tinstr=0x%x, blx 1 thumb index=%d\n", __FUNCTION__, tinstr, inst_index);
+ *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
+ break;
+
+ case 8:
+ case 29:
+ /* For BLX 1 thumb instruction*/
+ inst_index = table_length - 1;
+ //DEBUG_LOG(ARM11, "In %s, tinstr=0x%x, blx 1 thumb index=%d, pc=0x%x\n", __FUNCTION__, tinstr, inst_index, cpu->translate_pc);
+ *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
+ break;
+ case 30:
+ /* For BL 1 thumb instruction*/
+ inst_index = table_length - 3;
+ //DEBUG_LOG(ARM11, "In %s, tinstr=0x%x, bl 1 thumb index=%d, pc=0x%x\n", __FUNCTION__, tinstr, inst_index, cpu->translate_pc);
+ *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
+ break;
+ case 31:
+ /* For BL 2 thumb instruction*/
+ inst_index = table_length - 2;
+ //DEBUG_LOG(ARM11, "In %s, tinstr=0x%x, bl 2 thumb index=%d, px=0x%x\n", __FUNCTION__, tinstr, inst_index, cpu->translate_pc);
+ *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
+ break;
+ default:
+ ret = t_undefined;
+ break;
+ }
+ }
+ return ret;
+}
+
+#if 0
+int FetchInst(cpu_t *core, unsigned int &inst)
+{
+ //arm_processor *cpu = (arm_processor *)get_cast_conf_obj(core->cpu_data, "arm_core_t");
+ arm_processor *cpu = (arm_processor *)(core->cpu_data->obj);
+// fault_t fault = interpreter_read_memory(cpu->translate_pc, inst, 32);
+ fault_t fault = interpreter_fetch(core, cpu->translate_pc, inst, 32);
+ if (!core->is_user_mode) {
+ if (fault) {
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_PrefetchAbortV;
+ cpu->AbortAddr = cpu->translate_pc;
+ cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = cpu->translate_pc;
+ return FETCH_FAILURE;
+ }
+ }
+ return FETCH_SUCCESS;
+}
+#endif
+
+unsigned int *InstLength;
+
+enum {
+ KEEP_GOING,
+ FETCH_EXCEPTION
+};
+
+typedef struct instruction_set_encoding_item ISEITEM;
+
+extern const ISEITEM arm_instruction[];
+
+vector<uint64_t> code_page_set;
+
+void flush_bb(uint32_t addr)
+{
+ bb_map::iterator it;
+ uint32_t start;
+
+ addr &= 0xfffff000;
+ for (int i = 0; i < 65536; i ++) {
+ for (it = CreamCache[i].begin(); it != CreamCache[i].end(); ) {
+ start = static_cast<uint32_t>(it->first);
+ //start = (start >> 12) << 12;
+ start &= 0xfffff000;
+ if (start == addr) {
+ //DEBUG_LOG(ARM11, "[ERASE][0x%08x]\n", static_cast<int>(it->first));
+ CreamCache[i].erase(it ++);
+ } else
+ ++it;
+ }
+ }
+
+ for (int i = 0; i < 65536; i ++) {
+ for (it = ProfileCache[i].begin(); it != ProfileCache[i].end(); ) {
+ start = static_cast<uint32_t>(it->first);
+ //start = (start >> 12) << 12;
+ start &= 0xfffff000;
+ if (start == addr) {
+ //DEBUG_LOG(ARM11, "[ERASE][0x%08x]\n", static_cast<int>(it->first));
+ ProfileCache[i].erase(it ++);
+ } else
+ ++it;
+ }
+ }
+
+ //DEBUG_LOG(ARM11, "flush bb @ %x\n", addr);
+}
+
+//static uint32_t get_bank_addr(void *addr)
+//{
+// uint64_t address = (uint64_t)addr;
+// uint64_t bank0 = get_dma_addr(BANK0_START);
+// if ((address >= bank0) && (address < (bank0 + BANK0_SIZE))) {
+// //DEBUG_LOG(ARM11, "1.addr is %llx\n", addr);
+// return ((uint64_t)addr - bank0) + BANK0_START;
+// }
+// return 0;
+//}
+
+/* shenoubang add win32 2012-6-12 */
+//#ifndef __WIN32__
+//static void flush_code_cache(int signal_number, siginfo_t *si, void *unused)
+//{
+// DEBUG_LOG(ARM11, "in %s, addr=0x%llx\n", __FUNCTION__, si->si_addr);
+// uint64_t addr = (uint64_t)si->si_addr;
+// addr = (addr >> 12) << 12;
+// skyeye_backtrace();
+// #if 0
+// if (addr == 0) {
+// return;
+// }
+// const vector<uint64_t>::iterator it = find(code_page_set.begin(),
+// code_page_set.end(),
+// (uint64_t)addr);
+// if (it != code_page_set.end()) {
+// code_page_set.erase(it);
+// }
+// mprotect((void *)addr, 4096, PROT_READ | PROT_WRITE);
+// //DEBUG_LOG(ARM11, "[flush][ADDR:0x%08llx]\n", addr);
+// uint32_t phys_addr = get_bank_addr((void *)addr);
+//// DEBUG_LOG(ARM11, "[PHYSICAL][ADDR:0x%08llx]\n", phys_addr);
+// flush_bb(phys_addr);
+// flush_bb(phys_addr + 4096);
+//#if HYBRID_MODE
+// /* flush the translated BB of dyncom */
+// clear_translated_cache(phys_addr);
+//#endif
+// #endif
+//}
+//#endif /* shenoubang */
+
+//void protect_code_page(uint32_t addr)
+//{
+// void *mem_ptr = (void *)get_dma_addr(addr);
+// mem_ptr = (void *)((long long int)mem_ptr & 0xfffffffffffff000LL);
+//
+// const vector<uint64_t>::iterator it = find(code_page_set.begin(),
+// code_page_set.end(),
+// (uint64_t)mem_ptr);
+// if (it != code_page_set.end()) {
+// return;
+// }
+// //DEBUG_LOG(ARM11, "[mprotect][ADDR:0x%08llx]\n", mem_ptr);
+// /* shenoubang add win32 2012-6-12 */
+//#ifndef __WIN32__
+// struct sigaction sa;
+//
+// memset(&sa, 0, sizeof(sa));
+// sa.sa_flags = SA_RESTART | SA_SIGINFO;
+// sa.sa_sigaction = &flush_code_cache;
+// sigaction(SIGSEGV, &sa, NULL);
+//
+// //mprotect(mem_ptr, 4096, PROT_READ);
+//
+// code_page_set.push_back((uint64_t)mem_ptr);
+//#endif /* shenoubang */
+//}
+
+
+
+int InterpreterTranslate(arm_processor *cpu, int &bb_start, addr_t addr)
+{
+ /* Decode instruction, get index */
+ /* Allocate memory and init InsCream */
+ /* Go on next, until terminal instruction */
+ /* Save start addr of basicblock in CreamCache */
+ //arm_processor *cpu = (arm_processor *)get_cast_conf_obj(core->cpu_data, "arm_core_t");
+ //arm_processor *cpu = (arm_processor *)(core->cpu_data->obj);
+ ARM_INST_PTR inst_base = NULL;
+ unsigned int inst, inst_size = 4;
+ int idx;
+ int ret = NON_BRANCH;
+ int thumb = 0;
+ /* instruction size of basic block */
+ int size = 0;
+ /* (R15 - 8) ? */
+ //cpu->translate_pc = cpu->Reg[15];
+ bb_start = top;
+
+ if (cpu->TFlag)
+ thumb = THUMB;
+
+ addr_t phys_addr;
+ addr_t pc_start;
+ fault_t fault = NO_FAULT;
+ //fault = check_address_validity(cpu, addr, &phys_addr, 1, INSN_TLB);
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if(fault != NO_FAULT){
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_PrefetchAbortV;
+ cpu->AbortAddr = addr;
+ cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = addr;
+ return FETCH_EXCEPTION;
+ }
+ pc_start = phys_addr;
+ //phys_addr = get_dma_addr(phys_addr);
+ while(ret == NON_BRANCH) {
+ /* shenoubang add win32 2012-6-14 */
+#ifdef __WIN32__
+ mem_bank_t* bank;
+ if (bank = bank_ptr(addr)) {
+ bank->bank_read(32, phys_addr, &inst);
+ }
+ else {
+ DEBUG_LOG(ARM11, "SKYEYE: Read physical addr 0x%x error!!\n", phys_addr);
+ return FETCH_FAILURE;
+ }
+#else
+ inst = Memory::Read32(phys_addr & 0xFFFFFFFC);//*(uint32_t *)(phys_addr & 0xFFFFFFFC);
+#endif
+ //or_tag(core, phys_addr, TAG_FAST_INTERP);
+
+ /*if (ret == FETCH_FAILURE) {
+ return FETCH_EXCEPTION;
+ }*/
+
+ size ++;
+ /* If we are in thumb instruction, we will translate one thumb to one corresponding arm instruction */
+ if (cpu->TFlag){
+ //if(cpu->Cpsr & (1 << THUMB_BIT)){
+ uint32_t arm_inst;
+ tdstate state;
+ state = decode_thumb_instr(cpu, inst, phys_addr, &arm_inst, &inst_size, &inst_base);
+ //or_tag(core, phys_addr, TAG_THUMB);
+ //DEBUG_LOG(ARM11, "In thumb state, arm_inst=0x%x, inst_size=0x%x, pc=0x%x\n", arm_inst, inst_size, cpu->translate_pc);
+ /* we have translated the branch instruction of thumb in thumb decoder */
+ if(state == t_branch){
+ goto translated;
+ }
+ inst = arm_inst;
+ }
+
+ ret = decode_arm_instr(inst, &idx);
+ if (ret == DECODE_FAILURE) {
+ DEBUG_LOG(ARM11, "[info] : Decode failure.\tPC : [0x%x]\tInstruction : [%x]\n", phys_addr, inst);
+ DEBUG_LOG(ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x\n", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
+ CITRA_IGNORE_EXIT(-1);
+ }
+// DEBUG_LOG(ARM11, "PC : [0x%x] INST : %s\n", cpu->translate_pc, arm_instruction[idx].name);
+ inst_base = arm_instruction_trans[idx](inst, idx);
+// DEBUG_LOG(ARM11, "translated @ %x INST : %x\n", cpu->translate_pc, inst);
+// DEBUG_LOG(ARM11, "inst size is %d\n", InstLength[idx]);
+translated:
+ phys_addr += inst_size;
+
+ if ((phys_addr & 0xfff) == 0) {
+ inst_base->br = END_OF_PAGE;
+ }
+ ret = inst_base->br;
+ };
+
+ //DEBUG_LOG(ARM11, "In %s,insert_bb pc=0x%x, TFlag=0x%x\n", __FUNCTION__, pc_start, cpu->TFlag);
+ insert_bb(pc_start, bb_start);
+ return KEEP_GOING;
+}
+
+#define LOG_IN_CLR skyeye_printf_in_color
+
+int cmp(const void *x, const void *y)
+{
+ return *(unsigned long long int*)x - *(unsigned long long int *)y;
+}
+
+void InterpreterInitInstLength(unsigned long long int *ptr, size_t size)
+{
+ int array_size = size / sizeof(void *);
+ unsigned long long int *InstLabel = new unsigned long long int[array_size];
+ memcpy(InstLabel, ptr, size);
+ qsort(InstLabel, array_size, sizeof(void *), cmp);
+ InstLength = new unsigned int[array_size - 4];
+ for (int i = 0; i < array_size - 4; i ++) {
+ for (int j = 0; j < array_size; j ++) {
+ if (ptr[i] == InstLabel[j]) {
+ InstLength[i] = InstLabel[j + 1] - InstLabel[j];
+ break;
+ }
+ }
+ }
+ for (int i = 0; i < array_size - 4; i ++)
+ DEBUG_LOG(ARM11, "[%d]:%d\n", i, InstLength[i]);
+}
+
+int clz(unsigned int x)
+{
+ int n;
+ if (x == 0) return (32);
+ n = 1;
+ if ((x >> 16) == 0) { n = n + 16; x = x << 16;}
+ if ((x >> 24) == 0) { n = n + 8; x = x << 8;}
+ if ((x >> 28) == 0) { n = n + 4; x = x << 4;}
+ if ((x >> 30) == 0) { n = n + 2; x = x << 2;}
+ n = n - (x >> 31);
+ return n;
+}
+
+unsigned arm_dyncom_SWI (ARMul_State * state, ARMword number);
+
+static bool InAPrivilegedMode(arm_core_t *core)
+{
+ return (core->Mode != USER32MODE);
+}
+
+/* r15 = r15 + 8 */
+void InterpreterMainLoop(ARMul_State* state)
+{
+ #define CRn inst_cream->crn
+ #define OPCODE_2 inst_cream->opcode_2
+ #define CRm inst_cream->crm
+ #define CP15_REG(n) cpu->CP15[CP15(n)]
+ #define RD cpu->Reg[inst_cream->Rd]
+ #define RN cpu->Reg[inst_cream->Rn]
+ #define RM cpu->Reg[inst_cream->Rm]
+ #define RS cpu->Reg[inst_cream->Rs]
+ #define RDHI cpu->Reg[inst_cream->RdHi]
+ #define RDLO cpu->Reg[inst_cream->RdLo]
+ #define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4)
+ #define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24)
+ #define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand)
+
+ #if ENABLE_ICOUNTER
+ #define INC_ICOUNTER cpu->icounter++; \
+ if(cpu->Reg[15] > 0xc0000000) \
+ cpu->kernel_icounter++;
+ //if (debug_function(core)) \
+ if (core->check_int_flag) \
+ goto END
+ //DEBUG_LOG(ARM11, "icounter is %llx line is %d pc is %x\n", cpu->icounter, __LINE__, cpu->Reg[15])
+ #else
+ #define INC_ICOUNTER ;
+ #endif
+
+ #define FETCH_INST if (inst_base->br != NON_BRANCH) \
+ goto PROFILING; \
+ inst_base = (arm_inst *)&inst_buf[ptr]
+#define INC_PC(l) ptr += sizeof(arm_inst) + l
+
+#ifdef __GNUC__
+#define GOTO_NEXT_INST goto *InstLabel[inst_base->idx]
+#else
+#define GOTO_NEXT_INST switch(inst_base->idx) { \
+ case 0: goto VMLA_INST; \
+ case 1: goto VMLS_INST; \
+ case 2: goto VNMLA_INST; \
+ case 3: goto VNMLA_INST; \
+ case 4: goto VNMLS_INST; \
+ case 5: goto VNMUL_INST; \
+ case 6: goto VMUL_INST; \
+ case 7: goto VADD_INST; \
+ case 8: goto VSUB_INST; \
+ case 9: goto VDIV_INST; \
+ case 10: goto VMOVI_INST; \
+ case 11: goto VMOVR_INST; \
+ case 12: goto VABS_INST; \
+ case 13: goto VNEG_INST; \
+ case 14: goto VSQRT_INST; \
+ case 15: goto VCMP_INST; \
+ case 16: goto VCMP2_INST; \
+ case 17: goto VCVTBDS_INST; \
+ case 18: goto VCVTBFF_INST; \
+ case 19: goto VCVTBFI_INST; \
+ case 20: goto VMOVBRS_INST; \
+ case 21: goto VMSR_INST; \
+ case 22: goto VMOVBRC_INST; \
+ case 23: goto VMRS_INST; \
+ case 24: goto VMOVBCR_INST; \
+ case 25: goto VMOVBRRSS_INST; \
+ case 26: goto VMOVBRRD_INST; \
+ case 27: goto VSTR_INST; \
+ case 28: goto VPUSH_INST; \
+ case 29: goto VSTM_INST; \
+ case 30: goto VPOP_INST; \
+ case 31: goto VLDR_INST; \
+ case 32: goto VLDM_INST ; \
+ case 33: goto SRS_INST; \
+ case 34: goto RFE_INST; \
+ case 35: goto BKPT_INST; \
+ case 36: goto BLX_INST; \
+ case 37: goto CPS_INST; \
+ case 38: goto PLD_INST; \
+ case 39: goto SETEND_INST; \
+ case 40: goto CLREX_INST; \
+ case 41: goto REV16_INST; \
+ case 42: goto USAD8_INST; \
+ case 43: goto SXTB_INST; \
+ case 44: goto UXTB_INST; \
+ case 45: goto SXTH_INST; \
+ case 46: goto SXTB16_INST; \
+ case 47: goto UXTH_INST; \
+ case 48: goto UXTB16_INST; \
+ case 49: goto CPY_INST; \
+ case 50: goto UXTAB_INST; \
+ case 51: goto SSUB8_INST; \
+ case 52: goto SHSUB8_INST; \
+ case 53: goto SSUBADDX_INST; \
+ case 54: goto STREX_INST; \
+ case 55: goto STREXB_INST; \
+ case 56: goto SWP_INST; \
+ case 57: goto SWPB_INST; \
+ case 58: goto SSUB16_INST; \
+ case 59: goto SSAT16_INST; \
+ case 60: goto SHSUBADDX_INST; \
+ case 61: goto QSUBADDX_INST; \
+ case 62: goto SHADDSUBX_INST; \
+ case 63: goto SHADD8_INST; \
+ case 64: goto SHADD16_INST; \
+ case 65: goto SEL_INST; \
+ case 66: goto SADDSUBX_INST; \
+ case 67: goto SADD8_INST; \
+ case 68: goto SADD16_INST; \
+ case 69: goto SHSUB16_INST; \
+ case 70: goto UMAAL_INST; \
+ case 71: goto UXTAB16_INST; \
+ case 72: goto USUBADDX_INST; \
+ case 73: goto USUB8_INST; \
+ case 74: goto USUB16_INST; \
+ case 75: goto USAT16_INST; \
+ case 76: goto USADA8_INST; \
+ case 77: goto UQSUBADDX_INST; \
+ case 78: goto UQSUB8_INST; \
+ case 79: goto UQSUB16_INST; \
+ case 80: goto UQADDSUBX_INST; \
+ case 81: goto UQADD8_INST; \
+ case 82: goto UQADD16_INST; \
+ case 83: goto SXTAB_INST; \
+ case 84: goto UHSUBADDX_INST; \
+ case 85: goto UHSUB8_INST; \
+ case 86: goto UHSUB16_INST; \
+ case 87: goto UHADDSUBX_INST; \
+ case 88: goto UHADD8_INST; \
+ case 89: goto UHADD16_INST; \
+ case 90: goto UADDSUBX_INST; \
+ case 91: goto UADD8_INST; \
+ case 92: goto UADD16_INST; \
+ case 93: goto SXTAH_INST; \
+ case 94: goto SXTAB16_INST; \
+ case 95: goto QADD8_INST; \
+ case 96: goto BXJ_INST; \
+ case 97: goto CLZ_INST; \
+ case 98: goto UXTAH_INST; \
+ case 99: goto BX_INST; \
+ case 100: goto REV_INST; \
+ case 101: goto BLX_INST; \
+ case 102: goto REVSH_INST; \
+ case 103: goto QADD_INST; \
+ case 104: goto QADD16_INST; \
+ case 105: goto QADDSUBX_INST; \
+ case 106: goto LDREX_INST; \
+ case 107: goto QDADD_INST; \
+ case 108: goto QDSUB_INST; \
+ case 109: goto QSUB_INST; \
+ case 110: goto LDREXB_INST; \
+ case 111: goto QSUB8_INST; \
+ case 112: goto QSUB16_INST; \
+ case 113: goto SMUAD_INST; \
+ case 114: goto SMMUL_INST; \
+ case 115: goto SMUSD_INST; \
+ case 116: goto SMLSD_INST; \
+ case 117: goto SMLSLD_INST; \
+ case 118: goto SMMLA_INST; \
+ case 119: goto SMMLS_INST; \
+ case 120: goto SMLALD_INST; \
+ case 121: goto SMLAD_INST; \
+ case 122: goto SMLAW_INST; \
+ case 123: goto SMULW_INST; \
+ case 124: goto PKHTB_INST; \
+ case 125: goto PKHBT_INST; \
+ case 126: goto SMUL_INST; \
+ case 127: goto SMLAL_INST; \
+ case 128: goto SMLA_INST; \
+ case 129: goto MCRR_INST; \
+ case 130: goto MRRC_INST; \
+ case 131: goto CMP_INST; \
+ case 132: goto TST_INST; \
+ case 133: goto TEQ_INST; \
+ case 134: goto CMN_INST; \
+ case 135: goto SMULL_INST; \
+ case 136: goto UMULL_INST; \
+ case 137: goto UMLAL_INST; \
+ case 138: goto SMLAL_INST; \
+ case 139: goto MUL_INST; \
+ case 140: goto MLA_INST; \
+ case 141: goto SSAT_INST; \
+ case 142: goto USAT_INST; \
+ case 143: goto MRS_INST; \
+ case 144: goto MSR_INST; \
+ case 145: goto AND_INST; \
+ case 146: goto BIC_INST; \
+ case 147: goto LDM_INST; \
+ case 148: goto EOR_INST; \
+ case 149: goto ADD_INST; \
+ case 150: goto RSB_INST; \
+ case 151: goto RSC_INST; \
+ case 152: goto SBC_INST; \
+ case 153: goto ADC_INST; \
+ case 154: goto SUB_INST; \
+ case 155: goto ORR_INST; \
+ case 156: goto MVN_INST; \
+ case 157: goto MOV_INST; \
+ case 158: goto STM_INST; \
+ case 159: goto LDM_INST; \
+ case 160: goto LDRSH_INST; \
+ case 161: goto STM_INST; \
+ case 162: goto LDM_INST; \
+ case 163: goto LDRSB_INST; \
+ case 164: goto STRD_INST; \
+ case 165: goto LDRH_INST; \
+ case 166: goto STRH_INST; \
+ case 167: goto LDRD_INST; \
+ case 168: goto STRT_INST; \
+ case 169: goto STRBT_INST; \
+ case 170: goto LDRBT_INST; \
+ case 171: goto LDRT_INST; \
+ case 172: goto MRC_INST; \
+ case 173: goto MCR_INST; \
+ case 174: goto MSR_INST; \
+ case 175: goto LDRB_INST; \
+ case 176: goto STRB_INST; \
+ case 177: goto LDR_INST; \
+ case 178: goto LDRCOND_INST ; \
+ case 179: goto STR_INST; \
+ case 180: goto CDP_INST; \
+ case 181: goto STC_INST; \
+ case 182: goto LDC_INST; \
+ case 183: goto SWI_INST; \
+ case 184: goto BBL_INST; \
+ case 185: goto B_2_THUMB ; \
+ case 186: goto B_COND_THUMB ; \
+ case 187: goto BL_1_THUMB ; \
+ case 188: goto BL_2_THUMB ; \
+ case 189: goto BLX_1_THUMB ; \
+ case 190: goto DISPATCH; \
+ case 191: goto INIT_INST_LENGTH; \
+ case 192: goto END; \
+ }
+#endif
+
+ #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0)
+ #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1)
+// #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((ISNEG(lop) && ISPOS(rop)) || \
+ (ISNEG(lop) && ISPOS(dst)) || \
+ (ISPOS(rop) && ISPOS(dst))))
+ #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((dst < lop) || (dst < rop)))
+ #define UPDATE_CFLAG_CARRY_FROM_ADD(lop, rop, flag) (cpu->CFlag = (((uint64_t) lop + (uint64_t) rop + (uint64_t) flag) > 0xffffffff) )
+ #define UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(lop, rop, flag) (cpu->CFlag = ((uint64_t) lop >= ((uint64_t) rop + (uint64_t) flag)))
+ #define UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop) (cpu->CFlag = (lop >= rop))
+ #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) (cpu->CFlag = !(dst < lop))
+ #define UPDATE_CFLAG_WITH_SC cpu->CFlag = cpu->shifter_carry_out
+// #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) cpu->CFlag = !((ISNEG(lop) && ISPOS(rop)) || \
+ (ISNEG(lop) && ISPOS(dst)) || \
+ (ISPOS(rop) && ISPOS(dst)))
+ #define UPDATE_VFLAG(dst, lop, rop) (cpu->VFlag = (((lop < 0) && (rop < 0) && (dst >= 0)) || \
+ ((lop >= 0) && (rop) >= 0 && (dst < 0))))
+ #define UPDATE_VFLAG_WITH_NOT(dst, lop, rop) (cpu->VFlag = !(((lop < 0) && (rop < 0) && (dst >= 0)) || \
+ ((lop >= 0) && (rop) >= 0 && (dst < 0))))
+ #define UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop) (cpu->VFlag = (((lop ^ rop) & (lop ^ dst)) >> 31))
+
+ #define SAVE_NZCVT cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | \
+ (cpu->NFlag << 31) | \
+ (cpu->ZFlag << 30) | \
+ (cpu->CFlag << 29) | \
+ (cpu->VFlag << 28) | \
+ (cpu->TFlag << 5)
+ #define LOAD_NZCVT cpu->NFlag = (cpu->Cpsr >> 31); \
+ cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \
+ cpu->CFlag = (cpu->Cpsr >> 29) & 1; \
+ cpu->VFlag = (cpu->Cpsr >> 28) & 1; \
+ cpu->TFlag = (cpu->Cpsr >> 5) & 1;
+
+ #define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE)
+ #define PC (cpu->Reg[15])
+ #define CHECK_EXT_INT if (!cpu->NirqSig) { \
+ if (!(cpu->Cpsr & 0x80)) { \
+ goto END; \
+ } \
+ }
+
+
+
+ //arm_processor *cpu = (arm_processor *)get_cast_conf_obj(core->cpu_data, "arm_core_t");
+ arm_processor *cpu = state; //(arm_processor *)(core->cpu_data->obj);
+
+#if __GNUC__
+ void *InstLabel[] = {
+ #define VFP_INTERPRETER_LABEL
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+ #undef VFP_INTERPRETER_LABEL
+ &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST,
+ &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST,
+ &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST,
+ &&SHADD8_INST,&&SHADD16_INST,&&SEL_INST,&&SADDSUBX_INST,&&SADD8_INST,&&SADD16_INST,&&SHSUB16_INST,&&UMAAL_INST,&&UXTAB16_INST,
+ &&USUBADDX_INST,&&USUB8_INST,&&USUB16_INST,&&USAT16_INST,&&USADA8_INST,&&UQSUBADDX_INST,&&UQSUB8_INST,&&UQSUB16_INST,
+ &&UQADDSUBX_INST,&&UQADD8_INST,&&UQADD16_INST,&&SXTAB_INST,&&UHSUBADDX_INST,&&UHSUB8_INST,&&UHSUB16_INST,&&UHADDSUBX_INST,&&UHADD8_INST,
+ &&UHADD16_INST,&&UADDSUBX_INST,&&UADD8_INST,&&UADD16_INST,&&SXTAH_INST,&&SXTAB16_INST,&&QADD8_INST,&&BXJ_INST,&&CLZ_INST,&&UXTAH_INST,
+ &&BX_INST,&&REV_INST,&&BLX_INST,&&REVSH_INST,&&QADD_INST,&&QADD16_INST,&&QADDSUBX_INST,&&LDREX_INST,&&QDADD_INST,&&QDSUB_INST,
+ &&QSUB_INST,&&LDREXB_INST,&&QSUB8_INST,&&QSUB16_INST,&&SMUAD_INST,&&SMMUL_INST,&&SMUSD_INST,&&SMLSD_INST,&&SMLSLD_INST,&&SMMLA_INST,
+ &&SMMLS_INST,&&SMLALD_INST,&&SMLAD_INST,&&SMLAW_INST,&&SMULW_INST,&&PKHTB_INST,&&PKHBT_INST,&&SMUL_INST,&&SMLAL_INST,&&SMLA_INST,
+ &&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST,
+ &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
+ &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
+ &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
+ &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&B_2_THUMB, &&B_COND_THUMB,
+ &&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,&&INIT_INST_LENGTH,&&END
+ };
+#endif
+ arm_inst * inst_base;
+ unsigned int lop, rop, dst;
+ unsigned int addr;
+ unsigned int phys_addr;
+ unsigned int last_pc = 0;
+ fault_t fault;
+ static unsigned int last_physical_base = 0, last_logical_base = 0;
+ int ptr;
+
+ LOAD_NZCVT;
+ DISPATCH:
+ {
+ if (cpu->NumInstrsToExecute == 0)
+ return;
+
+ cpu->NumInstrsToExecute--;
+
+ //NOTICE_LOG(ARM11, "instr!");
+
+ if (!cpu->NirqSig) {
+ if (!(cpu->Cpsr & 0x80)) {
+ goto END;
+ }
+ }
+
+ if (cpu->TFlag) {
+ cpu->Reg[15] &= 0xfffffffe;
+ } else
+ cpu->Reg[15] &= 0xfffffffc;
+#if PROFILE
+ /* check next instruction address is valid. */
+ last_pc = cpu->Reg[15];
+#endif
+#if USER_MODE_OPT
+ phys_addr = cpu->Reg[15];
+#else
+ {
+ if (last_logical_base == (cpu->Reg[15] & 0xfffff000))
+ phys_addr = last_physical_base + (cpu->Reg[15] & 0xfff);
+ else {
+ /* check next instruction address is valid. */
+ fault = check_address_validity(cpu, cpu->Reg[15], &phys_addr, 1, INSN_TLB);
+ if (fault) {
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_PrefetchAbortV;
+ cpu->AbortAddr = cpu->Reg[15];
+ cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = cpu->Reg[15];
+ goto END;
+ }
+ last_logical_base = cpu->Reg[15] & 0xfffff000;
+ last_physical_base = phys_addr & 0xfffff000;
+ }
+ }
+#if HYBRID_MODE
+ /* check if the native code of dyncom is available */
+ //fast_map hash_map = core->dyncom_engine->fmap;
+ //void * pfunc = NULL;
+ //PFUNC(phys_addr);
+ //if(pfunc){
+ if(is_translated_entry(core, phys_addr)){
+ int rc = JIT_RETURN_NOERR;
+ //DEBUG_LOG(ARM11, "enter jit icounter is %lld, pc=0x%x\n", core->icounter, cpu->Reg[15]);
+ SAVE_NZCVT;
+// resume_timing();
+ rc = cpu_run(core);
+ LOAD_NZCVT;
+ //DEBUG_LOG(ARM11, "out of jit ret is %d icounter is %lld, pc=0x%x\n", rc, core->icounter, cpu->Reg[15]);
+ if((rc == JIT_RETURN_FUNCNOTFOUND) || (rc == JIT_RETURN_FUNC_BLANK)){
+ /* keep the tflag same with the bit in CPSR */
+ //cpu->TFlag = cpu->Cpsr & (1 << THUMB_BIT);
+ //cpu->TFlag = cpu->Cpsr & (1 << 5);
+ //switch_mode(cpu, cpu->Cpsr & 0x1f);
+ //DEBUG_LOG(ARM11, "FUNCTION not found , pc=0x%x\n", cpu->Reg[15]);
+ fault = check_address_validity(cpu, cpu->Reg[15], &phys_addr, 1, INSN_TLB);
+ if (fault) {
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_PrefetchAbortV;
+ cpu->AbortAddr = cpu->Reg[15];
+ cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = cpu->Reg[15];
+ goto END;
+ }
+ last_logical_base = cpu->Reg[15] & 0xfffff000;
+ last_physical_base = phys_addr & 0xfffff000;
+ core->current_page_phys = last_physical_base;
+ core->current_page_effec = last_logical_base;
+ //push_to_compiled(core, phys_addr);
+ }
+ else{
+ if((cpu->CP15[CP15(CP15_TLB_FAULT_STATUS)] & 0xf0)){
+ //DEBUG_LOG(ARM11, "\n\n###############In %s, fsr=0x%x, fault_addr=0x%x, pc=0x%x\n\n", __FUNCTION__, cpu->CP15[CP15(CP15_FAULT_STATUS)], cpu->CP15[CP15(CP15_FAULT_ADDRESS)], cpu->Reg[15]);
+ //core->Reg[15] -= get_instr_size(cpu_dyncom);
+ fill_tlb(cpu);
+ goto END;
+ }
+ if (cpu->syscallSig) {
+ goto END;
+ }
+ if (cpu->abortSig) {
+ cpu->CP15[CP15_TLB_FAULT_STATUS - CP15_BASE] &= 0xFFFFFFF0;
+ goto END;
+ }
+ if (!cpu->NirqSig) {
+ if (!(cpu->Cpsr & 0x80)) {
+ goto END;
+ }
+ }
+
+ /* if regular trap */
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ /*uint32_t mode = cpu->Cpsr & 0x1f;
+ if ((mode != cpu->Mode) && (!is_user_mode(core))) {
+ switch_mode(cpu, mode);
+ return 1;
+ }*/
+
+ goto END;
+ }
+ //phys_addr = cpu->Reg[15];
+ }
+ else{
+ if (last_logical_base == (cpu->Reg[15] & 0xfffff000))
+ phys_addr = last_physical_base + (cpu->Reg[15] & 0xfff);
+ else {
+ /* check next instruction address is valid. */
+ fault = check_address_validity(cpu, cpu->Reg[15], &phys_addr, 1, INSN_TLB);
+ if (fault) {
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_PrefetchAbortV;
+ cpu->AbortAddr = cpu->Reg[15];
+ cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = cpu->Reg[15];
+ goto END;
+ }
+ last_logical_base = cpu->Reg[15] & 0xfffff000;
+ last_physical_base = phys_addr & 0xfffff000;
+ }
+ }
+#endif /* #if HYBRID_MODE */
+#endif /* #if USER_MODE_OPT */
+ if (true){//if(is_fast_interp_code(core, phys_addr)){
+ if (find_bb(phys_addr, ptr) == -1)
+ if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
+ goto END;
+ }
+ else{
+ if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
+ goto END;
+ }
+#if PROFILE
+ resume_timing();
+#endif
+ inst_base = (arm_inst *)&inst_buf[ptr];
+ GOTO_NEXT_INST;
+ }
+ PROFILING:
+ {
+ goto DISPATCH;
+ }
+ ADC_INST:
+ {
+ INC_ICOUNTER;
+ adc_inst *inst_cream = (adc_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ unsigned int sht_op = SHIFTER_OPERAND;
+ rop = SHIFTER_OPERAND + cpu->CFlag;
+ RD = dst = lop + rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_CARRY_FROM_ADD(lop, sht_op, cpu->CFlag);
+ UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(adc_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(adc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ ADD_INST:
+ {
+ INC_ICOUNTER;
+ add_inst *inst_cream = (add_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ if (inst_cream->Rn == 15) {
+ lop += 2 * GET_INST_SIZE(cpu);
+ }
+ rop = SHIFTER_OPERAND;
+ RD = dst = lop + rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr*/
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Cpsr & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG(dst, lop, rop);
+ UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(add_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(add_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ AND_INST:
+ {
+ INC_ICOUNTER;
+ and_inst *inst_cream = (and_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ rop = SHIFTER_OPERAND;
+ RD = dst = lop & rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr*/
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Cpsr & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ //UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(and_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(and_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ BBL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
+ if (inst_cream->L) {
+ LINK_RTN_ADDR;
+ }
+ SET_PC;
+ INC_PC(sizeof(bbl_inst));
+ goto PROFILING;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(bbl_inst));
+ goto PROFILING;
+ }
+ BIC_INST:
+ {
+ INC_ICOUNTER;
+ bic_inst *inst_cream = (bic_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ if (inst_cream->Rn == 15) {
+ lop += 2 * GET_INST_SIZE(cpu);
+ }
+ rop = SHIFTER_OPERAND;
+// RD = dst = lop & (rop ^ 0xffffffff);
+ RD = dst = lop & (~rop);
+ if ((inst_cream->S) && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(bic_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(bic_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ BKPT_INST:
+ BLX_INST:
+ {
+ INC_ICOUNTER;
+ blx_inst *inst_cream = (blx_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int inst = inst_cream->inst;
+ if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
+ //LINK_RTN_ADDR;
+ cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu));
+ if(cpu->TFlag)
+ cpu->Reg[14] |= 0x1;
+ cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe;
+ cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1;
+ //cpu->Reg[15] = cpu->Reg[BITS(inst, 0, 3)] & 0xfffffffe;
+ //cpu->TFlag = cpu->Reg[BITS(inst, 0, 3)] & 0x1;
+ } else {
+ cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu));
+ cpu->TFlag = 0x1;
+ int signed_int = inst_cream->val.signed_immed_24;
+ signed_int = (signed_int) & 0x800000 ? (0x3F000000 | signed_int) : signed_int;
+ signed_int = signed_int << 2;
+ // cpu->Reg[15] = cpu->Reg[15] + 2 * GET_INST_SIZE(cpu)
+ cpu->Reg[15] = cpu->Reg[15] + 8
+ + signed_int + (BIT(inst, 24) << 1);
+ //DEBUG_MSG;
+ }
+ INC_PC(sizeof(blx_inst));
+ goto PROFILING;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+// INC_PC(sizeof(bx_inst));
+ INC_PC(sizeof(blx_inst));
+ goto PROFILING;
+ }
+ BX_INST:
+ {
+ INC_ICOUNTER;
+ bx_inst *inst_cream = (bx_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (inst_cream->Rm == 15)
+ DEBUG_LOG(ARM11, "In %s, BX at pc %x: use of Rm = R15 is discouraged\n", __FUNCTION__, cpu->Reg[15]);
+ cpu->TFlag = cpu->Reg[inst_cream->Rm] & 0x1;
+ cpu->Reg[15] = cpu->Reg[inst_cream->Rm] & 0xfffffffe;
+// cpu->TFlag = cpu->Reg[inst_cream->Rm] & 0x1;
+ INC_PC(sizeof(bx_inst));
+ goto PROFILING;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+// INC_PC(sizeof(bx_inst));
+ INC_PC(sizeof(bx_inst));
+ goto PROFILING;
+ }
+ BXJ_INST:
+ CDP_INST:
+ {
+ INC_ICOUNTER;
+ cdp_inst *inst_cream = (cdp_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ /* FIXME, check if cp access allowed */
+ #define CP_ACCESS_ALLOW 0
+ if(CP_ACCESS_ALLOW){
+ /* undefined instruction here */
+ return;
+ }
+ ERROR_LOG(ARM11, "CDP insn inst=0x%x, pc=0x%x\n", inst_cream->inst, cpu->Reg[15]);
+ unsigned cpab = (cpu->CDP[inst_cream->cp_num]) (cpu, ARMul_FIRST, inst_cream->inst);
+ if(cpab != ARMul_DONE){
+ ERROR_LOG(ARM11, "CDP insn wrong, inst=0x%x, cp_num=0x%x\n", inst_cream->inst, inst_cream->cp_num);
+ //CITRA_IGNORE_EXIT(-1);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(cdp_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
+ CLREX_INST:
+ {
+ INC_ICOUNTER;
+ remove_exclusive(cpu, 0);
+ cpu->exclusive_state = 0;
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(clrex_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ CLZ_INST:
+ {
+ INC_ICOUNTER;
+ clz_inst *inst_cream = (clz_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ RD = clz(RM);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(clz_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ CMN_INST:
+ {
+ INC_ICOUNTER;
+ cmn_inst *inst_cream = (cmn_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+// DEBUG_LOG(ARM11, "RN is %x\n", RN);
+ lop = RN;
+ rop = SHIFTER_OPERAND;
+ dst = lop + rop;
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG(dst, lop, rop);
+ UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(cmn_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ CMP_INST:
+ {
+// DEBUG_LOG(ARM11, "cmp inst\n");
+// DEBUG_LOG(ARM11, "pc: %x\n", cpu->Reg[15]);
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+// DEBUG_LOG(ARM11, "r0 is %x\n", cpu->Reg[0]);
+ cmp_inst *inst_cream = (cmp_inst *)inst_base->component;
+ lop = RN;
+ if (inst_cream->Rn == 15) {
+ lop += 2 * GET_INST_SIZE(cpu);
+ }
+ rop = SHIFTER_OPERAND;
+ dst = lop - rop;
+
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+// UPDATE_CFLAG(dst, lop, rop);
+ UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
+// UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
+// UPDATE_VFLAG_WITH_NOT(dst, lop, rop);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(cmp_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ CPS_INST:
+ {
+ INC_ICOUNTER;
+ cps_inst *inst_cream = (cps_inst *)inst_base->component;
+ uint32_t aif_val = 0;
+ uint32_t aif_mask = 0;
+ if (InAPrivilegedMode(cpu)) {
+ /* isInAPrivilegedMode */
+ if (inst_cream->imod1) {
+ if (inst_cream->A) {
+ aif_val |= (inst_cream->imod0 << 8);
+ aif_mask |= 1 << 8;
+ }
+ if (inst_cream->I) {
+ aif_val |= (inst_cream->imod0 << 7);
+ aif_mask |= 1 << 7;
+ }
+ if (inst_cream->F) {
+ aif_val |= (inst_cream->imod0 << 6);
+ aif_mask |= 1 << 6;
+ }
+ aif_mask = ~aif_mask;
+ cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val;
+ }
+ if (inst_cream->mmod) {
+ cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode;
+ switch_mode(cpu, inst_cream->mode);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(cps_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ CPY_INST:
+ {
+ INC_ICOUNTER;
+ mov_inst *inst_cream = (mov_inst *)inst_base->component;
+// cpy_inst *inst_cream = (cpy_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ RD = SHIFTER_OPERAND;
+// RD = RM;
+ if ((inst_cream->Rd == 15)) {
+ INC_PC(sizeof(mov_inst));
+ goto PROFILING;
+ }
+ }
+// DEBUG_LOG(ARM11, "cpy inst %x\n", cpu->Reg[15]);
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mov_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ EOR_INST:
+ {
+ INC_ICOUNTER;
+ eor_inst *inst_cream = (eor_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ if (inst_cream->Rn == 15) {
+ lop += 2 * GET_INST_SIZE(cpu);
+ }
+ rop = SHIFTER_OPERAND;
+ RD = dst = lop ^ rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr*/
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+// UPDATE_CFLAG(dst, lop, rop);
+// UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(eor_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(eor_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDC_INST:
+ {
+ INC_ICOUNTER;
+ /* NOT IMPL */
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDM_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ int i;
+ unsigned int ret;
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ unsigned int inst = inst_cream->inst;
+ if (BIT(inst, 22) && !BIT(inst, 15)) {
+// DEBUG_MSG;
+ #if 1
+ /* LDM (2) user */
+ for (i = 0; i < 13; i++) {
+ if(BIT(inst, i)){
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ //if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[i] = ret;
+ addr += 4;
+ if ((addr & 0xfff) == 0) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ } else {
+ phys_addr += 4;
+ }
+ }
+ }
+ if (BIT(inst, 13)) {
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ //if (fault) goto MMU_EXCEPTION;
+ if (cpu->Mode == USER32MODE)
+ cpu->Reg[13] = ret;
+ else
+ cpu->Reg_usr[0] = ret;
+ addr += 4;
+ if ((addr & 0xfff) == 0) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ } else {
+ phys_addr += 4;
+ }
+ }
+ if (BIT(inst, 14)) {
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ //if (fault) goto MMU_EXCEPTION;
+ if (cpu->Mode == USER32MODE)
+ cpu->Reg[14] = ret;
+ else
+ cpu->Reg_usr[1] = ret;
+ }
+ #endif
+ } else if (!BIT(inst, 22)) {
+ for( i = 0; i < 16; i ++ ){
+ if(BIT(inst, i)){
+ //bus_read(32, addr, &ret);
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ if (fault) goto MMU_EXCEPTION;
+ /* For armv5t, should enter thumb when bits[0] is non-zero. */
+ if(i == 15){
+ cpu->TFlag = ret & 0x1;
+ ret &= 0xFFFFFFFE;
+ //DEBUG_LOG(ARM11, "In %s, TFlag ret=0x%x\n", __FUNCTION__, ret);
+ }
+
+ cpu->Reg[i] = ret;
+ addr += 4;
+ if ((addr & 0xfff) == 0) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ } else {
+ phys_addr += 4;
+ }
+ }
+ }
+ } else if (BIT(inst, 22) && BIT(inst, 15)) {
+ for( i = 0; i < 15; i ++ ){
+ if(BIT(inst, i)){
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ //if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[i] = ret;
+ addr += 4;
+ if ((addr & 0xfff) == 0) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ } else {
+ phys_addr += 4;
+ }
+ }
+ }
+
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Cpsr & 0x1f);
+ LOAD_NZCVT;
+ }
+ #if 0
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ #endif
+ fault = interpreter_read_memory(addr, phys_addr, ret, 32);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] = ret;
+ #if 0
+ addr += 4;
+ phys_addr += 4;
+ #endif
+ }
+ if (BIT(inst, 15)) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SXTH_INST:
+ {
+ INC_ICOUNTER;
+ sxth_inst *inst_cream = (sxth_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
+ if (BIT(operand2, 15)) {
+ operand2 |= 0xffff0000;
+ } else {
+ operand2 &= 0xffff;
+ }
+ RD = operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(sxth_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDR_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ //if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ //bus_read(32, addr, &value);
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ else {
+ value = ROTATE_RIGHT_32(value,(8*(addr&0x3)));
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ }
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ /* For armv5t, should enter thumb when bits[0] is non-zero. */
+ cpu->TFlag = value & 0x1;
+ cpu->Reg[15] &= 0xFFFFFFFE;
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ //}
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRCOND_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if (CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ //bus_read(32, addr, &value);
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ else {
+ value = ROTATE_RIGHT_32(value,(8*(addr&0x3)));
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ }
+
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ /* For armv5t, should enter thumb when bits[0] is non-zero. */
+ cpu->TFlag = value & 0x1;
+ cpu->Reg[15] &= 0xFFFFFFFE;
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UXTH_INST:
+ {
+ INC_ICOUNTER;
+ uxth_inst *inst_cream = (uxth_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
+ & 0xffff;
+ RD = operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(uxth_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UXTAH_INST:
+ {
+ INC_ICOUNTER;
+ uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
+ & 0xffff;
+ RD = RN + operand2;
+ if (inst_cream->Rn == 15 || inst_cream->Rm == 15) {
+ DEBUG_LOG(ARM11, "in line %d\n", __LINE__);
+ CITRA_IGNORE_EXIT(-1);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(uxtah_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRB_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ //bus_read(8, addr, &value);
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRBT_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRD_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ /* Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) */
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ uint32_t rear_phys_addr;
+ fault = check_address_validity(cpu, addr + 4, &rear_phys_addr, 1);
+ if(fault){
+ ERROR_LOG(ARM11, "mmu fault , should rollback the above get_addr\n");
+ CITRA_IGNORE_EXIT(-1);
+ goto MMU_EXCEPTION;
+ }
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ fault = interpreter_read_memory(addr + 4, rear_phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = value;
+ /* No dispatch since this operation should not modify R15 */
+ }
+ cpu->Reg[15] += 4;
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
+ LDREX_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+
+ add_exclusive_addr(cpu, phys_addr);
+ cpu->exclusive_state = 1;
+
+ //bus_read(32, addr, &value);
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDREXB_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+
+ add_exclusive_addr(cpu, phys_addr);
+ cpu->exclusive_state = 1;
+
+ //bus_read(8, addr, &value);
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRH_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = 0;
+ fault = interpreter_read_memory(addr, phys_addr, value, 16);
+// fault = interpreter_read_memory(addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ //if (value == 0xffff && cpu->icounter > 190000000 && cpu->icounter < 210000000) {
+ // value = 0xffffffff;
+ //}
+ //bus_read(16, addr, &value);
+// cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value & 0xffff;
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRSB_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+// DEBUG_LOG(ARM11, "ldrsb addr is %x\n", addr);
+ fault = interpreter_read_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ //bus_read(8, addr, &value);
+ if (BIT(value, 7)) {
+ value |= 0xffffff00;
+ }
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRSH_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 16);
+ if (fault) goto MMU_EXCEPTION;
+ //bus_read(16, addr, &value);
+ if (BIT(value, 15)) {
+ value |= 0xffff0000;
+ }
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ LDRT_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+
+ if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ else
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ROTATE_RIGHT_32(value,(8*(addr&0x3))) ;
+
+ if (BITS(inst_cream->inst, 12, 15) == 15) {
+ INC_PC(sizeof(ldst_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MCR_INST:
+ {
+ INC_ICOUNTER;
+ /* NOT IMPL */
+ mcr_inst *inst_cream = (mcr_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int inst = inst_cream->inst;
+ if (inst_cream->Rd == 15) {
+ DEBUG_MSG;
+ } else {
+ if (inst_cream->cp_num == 15) {
+ if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
+ //LET(RD, CONST(0x0007b000));
+ //LET(RD, CONST(0x410FB760));
+ //LET(CP15_MAIN_ID, R(RD));
+ CP15_REG(CP15_MAIN_ID) = RD;
+ } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
+ //LET(RD, R(CP15_CONTROL));
+ CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
+ } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
+ //LET(RD, R(CP15_CONTROL));
+ CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
+ } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(CP15_CONTROL, R(RD));
+ CP15_REG(CP15_CONTROL) = RD;
+ } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(CP15_DOMAIN_ACCESS_CONTROL, R(RD));
+ CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(CP15_TRANSLATION_BASE_TABLE_0, R(RD));
+ CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
+ //LET(CP15_TRANSLATION_BASE_TABLE_1, R(RD));
+ CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
+ //LET(CP15_TRANSLATION_BASE_CONTROL, R(RD));
+ CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
+ } else if(CRn == MMU_CACHE_OPS){
+ //SKYEYE_WARNING("cache operation have not implemented.\n");
+ } else if(CRn == MMU_TLB_OPS){
+ switch (CRm) {
+ case 5: /* ITLB */
+ switch(OPCODE_2){
+ case 0: /* invalidate all */
+ //invalidate_all_tlb(state);
+ DEBUG_LOG(ARM11, "{TLB} [INSN] invalidate all\n");
+ //remove_tlb(INSN_TLB);
+ //erase_all(core, INSN_TLB);
+ break;
+ case 1: /* invalidate by MVA */
+ //invalidate_by_mva(state, value);
+ //DEBUG_LOG(ARM11, "{TLB} [INSN] invalidate by mva\n");
+ //remove_tlb_by_mva(RD, INSN_TLB);
+ //erase_by_mva(core, RD, INSN_TLB);
+ break;
+ case 2: /* invalidate by asid */
+ //invalidate_by_asid(state, value);
+ //DEBUG_LOG(ARM11, "{TLB} [INSN] invalidate by asid\n");
+ //erase_by_asid(core, RD, INSN_TLB);
+ break;
+ default:
+ break;
+ }
+
+ break;
+ case 6: /* DTLB */
+ switch(OPCODE_2){
+ case 0: /* invalidate all */
+ //invalidate_all_tlb(state);
+ //remove_tlb(DATA_TLB);
+ //erase_all(core, DATA_TLB);
+ DEBUG_LOG(ARM11, "{TLB} [DATA] invalidate all\n");
+ break;
+ case 1: /* invalidate by MVA */
+ //invalidate_by_mva(state, value);
+ //remove_tlb_by_mva(RD, DATA_TLB);
+ //erase_by_mva(core, RD, DATA_TLB);
+ //DEBUG_LOG(ARM11, "{TLB} [DATA] invalidate by mva\n");
+ break;
+ case 2: /* invalidate by asid */
+ //invalidate_by_asid(state, value);
+ //remove_tlb_by_asid(RD, DATA_TLB);
+ //erase_by_asid(core, RD, DATA_TLB);
+ //DEBUG_LOG(ARM11, "{TLB} [DATA] invalidate by asid\n");
+ break;
+ default:
+ break;
+ }
+ break;
+ case 7: /* UNIFILED TLB */
+ switch(OPCODE_2){
+ case 0: /* invalidate all */
+ //invalidate_all_tlb(state);
+ //erase_all(core, INSN_TLB);
+ //erase_all(core, DATA_TLB);
+ //remove_tlb(DATA_TLB);
+ //remove_tlb(INSN_TLB);
+ //DEBUG_LOG(ARM11, "{TLB} [UNIFILED] invalidate all\n");
+ break;
+ case 1: /* invalidate by MVA */
+ //invalidate_by_mva(state, value);
+ //erase_by_mva(core, RD, DATA_TLB);
+ //erase_by_mva(core, RD, INSN_TLB);
+ DEBUG_LOG(ARM11, "{TLB} [UNIFILED] invalidate by mva\n");
+ break;
+ case 2: /* invalidate by asid */
+ //invalidate_by_asid(state, value);
+ //erase_by_asid(core, RD, DATA_TLB);
+ //erase_by_asid(core, RD, INSN_TLB);
+ DEBUG_LOG(ARM11, "{TLB} [UNIFILED] invalidate by asid\n");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ } else if(CRn == MMU_PID){
+ if(OPCODE_2 == 0)
+ CP15_REG(CP15_PID) = RD;
+ else if(OPCODE_2 == 1)
+ CP15_REG(CP15_CONTEXT_ID) = RD;
+ else if(OPCODE_2 == 3){
+ CP15_REG(CP15_THREAD_URO) = RD;
+ }
+ else{
+ printf ("mmu_mcr wrote UNKNOWN - reg %d\n", CRn);
+ }
+
+ } else {
+ DEBUG_LOG(ARM11, "mcr is not implementated. CRn is %d, CRm is %d, OPCODE_2 is %d\n", CRn, CRm, OPCODE_2);
+ }
+ }
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mcr_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MCRR_INST:
+ MLA_INST:
+ {
+ INC_ICOUNTER;
+ mla_inst *inst_cream = (mla_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ uint64_t rm = RM;
+ uint64_t rs = RS;
+ uint64_t rn = RN;
+ if (inst_cream->Rm == 15 || inst_cream->Rs == 15 || inst_cream->Rn == 15) {
+ DEBUG_LOG(ARM11, "in __line__\n", __LINE__);
+ CITRA_IGNORE_EXIT(-1);
+ }
+// RD = dst = RM * RS + RN;
+ RD = dst = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
+ if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(mla_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mla_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MOV_INST:
+ {
+// DEBUG_LOG(ARM11, "mov inst\n");
+// DEBUG_LOG(ARM11, "pc: %x\n", cpu->Reg[15]);
+// debug_function(cpu);
+// cpu->icount ++;
+ INC_ICOUNTER;
+ mov_inst *inst_cream = (mov_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ RD = dst = SHIFTER_OPERAND;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(mov_inst));
+ goto PROFILING;
+ }
+// return;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mov_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MRC_INST:
+ {
+ INC_ICOUNTER;
+ /* NOT IMPL */
+ mrc_inst *inst_cream = (mrc_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int inst = inst_cream->inst;
+ if (inst_cream->Rd == 15) {
+ DEBUG_MSG;
+ }
+ if (inst_cream->inst == 0xeef04a10) {
+ /* undefined instruction fmrx */
+ RD = 0x20000000;
+ CITRA_IGNORE_EXIT(-1);
+ goto END;
+ } else {
+ if (inst_cream->cp_num == 15) {
+ if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
+ //LET(RD, CONST(0x0007b000));
+ //LET(RD, CONST(0x410FB760));
+ //LET(RD, R(CP15_MAIN_ID));
+ RD = cpu->CP15[CP15(CP15_MAIN_ID)];
+ } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(RD, R(CP15_CONTROL));
+ RD = cpu->CP15[CP15(CP15_CONTROL)];
+ } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
+ //LET(RD, R(CP15_CONTROL));
+ RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
+ } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
+ //LET(RD, R(CP15_CONTROL));
+ RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
+ } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(RD, R(CP15_DOMAIN_ACCESS_CONTROL));
+ RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
+ } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(RD, R(CP15_TRANSLATION_BASE_TABLE_0));
+ RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
+ } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(RD, R(CP15_FAULT_STATUS));
+ RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
+ } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
+ //LET(RD, R(CP15_FAULT_ADDRESS));
+ RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
+ } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
+ //LET(RD, R(CP15_CACHE_TYPE));
+ RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
+ } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
+ //LET(RD, R(CP15_INSTR_FAULT_STATUS));
+ RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
+ } else if (CRn == 13) {
+ if(OPCODE_2 == 0)
+ RD = CP15_REG(CP15_PID);
+ else if(OPCODE_2 == 1)
+ RD = CP15_REG(CP15_CONTEXT_ID);
+ else if(OPCODE_2 == 3){
+ RD = Memory::KERNEL_MEMORY_VADDR;
+ }
+ else{
+ printf ("mmu_mrr wrote UNKNOWN - reg %d\n", CRn);
+ }
+ }
+ else {
+ DEBUG_LOG(ARM11, "mrc is not implementated. CRn is %d, CRm is %d, OPCODE_2 is %d\n", CRn, CRm, OPCODE_2);
+ }
+ }
+ //DEBUG_LOG(ARM11, "mrc is not implementated. CRn is %d, CRm is %d, OPCODE_2 is %d\n", CRn, CRm, OPCODE_2);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mrc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MRRC_INST:
+ MRS_INST:
+ {
+ INC_ICOUNTER;
+ mrs_inst *inst_cream = (mrs_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (inst_cream->R) {
+ RD = cpu->Spsr_copy;
+ } else {
+ SAVE_NZCVT;
+ RD = cpu->Cpsr;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mrs_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MSR_INST:
+ {
+ INC_ICOUNTER;
+ msr_inst *inst_cream = (msr_inst *)inst_base->component;
+ const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
+ unsigned int inst = inst_cream->inst;
+ unsigned int operand;
+
+ if (BIT(inst, 25)) {
+ int rot_imm = BITS(inst, 8, 11) * 2;
+ //operand = ROTL(CONST(BITS(0, 7)), CONST(32 - rot_imm));
+ operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm);
+ } else {
+ //operand = R(RM);
+ operand = cpu->Reg[BITS(inst, 0, 3)];
+ }
+ uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
+ | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
+ uint32_t mask;
+ if (!inst_cream->R) {
+ if (InAPrivilegedMode(cpu)) {
+ if ((operand & StateMask) != 0) {
+ /* UNPREDICTABLE */
+ DEBUG_MSG;
+ } else
+ mask = byte_mask & (UserMask | PrivMask);
+ } else {
+ mask = byte_mask & UserMask;
+ }
+ //LET(CPSR_REG, OR(AND(R(CPSR_REG), COM(CONST(mask))), AND(operand, CONST(mask))));
+ SAVE_NZCVT;
+
+ cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask);
+ switch_mode(cpu, cpu->Cpsr & 0x1f);
+ LOAD_NZCVT;
+ } else {
+ if (CurrentModeHasSPSR) {
+ mask = byte_mask & (UserMask | PrivMask | StateMask);
+ //LET(SPSR_REG, OR(AND(R(SPSR_REG), COM(CONST(mask))), AND(operand, CONST(mask))));
+ cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(msr_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MUL_INST:
+ {
+ INC_ICOUNTER;
+ mul_inst *inst_cream = (mul_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+// RD = dst = SHIFTER_OPERAND;
+ uint64_t rm = RM;
+ uint64_t rs = RS;
+ RD = dst = static_cast<uint32_t>((rm * rs) & 0xffffffff);
+ if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(mul_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mul_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ MVN_INST:
+ {
+ INC_ICOUNTER;
+ mvn_inst *inst_cream = (mvn_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+// RD = dst = (SHIFTER_OPERAND ^ 0xffffffff);
+ RD = dst = ~SHIFTER_OPERAND;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(mvn_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(mvn_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ ORR_INST:
+ {
+ INC_ICOUNTER;
+ orr_inst *inst_cream = (orr_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ rop = SHIFTER_OPERAND;
+// DEBUG_LOG(ARM11, "lop is %x, rop is %x, r2 is %x, r3 is %x\n", lop, rop, cpu->Reg[2], cpu->Reg[3]);
+ RD = dst = lop | rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr*/
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+// UPDATE_CFLAG(dst, lop, rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(orr_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(orr_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ PKHBT_INST:
+ PKHTB_INST:
+ PLD_INST:
+ {
+ INC_ICOUNTER;
+ /* NOT IMPL */
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(stc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ QADD_INST:
+ QADD16_INST:
+ QADD8_INST:
+ QADDSUBX_INST:
+ QDADD_INST:
+ QDSUB_INST:
+ QSUB_INST:
+ QSUB16_INST:
+ QSUB8_INST:
+ QSUBADDX_INST:
+ REV_INST:
+ {
+ INC_ICOUNTER;
+ rev_inst *inst_cream = (rev_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ RD = ((RM & 0xff) << 24) |
+ (((RM >> 8) & 0xff) << 16) |
+ (((RM >> 16) & 0xff) << 8) |
+ ((RM >> 24) & 0xff);
+ if (inst_cream->Rm == 15) {
+ DEBUG_LOG(ARM11, "in line %d\n", __LINE__);
+ CITRA_IGNORE_EXIT(-1);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(rev_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ REV16_INST:
+ {
+ INC_ICOUNTER;
+ rev_inst *inst_cream = (rev_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ RD = (BITS(RM, 0, 7) << 8) |
+ BITS(RM, 8, 15) |
+ (BITS(RM, 16, 23) << 24) |
+ (BITS(RM, 24, 31) << 16);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(rev_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ REVSH_INST:
+ RFE_INST:
+ RSB_INST:
+ {
+ INC_ICOUNTER;
+ rsb_inst *inst_cream = (rsb_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ rop = RN;
+ lop = SHIFTER_OPERAND;
+ if (inst_cream->Rn == 15) {
+ rop += 2 * GET_INST_SIZE(cpu);;
+ }
+ RD = dst = lop - rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
+// UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(rsb_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(rsb_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ RSC_INST:
+ {
+ INC_ICOUNTER;
+ rsc_inst *inst_cream = (rsc_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ //lop = RN + !cpu->CFlag;
+ //rop = SHIFTER_OPERAND;
+ //RD = dst = rop - lop;
+ lop = RN;
+ rop = SHIFTER_OPERAND;
+ RD = dst = rop - lop - !cpu->CFlag;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+// UPDATE_CFLAG(dst, lop, rop);
+// UPDATE_CFLAG_NOT_BORROW_FROM(rop, lop);
+ UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(rop, lop, !cpu->CFlag);
+// cpu->CFlag = !((ISNEG(lop) && ISPOS(rop)) || (ISNEG(lop) && ISPOS(dst)) || (ISPOS(rop) && ISPOS(dst)));
+ UPDATE_VFLAG_OVERFLOW_FROM((int)dst, (int)rop, (int)lop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(rsc_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(rsc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SADD16_INST:
+ SADD8_INST:
+ SADDSUBX_INST:
+ SBC_INST:
+ {
+ INC_ICOUNTER;
+ sbc_inst *inst_cream = (sbc_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = SHIFTER_OPERAND + !cpu->CFlag;
+ rop = RN;
+ RD = dst = rop - lop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+// UPDATE_CFLAG(dst, lop, rop);
+ //UPDATE_CFLAG_NOT_BORROW_FROM(rop, lop);
+ //rop = rop - !cpu->CFlag;
+ if(rop >= !cpu->CFlag)
+ UPDATE_CFLAG_NOT_BORROW_FROM(rop - !cpu->CFlag, SHIFTER_OPERAND);
+ else
+ UPDATE_CFLAG_NOT_BORROW_FROM(rop, !cpu->CFlag);
+// cpu->CFlag = !((ISNEG(lop) && ISPOS(rop)) || (ISNEG(lop) && ISPOS(dst)) || (ISPOS(rop) && ISPOS(dst)));
+ UPDATE_VFLAG_OVERFLOW_FROM(dst, rop, lop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(sbc_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(sbc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SEL_INST:
+ SETEND_INST:
+ SHADD16_INST:
+ SHADD8_INST:
+ SHADDSUBX_INST:
+ SHSUB16_INST:
+ SHSUB8_INST:
+ SHSUBADDX_INST:
+ SMLA_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ smla_inst *inst_cream = (smla_inst *)inst_base->component;
+ int32_t operand1, operand2;
+ if (inst_cream->x == 0)
+ operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
+ else
+ operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
+
+ if (inst_cream->y == 0)
+ operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
+ else
+ operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
+ RD = operand1 * operand2 + RN;
+ //FIXME: UPDATE Q FLAGS
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(smla_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SMLAD_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
+ long long int rm = cpu->Reg[inst_cream->Rm];
+ long long int rn = cpu->Reg[inst_cream->Rn];
+ long long int ra = cpu->Reg[inst_cream->Ra];
+ /* see SMUAD */
+ if(inst_cream->Ra == 15)
+ CITRA_IGNORE_EXIT(-1);
+ int operand2 = (inst_cream->m)? ROTATE_RIGHT_32(rm, 16):rm;
+
+ int half_rn, half_operand2;
+ half_rn = rn & 0xFFFF;
+ half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn;
+
+ half_operand2 = operand2 & 0xFFFF;
+ half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2;
+
+ long long int product1 = half_rn * half_operand2;
+
+ half_rn = (rn & 0xFFFF0000) >> 16;
+ half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn;
+
+ half_operand2 = (operand2 & 0xFFFF0000) >> 16;
+ half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2;
+
+ long long int product2 = half_rn * half_operand2;
+
+ long long int signed_ra = (ra & 0x80000000)? (0xFFFFFFFF00000000LL) | ra : ra;
+ long long int result = product1 + product2 + signed_ra;
+ cpu->Reg[inst_cream->Rd] = result & 0xFFFFFFFF;
+ /* FIXME , should check Signed overflow */
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(umlal_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
+ SMLAL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
+ long long int rm = RM;
+ long long int rs = RS;
+ if (BIT(rm, 31)) {
+ rm |= 0xffffffff00000000LL;
+ }
+ if (BIT(rs, 31)) {
+ rs |= 0xffffffff00000000LL;
+ }
+ long long int rst = rm * rs;
+ long long int rdhi32 = RDHI;
+ long long int hilo = (rdhi32 << 32) + RDLO;
+ rst += hilo;
+ RDLO = BITS(rst, 0, 31);
+ RDHI = BITS(rst, 32, 63);
+ if (inst_cream->S) {
+ cpu->NFlag = BIT(RDHI, 31);
+ cpu->ZFlag = (RDHI == 0 && RDLO == 0);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(umlal_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SMLALXY_INST:
+ SMLALD_INST:
+ SMLAW_INST:
+ SMLSD_INST:
+ SMLSLD_INST:
+ SMMLA_INST:
+ SMMLS_INST:
+ SMMUL_INST:
+ SMUAD_INST:
+ SMUL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ smul_inst *inst_cream = (smul_inst *)inst_base->component;
+ uint32_t operand1, operand2;
+ if (inst_cream->x == 0)
+ operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
+ else
+ operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
+
+ if (inst_cream->y == 0)
+ operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
+ else
+ operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
+ RD = operand1 * operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(smul_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SMULL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ umull_inst *inst_cream = (umull_inst *)inst_base->component;
+// DEBUG_LOG(ARM11, "rm : [%llx] rs : [%llx] rst [%llx]\n", RM, RS, rst);
+ int64_t rm = RM;
+ int64_t rs = RS;
+ if (BIT(rm, 31)) {
+ rm |= 0xffffffff00000000LL;
+ }
+ if (BIT(rs, 31)) {
+ rs |= 0xffffffff00000000LL;
+ }
+ int64_t rst = rm * rs;
+ RDHI = BITS(rst, 32, 63);
+ RDLO = BITS(rst, 0, 31);
+
+
+ if (inst_cream->S) {
+ cpu->NFlag = BIT(RDHI, 31);
+ cpu->ZFlag = (RDHI == 0 && RDLO == 0);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(umull_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SMULW_INST:
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
+// DEBUG_LOG(ARM11, "rm : [%llx] rs : [%llx] rst [%llx]\n", RM, RS, rst);
+ int64_t rm = RM;
+ int64_t rn = RN;
+ if (inst_cream->m)
+ rm = BITS(rm,16 , 31);
+ else
+ rm = BITS(rm,0 , 15);
+ int64_t rst = rm * rn;
+ RD = BITS(rst, 16, 47);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(smlad_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+
+ SMUSD_INST:
+ SRS_INST:
+ SSAT_INST:
+ SSAT16_INST:
+ SSUB16_INST:
+ SSUB8_INST:
+ SSUBADDX_INST:
+ STC_INST:
+ {
+ INC_ICOUNTER;
+ /* NOT IMPL */
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(stc_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STM_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ unsigned int inst = inst_cream->inst;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ int i;
+ unsigned int Rn = BITS(inst, 16, 19);
+ unsigned int old_RN = cpu->Reg[Rn];
+
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ if (BIT(inst_cream->inst, 22) == 1) {
+// DEBUG_MSG;
+ #if 1
+ for (i = 0; i < 13; i++) {
+ if(BIT(inst_cream->inst, i)){
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ }
+ }
+ if (BIT(inst_cream->inst, 13)) {
+ if (cpu->Mode == USER32MODE) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ } else {
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg_usr[0], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ }
+ }
+ if (BIT(inst_cream->inst, 14)) {
+ if (cpu->Mode == USER32MODE) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ } else {
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg_usr[1], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ }
+ }
+ if (BIT(inst_cream->inst, 15)) {
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i] + 8, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ #endif
+ } else {
+ for( i = 0; i < 15; i ++ ){
+ if(BIT(inst_cream->inst, i)){
+ //arch_write_memory(cpu, bb, Addr, R(i), 32);
+ //bus_write(32, addr, cpu->Reg[i]);
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ if(i == Rn)
+ fault = interpreter_write_memory(addr, phys_addr, old_RN, 32);
+ else
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
+ if (fault) goto MMU_EXCEPTION;
+ addr += 4;
+ phys_addr += 4;
+ //Addr = ADD(Addr, CONST(4));
+ }
+ }
+
+ /* check pc reg*/
+ if(BIT(inst_cream->inst, i)){
+ //arch_write_memory(cpu, bb, Addr, STOREM_CHECK_PC, 32);
+ //bus_write(32, addr, cpu->Reg[i] + 8);
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) {
+ goto MMU_EXCEPTION;
+ }
+ fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i] + 8, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SXTB_INST:
+ {
+ INC_ICOUNTER;
+ sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (inst_cream->Rm == 15) {
+ DEBUG_LOG(ARM11, "line is %d\n", __LINE__);
+ CITRA_IGNORE_EXIT(-1);
+ }
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
+ if (BIT(operand2, 7)) {
+ operand2 |= 0xffffff00;
+ } else
+ operand2 &= 0xff;
+ RD = operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(sxtb_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STR_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
+ //bus_write(32, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UXTB_INST:
+ {
+ INC_ICOUNTER;
+ uxtb_inst *inst_cream = (uxtb_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
+ & 0xff;
+ RD = operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(uxtb_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UXTAB_INST:
+ {
+ INC_ICOUNTER;
+ uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
+ & 0xff;
+ RD = RN + operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(uxtab_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STRB_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
+ //bus_write(8, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STRBT_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
+ //bus_write(8, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ //if (BITS(inst_cream->inst, 12, 15) == 15)
+ // goto PROFILING;
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STRD_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ uint32_t rear_phys_addr;
+ fault = check_address_validity(cpu, addr + 4, &rear_phys_addr, 0);
+ if (fault){
+ ERROR_LOG(ARM11, "mmu fault , should rollback the above get_addr\n");
+ CITRA_IGNORE_EXIT(-1);
+ goto MMU_EXCEPTION;
+ }
+
+ //fault = inst_cream->get_addr(cpu, inst_cream->inst, addr + 4, phys_addr + 4, 0);
+ //if (fault) goto MMU_EXCEPTION;
+
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
+ //bus_write(32, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ value = cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1];
+ //bus_write(32, addr, value);
+ fault = interpreter_write_memory(addr + 4, rear_phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STREX_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)];
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+
+ int dest_reg = BITS(inst_cream->inst, 12, 15);
+ if((exclusive_detect(cpu, phys_addr) == 0) && (cpu->exclusive_state == 1)){
+ remove_exclusive(cpu, phys_addr);
+ cpu->Reg[dest_reg] = 0;
+ cpu->exclusive_state = 0;
+
+ // bus_write(32, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ else{
+ /* Failed to write due to mutex access */
+ cpu->Reg[dest_reg] = 1;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STREXB_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)] & 0xff;
+ fault = check_address_validity(cpu, addr, &phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ //bus_write(8, addr, value);
+ int dest_reg = BITS(inst_cream->inst, 12, 15);
+ if((exclusive_detect(cpu, phys_addr) == 0) && (cpu->exclusive_state == 1)){
+ remove_exclusive(cpu, phys_addr);
+ cpu->Reg[dest_reg] = 0;
+ cpu->exclusive_state = 0;
+ fault = interpreter_write_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+
+ }
+ else{
+ cpu->Reg[dest_reg] = 1;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STRH_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
+ //bus_write(16, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 16);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ //if (BITS(inst_cream->inst, 12, 15) == 15)
+ // goto PROFILING;
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ STRT_INST:
+ {
+ INC_ICOUNTER;
+ ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
+ //bus_write(16, addr, value);
+ fault = interpreter_write_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SUB_INST:
+ {
+ INC_ICOUNTER;
+ sub_inst *inst_cream = (sub_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ lop = RN;
+ if (inst_cream->Rn == 15) {
+ lop += 8;
+ }
+ rop = SHIFTER_OPERAND;
+ RD = dst = lop - rop;
+ if (inst_cream->S && (inst_cream->Rd == 15)) {
+ /* cpsr = spsr */
+ if (CurrentModeHasSPSR) {
+ cpu->Cpsr = cpu->Spsr_copy;
+ switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+ LOAD_NZCVT;
+ }
+ } else if (inst_cream->S) {
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+// UPDATE_CFLAG(dst, lop, rop);
+ UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop);
+ // UPDATE_VFLAG((int)dst, (int)lop, (int)rop);
+ UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop);
+ }
+ if (inst_cream->Rd == 15) {
+ INC_PC(sizeof(sub_inst));
+ goto PROFILING;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(sub_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SWI_INST:
+ {
+ INC_ICOUNTER;
+ swi_inst *inst_cream = (swi_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (true){ //if (core->is_user_mode) { --> Citra only emulates user mode
+ //arm_dyncom_SWI(cpu, inst_cream->num);
+ HLE::CallSVC(Memory::Read32(cpu->Reg[15]));
+ } else {
+ cpu->syscallSig = 1;
+ goto END;
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(swi_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SWP_INST:
+ {
+ INC_ICOUNTER;
+ swp_inst *inst_cream = (swp_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = RN;
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 32);
+ if (fault) goto MMU_EXCEPTION;
+ fault = interpreter_write_memory(addr, phys_addr, RM, 32);
+ if (fault) goto MMU_EXCEPTION;
+
+ /* ROR(data, 8*UInt(address<1:0>)); */
+ assert((phys_addr & 0x3) == 0);
+ RD = value;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(swp_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SWPB_INST:
+ {
+ INC_ICOUNTER;
+ swp_inst *inst_cream = (swp_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ addr = RN;
+ fault = check_address_validity(cpu, addr, &phys_addr, 1);
+ if (fault) goto MMU_EXCEPTION;
+ unsigned int value;
+ fault = interpreter_read_memory(addr, phys_addr, value, 8);
+ if (fault) goto MMU_EXCEPTION;
+ fault = interpreter_write_memory(addr, phys_addr, (RM & 0xFF), 8);
+ if (fault) goto MMU_EXCEPTION;
+
+ /* FIXME */
+ #if 0
+ if Shared(address) then
+ /* ARMv6 */
+ physical_address = TLB(address)
+ ClearExclusiveByAddress(physical_address,processor_id,1)
+ /* See Summary of operation on page A2-49 */
+ #endif
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(swp_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SXTAB_INST:
+ {
+ INC_ICOUNTER;
+ sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ /* R15 should be check */
+ if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15){
+ CITRA_IGNORE_EXIT(-1);
+ }
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
+ & 0xff;
+ /* sign extend for byte */
+ operand2 = (0x80 & operand2)? (0xFFFFFF00 | operand2):operand2;
+ RD = RN + operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(uxtab_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SXTAB16_INST:
+ SXTAH_INST:
+ {
+ INC_ICOUNTER;
+ sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ /* R15 should be check */
+ if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15){
+ CITRA_IGNORE_EXIT(-1);
+ }
+ unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
+ /* sign extend for half */
+ operand2 = (0x8000 & operand2)? (0xFFFF0000 | operand2):operand2;
+ RD = RN + operand2;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(sxtah_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ SXTB16_INST:
+ TEQ_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ teq_inst *inst_cream = (teq_inst *)inst_base->component;
+ lop = RN;
+ if (inst_cream->Rn == 15)
+ lop += GET_INST_SIZE(cpu) * 2;
+
+ rop = SHIFTER_OPERAND;
+ dst = lop ^ rop;
+
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(teq_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ TST_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ tst_inst *inst_cream = (tst_inst *)inst_base->component;
+ lop = RN;
+ if (inst_cream->Rn == 15)
+ lop += GET_INST_SIZE(cpu) * 2;
+ rop = SHIFTER_OPERAND;
+ dst = lop & rop;
+
+ UPDATE_NFLAG(dst);
+ UPDATE_ZFLAG(dst);
+ UPDATE_CFLAG_WITH_SC;
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(tst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UADD16_INST:
+ UADD8_INST:
+ UADDSUBX_INST:
+ UHADD16_INST:
+ UHADD8_INST:
+ UHADDSUBX_INST:
+ UHSUB16_INST:
+ UHSUB8_INST:
+ UHSUBADDX_INST:
+ UMAAL_INST:
+ UMLAL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
+ unsigned long long int rm = RM;
+ unsigned long long int rs = RS;
+ unsigned long long int rst = rm * rs;
+ unsigned long long int add = ((unsigned long long) RDHI)<<32;
+ add += RDLO;
+ //DEBUG_LOG(ARM11, "rm[%llx] * rs[%llx] = rst[%llx] | add[%llx]\n", RM, RS, rst, add);
+ rst += add;
+ RDLO = BITS(rst, 0, 31);
+ RDHI = BITS(rst, 32, 63);
+
+ if (inst_cream->S)
+ {
+ cpu->NFlag = BIT(RDHI, 31);
+ cpu->ZFlag = (RDHI == 0 && RDLO == 0);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(umlal_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ UMULL_INST:
+ {
+ INC_ICOUNTER;
+ if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ umull_inst *inst_cream = (umull_inst *)inst_base->component;
+ unsigned long long int rm = RM;
+ unsigned long long int rs = RS;
+ unsigned long long int rst = rm * rs;
+// DEBUG_LOG(ARM11, "rm : [%llx] rs : [%llx] rst [%llx]\n", RM, RS, rst);
+ RDHI = BITS(rst, 32, 63);
+ RDLO = BITS(rst, 0, 31);
+
+ if (inst_cream->S) {
+ cpu->NFlag = BIT(RDHI, 31);
+ cpu->ZFlag = (RDHI == 0 && RDLO == 0);
+ }
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(umull_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+ B_2_THUMB:
+ {
+ INC_ICOUNTER;
+ b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component;
+ cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm;
+ //DEBUG_LOG(ARM11, " BL_1_THUMB: imm=0x%x, r14=0x%x, r15=0x%x\n", inst_cream->imm, cpu->Reg[14], cpu->Reg[15]);
+ INC_PC(sizeof(b_2_thumb));
+ goto PROFILING;
+ }
+ B_COND_THUMB:
+ {
+ INC_ICOUNTER;
+ b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component;
+ if(CondPassed(cpu, inst_cream->cond))
+ cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm;
+ else
+ cpu->Reg[15] += 2;
+ //DEBUG_LOG(ARM11, " B_COND_THUMB: imm=0x%x, r15=0x%x\n", inst_cream->imm, cpu->Reg[15]);
+ INC_PC(sizeof(b_cond_thumb));
+ goto PROFILING;
+ }
+ BL_1_THUMB:
+ {
+ INC_ICOUNTER;
+ bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component;
+ cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm;
+ //cpu->Reg[15] += 2;
+ //DEBUG_LOG(ARM11, " BL_1_THUMB: imm=0x%x, r14=0x%x, r15=0x%x\n", inst_cream->imm, cpu->Reg[14], cpu->Reg[15]);
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(bl_1_thumb));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+
+ }
+ BL_2_THUMB:
+ {
+ INC_ICOUNTER;
+ bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component;
+ int tmp = ((cpu->Reg[15] + 2) | 1);
+ cpu->Reg[15] =
+ (cpu->Reg[14] + inst_cream->imm);
+ cpu->Reg[14] = tmp;
+ //DEBUG_LOG(ARM11, " BL_2_THUMB: imm=0x%x, r14=0x%x, r15=0x%x\n", inst_cream->imm, cpu->Reg[14], cpu->Reg[15]);
+ INC_PC(sizeof(bl_2_thumb));
+ goto PROFILING;
+ }
+ BLX_1_THUMB:
+ {
+ /* BLX 1 for armv5t and above */
+ INC_ICOUNTER;
+ uint32 tmp = cpu->Reg[15];
+ blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component;
+ cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC;
+ //DEBUG_LOG(ARM11, "In BLX_1_THUMB, BLX(1),imm=0x%x,r14=0x%x, instr=0x%x\n", inst_cream->imm, cpu->Reg[14], inst_cream->instr);
+ cpu->Reg[14] = ((tmp + 2) | 1);
+ //(state->Reg[14] + ((tinstr & 0x07FF) << 1)) & 0xFFFFFFFC;
+ /* switch to arm state from thumb state */
+ cpu->TFlag = 0;
+ //DEBUG_LOG(ARM11, "In BLX_1_THUMB, BLX(1),imm=0x%x,r14=0x%x, r15=0x%x, \n", inst_cream->imm, cpu->Reg[14], cpu->Reg[15]);
+ INC_PC(sizeof(blx_1_thumb));
+ goto PROFILING;
+ }
+
+ UQADD16_INST:
+ UQADD8_INST:
+ UQADDSUBX_INST:
+ UQSUB16_INST:
+ UQSUB8_INST:
+ UQSUBADDX_INST:
+ USAD8_INST:
+ USADA8_INST:
+ USAT_INST:
+ USAT16_INST:
+ USUB16_INST:
+ USUB8_INST:
+ USUBADDX_INST:
+ UXTAB16_INST:
+ UXTB16_INST:
+ #define VFP_INTERPRETER_IMPL
+ #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
+ #undef VFP_INTERPRETER_IMPL
+ MMU_EXCEPTION:
+ {
+ SAVE_NZCVT;
+ cpu->abortSig = true;
+ cpu->Aborted = ARMul_DataAbortV;
+ cpu->AbortAddr = addr;
+ cpu->CP15[CP15(CP15_FAULT_STATUS)] = fault & 0xff;
+ cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = addr;
+ return;
+ }
+ END:
+ {
+ SAVE_NZCVT;
+ return;
+ }
+ INIT_INST_LENGTH:
+ {
+#if 0
+ DEBUG_LOG(ARM11, "InstLabel:%d\n", sizeof(InstLabel));
+ for (int i = 0; i < (sizeof(InstLabel) / sizeof(void *)); i ++)
+ DEBUG_LOG(ARM11, "[%llx]\n", InstLabel[i]);
+ DEBUG_LOG(ARM11, "InstLabel:%d\n", sizeof(InstLabel));
+#endif
+#ifdef __GNUC__
+ InterpreterInitInstLength((unsigned long long int *)InstLabel, sizeof(InstLabel));
+#endif
+#if 0
+ for (int i = 0; i < (sizeof(InstLabel) / sizeof(void *)); i ++)
+ DEBUG_LOG(ARM11, "[%llx]\n", InstLabel[i]);
+ DEBUG_LOG(ARM11, "%llx\n", InstEndLabel[1]);
+ DEBUG_LOG(ARM11, "%llx\n", InstLabel[1]);
+ DEBUG_LOG(ARM11, "%lld\n", (char *)InstEndLabel[1] - (char *)InstLabel[1]);
+#endif
+ return;
+ }
+}
+
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.h b/src/core/arm/dyncom/arm_dyncom_interpreter.h
new file mode 100644
index 0000000000..d73f8f65f9
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.h
@@ -0,0 +1,7 @@
+// Copyright 2014 Citra Emulator Project
+// Licensed under GPLv2
+// Refer to the license.txt file included.
+
+#pragma once
+
+void InterpreterMainLoop(ARMul_State* state);
diff --git a/src/core/arm/dyncom/arm_dyncom_run.cpp b/src/core/arm/dyncom/arm_dyncom_run.cpp
new file mode 100644
index 0000000000..a2026cbf31
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_run.cpp
@@ -0,0 +1,120 @@
+/* Copyright (C)
+* 2011 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+/**
+* @file arm_dyncom_run.cpp
+* @brief The dyncom run implementation for arm
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 78.77
+* @date 2011-11-20
+*/
+
+#include <assert.h>
+
+#include "core/arm/skyeye_common/armdefs.h"
+
+void switch_mode(arm_core_t *core, uint32_t mode)
+{
+ uint32_t tmp1, tmp2;
+ if (core->Mode == mode) {
+ //Mode not changed.
+ //printf("mode not changed\n");
+ return;
+ }
+ //printf("%d --->>> %d\n", core->Mode, mode);
+ //printf("In %s, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
+ if (mode != USERBANK) {
+ switch (core->Mode) {
+ case USER32MODE:
+ core->Reg_usr[0] = core->Reg[13];
+ core->Reg_usr[1] = core->Reg[14];
+ break;
+ case IRQ32MODE:
+ core->Reg_irq[0] = core->Reg[13];
+ core->Reg_irq[1] = core->Reg[14];
+ core->Spsr[IRQBANK] = core->Spsr_copy;
+ break;
+ case SVC32MODE:
+ core->Reg_svc[0] = core->Reg[13];
+ core->Reg_svc[1] = core->Reg[14];
+ core->Spsr[SVCBANK] = core->Spsr_copy;
+ break;
+ case ABORT32MODE:
+ core->Reg_abort[0] = core->Reg[13];
+ core->Reg_abort[1] = core->Reg[14];
+ core->Spsr[ABORTBANK] = core->Spsr_copy;
+ break;
+ case UNDEF32MODE:
+ core->Reg_undef[0] = core->Reg[13];
+ core->Reg_undef[1] = core->Reg[14];
+ core->Spsr[UNDEFBANK] = core->Spsr_copy;
+ break;
+ case FIQ32MODE:
+ core->Reg_firq[0] = core->Reg[13];
+ core->Reg_firq[1] = core->Reg[14];
+ core->Spsr[FIQBANK] = core->Spsr_copy;
+ break;
+
+ }
+
+ switch (mode) {
+ case USER32MODE:
+ core->Reg[13] = core->Reg_usr[0];
+ core->Reg[14] = core->Reg_usr[1];
+ core->Bank = USERBANK;
+ break;
+ case IRQ32MODE:
+ core->Reg[13] = core->Reg_irq[0];
+ core->Reg[14] = core->Reg_irq[1];
+ core->Spsr_copy = core->Spsr[IRQBANK];
+ core->Bank = IRQBANK;
+ break;
+ case SVC32MODE:
+ core->Reg[13] = core->Reg_svc[0];
+ core->Reg[14] = core->Reg_svc[1];
+ core->Spsr_copy = core->Spsr[SVCBANK];
+ core->Bank = SVCBANK;
+ break;
+ case ABORT32MODE:
+ core->Reg[13] = core->Reg_abort[0];
+ core->Reg[14] = core->Reg_abort[1];
+ core->Spsr_copy = core->Spsr[ABORTBANK];
+ core->Bank = ABORTBANK;
+ break;
+ case UNDEF32MODE:
+ core->Reg[13] = core->Reg_undef[0];
+ core->Reg[14] = core->Reg_undef[1];
+ core->Spsr_copy = core->Spsr[UNDEFBANK];
+ core->Bank = UNDEFBANK;
+ break;
+ case FIQ32MODE:
+ core->Reg[13] = core->Reg_firq[0];
+ core->Reg[14] = core->Reg_firq[1];
+ core->Spsr_copy = core->Spsr[FIQBANK];
+ core->Bank = FIQBANK;
+ break;
+
+ }
+ core->Mode = mode;
+ //printf("In %si end, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
+ //printf("\n--------------------------------------\n");
+ }
+ else {
+ printf("user mode\n");
+ exit(-2);
+ }
+}
diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h
new file mode 100644
index 0000000000..aeabeac16d
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_run.h
@@ -0,0 +1,55 @@
+/* Copyright (C)
+* 2011 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+
+#ifndef __ARM_DYNCOM_RUN__
+#define __ARM_DYNCOM_RUN__
+
+#include "core/arm/skyeye_common/skyeye_types.h"
+
+void switch_mode(arm_core_t *core, uint32_t mode);
+
+/* FIXME, we temporarily think thumb instruction is always 16 bit */
+static inline uint32 GET_INST_SIZE(arm_core_t* core){
+ return core->TFlag? 2 : 4;
+}
+
+/**
+* @brief Read R15 and forced R15 to wold align, used address calculation
+*
+* @param core
+* @param Rn
+*
+* @return
+*/
+static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn){
+ return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
+}
+
+/**
+* @brief Read R15, used to data processing with pc
+*
+* @param core
+* @param Rn
+*
+* @return
+*/
+static inline uint32 CHECK_READ_REG15(arm_core_t* core, int Rn){
+ return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
+}
+
+#endif
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
new file mode 100644
index 0000000000..e10f2f9ee3
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -0,0 +1,521 @@
+/* Copyright (C)
+* 2011 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+/**
+* @file arm_dyncom_thumb.c
+* @brief The thumb dynamic interpreter
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 78.77
+* @date 2011-11-07
+*/
+
+/* We can provide simple Thumb simulation by decoding the Thumb
+instruction into its corresponding ARM instruction, and using the
+existing ARM simulator. */
+
+#include "core/arm/skyeye_common/skyeye_defs.h"
+
+#ifndef MODET /* required for the Thumb instruction support */
+#if 1
+#error "MODET needs to be defined for the Thumb world to work"
+#else
+#define MODET (1)
+#endif
+#endif
+
+#include "core/arm/skyeye_common/armos.h"
+#include "core/arm/dyncom/arm_dyncom_thumb.h"
+
+/* Decode a 16bit Thumb instruction. The instruction is in the low
+ 16-bits of the tinstr field, with the following Thumb instruction
+ held in the high 16-bits. Passing in two Thumb instructions allows
+ easier simulation of the special dual BL instruction. */
+
+tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size)
+{
+ tdstate valid = t_uninitialized;
+ ARMword next_instr;
+ ARMword tinstr;
+ tinstr = instr;
+ /* The endian should be judge here */
+ #if 0
+ if (state->bigendSig) {
+ next_instr = tinstr & 0xFFFF;
+ tinstr >>= 16;
+ }
+ else {
+ next_instr = tinstr >> 16;
+ tinstr &= 0xFFFF;
+ }
+ #endif
+ if((addr & 0x3) != 0)
+ tinstr = instr >> 16;
+ else
+ tinstr &= 0xFFFF;
+
+ //printf("In %s, instr=0x%x, tinstr=0x%x, r15=0x%x\n", __FUNCTION__, instr, tinstr, cpu->translate_pc);
+#if 1 /* debugging to catch non updates */
+ *ainstr = 0xDEADC0DE;
+#endif
+
+ switch ((tinstr & 0xF800) >> 11) {
+ case 0: /* LSL */
+ case 1: /* LSR */
+ case 2: /* ASR */
+ /* Format 1 */
+ *ainstr = 0xE1B00000 /* base opcode */
+ | ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
+ |((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
+ |((tinstr & 0x0038) >> 3) /* Rs */
+ |((tinstr & 0x0007) << 12); /* Rd */
+ break;
+ case 3: /* ADD/SUB */
+ /* Format 2 */
+ {
+ ARMword subset[4] = {
+ 0xE0900000, /* ADDS Rd,Rs,Rn */
+ 0xE0500000, /* SUBS Rd,Rs,Rn */
+ 0xE2900000, /* ADDS Rd,Rs,#imm3 */
+ 0xE2500000 /* SUBS Rd,Rs,#imm3 */
+ };
+ /* It is quicker indexing into a table, than performing switch
+ or conditionals: */
+ *ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
+ |((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
+ |((tinstr & 0x0038) << (16 - 3)) /* Rs */
+ |((tinstr & 0x0007) << (12 - 0)); /* Rd */
+ }
+ break;
+ case 4: /* MOV */
+ case 5: /* CMP */
+ case 6: /* ADD */
+ case 7: /* SUB */
+ /* Format 3 */
+ {
+ ARMword subset[4] = {
+ 0xE3B00000, /* MOVS Rd,#imm8 */
+ 0xE3500000, /* CMP Rd,#imm8 */
+ 0xE2900000, /* ADDS Rd,Rd,#imm8 */
+ 0xE2500000, /* SUBS Rd,Rd,#imm8 */
+ };
+ *ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */
+ |((tinstr & 0x00FF) >> 0) /* imm8 */
+ |((tinstr & 0x0700) << (16 - 8)) /* Rn */
+ |((tinstr & 0x0700) << (12 - 8)); /* Rd */
+ }
+ break;
+ case 8: /* Arithmetic and high register transfers */
+ /* TODO: Since the subsets for both Format 4 and Format 5
+ instructions are made up of different ARM encodings, we could
+ save the following conditional, and just have one large
+ subset. */
+ if ((tinstr & (1 << 10)) == 0) {
+ typedef enum
+ { t_norm, t_shift, t_neg, t_mul }otype_t;
+
+ /* Format 4 */
+ struct
+ {
+ ARMword opcode;
+ otype_t otype;
+ }
+ subset[16] = {
+ {
+ 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
+ {
+ 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
+ {
+ 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
+ {
+ 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
+ {
+ 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
+ {
+ 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
+ {
+ 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
+ {
+ 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
+ {
+ 0xE1100000, t_norm}, /* TST Rd,Rs */
+ {
+ 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
+ {
+ 0xE1500000, t_norm}, /* CMP Rd,Rs */
+ {
+ 0xE1700000, t_norm}, /* CMN Rd,Rs */
+ {
+ 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
+ {
+ 0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */
+ {
+ 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
+ {
+ 0xE1F00000, t_norm} /* MVNS Rd,Rs */
+ };
+ *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
+ switch (subset[(tinstr & 0x03C0) >> 6].otype) {
+ case t_norm:
+ *ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
+ |((tinstr & 0x0007) << 12) /* Rd */
+ |((tinstr & 0x0038) >> 3); /* Rs */
+ break;
+ case t_shift:
+ *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
+ |((tinstr & 0x0007) >> 0) /* Rm */
+ |((tinstr & 0x0038) << (8 - 3)); /* Rs */
+ break;
+ case t_neg:
+ *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
+ |((tinstr & 0x0038) << (16 - 3)); /* Rn */
+ break;
+ case t_mul:
+ *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
+ |((tinstr & 0x0007) << 8) /* Rs */
+ |((tinstr & 0x0038) >> 3); /* Rm */
+ break;
+ }
+ }
+ else {
+ /* Format 5 */
+ ARMword Rd = ((tinstr & 0x0007) >> 0);
+ ARMword Rs = ((tinstr & 0x0038) >> 3);
+ if (tinstr & (1 << 7))
+ Rd += 8;
+ if (tinstr & (1 << 6))
+ Rs += 8;
+ switch ((tinstr & 0x03C0) >> 6) {
+ case 0x1: /* ADD Rd,Rd,Hs */
+ case 0x2: /* ADD Hd,Hd,Rs */
+ case 0x3: /* ADD Hd,Hd,Hs */
+ *ainstr = 0xE0800000 /* base */
+ | (Rd << 16) /* Rn */
+ |(Rd << 12) /* Rd */
+ |(Rs << 0); /* Rm */
+ break;
+ case 0x5: /* CMP Rd,Hs */
+ case 0x6: /* CMP Hd,Rs */
+ case 0x7: /* CMP Hd,Hs */
+ *ainstr = 0xE1500000 /* base */
+ | (Rd << 16) /* Rn */
+ |(Rd << 12) /* Rd */
+ |(Rs << 0); /* Rm */
+ break;
+ case 0x9: /* MOV Rd,Hs */
+ case 0xA: /* MOV Hd,Rs */
+ case 0xB: /* MOV Hd,Hs */
+ *ainstr = 0xE1A00000 /* base */
+ | (Rd << 16) /* Rn */
+ |(Rd << 12) /* Rd */
+ |(Rs << 0); /* Rm */
+ break;
+ case 0xC: /* BX Rs */
+ case 0xD: /* BX Hs */
+ *ainstr = 0xE12FFF10 /* base */
+ | ((tinstr & 0x0078) >> 3); /* Rd */
+ break;
+ case 0x0: /* UNDEFINED */
+ case 0x4: /* UNDEFINED */
+ case 0x8: /* UNDEFINED */
+ valid = t_undefined;
+ break;
+ case 0xE: /* BLX */
+ case 0xF: /* BLX */
+
+ //if (state->is_v5) {
+ if(1){
+ //valid = t_branch;
+ #if 1
+ *ainstr = 0xE1200030 /* base */
+ |(Rs << 0); /* Rm */
+ #endif
+ } else {
+ valid = t_undefined;
+ }
+ break;
+ }
+ }
+ break;
+ case 9: /* LDR Rd,[PC,#imm8] */
+ /* Format 6 */
+ *ainstr = 0xE59F0000 /* base */
+ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
+ |((tinstr & 0x00FF) << (2 - 0)); /* off8 */
+ break;
+ case 10:
+ case 11:
+ /* TODO: Format 7 and Format 8 perform the same ARM encoding, so
+ the following could be merged into a single subset, saving on
+ the following boolean: */
+ if ((tinstr & (1 << 9)) == 0) {
+ /* Format 7 */
+ ARMword subset[4] = {
+ 0xE7800000, /* STR Rd,[Rb,Ro] */
+ 0xE7C00000, /* STRB Rd,[Rb,Ro] */
+ 0xE7900000, /* LDR Rd,[Rb,Ro] */
+ 0xE7D00000 /* LDRB Rd,[Rb,Ro] */
+ };
+ *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
+ |((tinstr & 0x0007) << (12 - 0)) /* Rd */
+ |((tinstr & 0x0038) << (16 - 3)) /* Rb */
+ |((tinstr & 0x01C0) >> 6); /* Ro */
+ }
+ else {
+ /* Format 8 */
+ ARMword subset[4] = {
+ 0xE18000B0, /* STRH Rd,[Rb,Ro] */
+ 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
+ 0xE19000B0, /* LDRH Rd,[Rb,Ro] */
+ 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
+ };
+ *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
+ |((tinstr & 0x0007) << (12 - 0)) /* Rd */
+ |((tinstr & 0x0038) << (16 - 3)) /* Rb */
+ |((tinstr & 0x01C0) >> 6); /* Ro */
+ }
+ break;
+ case 12: /* STR Rd,[Rb,#imm5] */
+ case 13: /* LDR Rd,[Rb,#imm5] */
+ case 14: /* STRB Rd,[Rb,#imm5] */
+ case 15: /* LDRB Rd,[Rb,#imm5] */
+ /* Format 9 */
+ {
+ ARMword subset[4] = {
+ 0xE5800000, /* STR Rd,[Rb,#imm5] */
+ 0xE5900000, /* LDR Rd,[Rb,#imm5] */
+ 0xE5C00000, /* STRB Rd,[Rb,#imm5] */
+ 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
+ };
+ /* The offset range defends on whether we are transferring a
+ byte or word value: */
+ *ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
+ |((tinstr & 0x0007) << (12 - 0)) /* Rd */
+ |((tinstr & 0x0038) << (16 - 3)) /* Rb */
+ |((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
+ }
+ break;
+ case 16: /* STRH Rd,[Rb,#imm5] */
+ case 17: /* LDRH Rd,[Rb,#imm5] */
+ /* Format 10 */
+ *ainstr = ((tinstr & (1 << 11)) /* base */
+ ? 0xE1D000B0 /* LDRH */
+ : 0xE1C000B0) /* STRH */
+ |((tinstr & 0x0007) << (12 - 0)) /* Rd */
+ |((tinstr & 0x0038) << (16 - 3)) /* Rb */
+ |((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
+ |((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
+ break;
+ case 18: /* STR Rd,[SP,#imm8] */
+ case 19: /* LDR Rd,[SP,#imm8] */
+ /* Format 11 */
+ *ainstr = ((tinstr & (1 << 11)) /* base */
+ ? 0xE59D0000 /* LDR */
+ : 0xE58D0000) /* STR */
+ |((tinstr & 0x0700) << (12 - 8)) /* Rd */
+ |((tinstr & 0x00FF) << 2); /* off8 */
+ break;
+ case 20: /* ADD Rd,PC,#imm8 */
+ case 21: /* ADD Rd,SP,#imm8 */
+ /* Format 12 */
+ if ((tinstr & (1 << 11)) == 0) {
+ /* NOTE: The PC value used here should by word aligned */
+ /* We encode shift-left-by-2 in the rotate immediate field,
+ so no shift of off8 is needed. */
+ *ainstr = 0xE28F0F00 /* base */
+ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
+ |(tinstr & 0x00FF); /* off8 */
+ }
+ else {
+ /* We encode shift-left-by-2 in the rotate immediate field,
+ so no shift of off8 is needed. */
+ *ainstr = 0xE28D0F00 /* base */
+ | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
+ |(tinstr & 0x00FF); /* off8 */
+ }
+ break;
+ case 22:
+ case 23:
+ if ((tinstr & 0x0F00) == 0x0000) {
+ /* Format 13 */
+ /* NOTE: The instruction contains a shift left of 2
+ equivalent (implemented as ROR #30): */
+ *ainstr = ((tinstr & (1 << 7)) /* base */
+ ? 0xE24DDF00 /* SUB */
+ : 0xE28DDF00) /* ADD */
+ |(tinstr & 0x007F); /* off7 */
+ }
+ else if ((tinstr & 0x0F00) == 0x0e00)
+ *ainstr = 0xEF000000 | SWI_Breakpoint;
+ else {
+ /* Format 14 */
+ ARMword subset[4] = {
+ 0xE92D0000, /* STMDB sp!,{rlist} */
+ 0xE92D4000, /* STMDB sp!,{rlist,lr} */
+ 0xE8BD0000, /* LDMIA sp!,{rlist} */
+ 0xE8BD8000 /* LDMIA sp!,{rlist,pc} */
+ };
+ *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */
+ |(tinstr & 0x00FF); /* mask8 */
+ }
+ break;
+ case 24: /* STMIA */
+ case 25: /* LDMIA */
+ /* Format 15 */
+ *ainstr = ((tinstr & (1 << 11)) /* base */
+ ? 0xE8B00000 /* LDMIA */
+ : 0xE8A00000) /* STMIA */
+ |((tinstr & 0x0700) << (16 - 8)) /* Rb */
+ |(tinstr & 0x00FF); /* mask8 */
+ break;
+ case 26: /* Bcc */
+ case 27: /* Bcc/SWI */
+ if ((tinstr & 0x0F00) == 0x0F00) {
+ #if 0
+ if (tinstr == (ARMul_ABORTWORD & 0xffff) &&
+ state->AbortAddr == pc) {
+ *ainstr = ARMul_ABORTWORD;
+ break;
+ }
+ #endif
+ /* Format 17 : SWI */
+ *ainstr = 0xEF000000;
+ /* Breakpoint must be handled specially. */
+ if ((tinstr & 0x00FF) == 0x18)
+ *ainstr |= ((tinstr & 0x00FF) << 16);
+ /* New breakpoint value. See gdb/arm-tdep.c */
+ else if ((tinstr & 0x00FF) == 0xFE)
+ *ainstr |= SWI_Breakpoint;
+ else
+ *ainstr |= (tinstr & 0x00FF);
+ }
+ else if ((tinstr & 0x0F00) != 0x0E00) {
+ /* Format 16 */
+ #if 0
+ int doit = FALSE;
+ /* TODO: Since we are doing a switch here, we could just add
+ the SWI and undefined instruction checks into this
+ switch to same on a couple of conditionals: */
+ switch ((tinstr & 0x0F00) >> 8) {
+ case EQ:
+ doit = ZFLAG;
+ break;
+ case NE:
+ doit = !ZFLAG;
+ break;
+ case VS:
+ doit = VFLAG;
+ break;
+ case VC:
+ doit = !VFLAG;
+ break;
+ case MI:
+ doit = NFLAG;
+ break;
+ case PL:
+ doit = !NFLAG;
+ break;
+ case CS:
+ doit = CFLAG;
+ break;
+ case CC:
+ doit = !CFLAG;
+ break;
+ case HI:
+ doit = (CFLAG && !ZFLAG);
+ break;
+ case LS:
+ doit = (!CFLAG || ZFLAG);
+ break;
+ case GE:
+ doit = ((!NFLAG && !VFLAG)
+ || (NFLAG && VFLAG));
+ break;
+ case LT:
+ doit = ((NFLAG && !VFLAG)
+ || (!NFLAG && VFLAG));
+ break;
+ case GT:
+ doit = ((!NFLAG && !VFLAG && !ZFLAG)
+ || (NFLAG && VFLAG && !ZFLAG));
+ break;
+ case LE:
+ doit = ((NFLAG && !VFLAG)
+ || (!NFLAG && VFLAG)) || ZFLAG;
+ break;
+ }
+ if (doit) {
+ state->Reg[15] = (pc + 4
+ + (((tinstr & 0x7F) << 1)
+ | ((tinstr & (1 << 7)) ?
+ 0xFFFFFF00 : 0)));
+ FLUSHPIPE;
+ }
+ #endif
+ valid = t_branch;
+ }
+ else /* UNDEFINED : cc=1110(AL) uses different format */
+ valid = t_undefined;
+ break;
+ case 28: /* B */
+ /* Format 18 */
+ #if 0
+ state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1)
+ | ((tinstr & (1 << 10)) ?
+ 0xFFFFF800 : 0)));
+ #endif
+ //FLUSHPIPE;
+ valid = t_branch;
+ break;
+ case 29:
+ if(tinstr & 0x1)
+ valid = t_undefined;
+ else{
+ /* BLX 1 for armv5t and above */
+ //printf("In %s, After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x\n", __FUNCTION__, state->Reg[14], state->Reg[15], (tinstr &0x7FF) << 1);
+ valid = t_branch;
+ }
+ break;
+ case 30: /* BL instruction 1 */
+ /* Format 19 */
+ /* There is no single ARM instruction equivalent for this Thumb
+ instruction. To keep the simulation simple (from the user
+ perspective) we check if the following instruction is the
+ second half of this BL, and if it is we simulate it
+ immediately. */
+ valid = t_branch;
+ break;
+ case 31: /* BL instruction 2 */
+ /* Format 19 */
+ /* There is no single ARM instruction equivalent for this
+ instruction. Also, it should only ever be matched with the
+ fmt19 "BL instruction 1" instruction. However, we do allow
+ the simulation of it on its own, with undefined results if
+ r14 is not suitably initialised. */
+ {
+ #if 0
+ ARMword tmp = (pc + 2);
+ state->Reg[15] =
+ (state->Reg[14] + ((tinstr & 0x07FF) << 1));
+ state->Reg[14] = (tmp | 1);
+ #endif
+ valid = t_branch;
+ }
+ break;
+ }
+ *inst_size = 2;
+ return valid;
+}
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h
new file mode 100644
index 0000000000..5541de9d13
--- /dev/null
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.h
@@ -0,0 +1,51 @@
+/* Copyright (C)
+* 2011 - Michael.Kang blackfin.kang@gmail.com
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*
+*/
+
+/**
+* @file arm_dyncom_thumb.h
+* @brief The thumb dyncom
+* @author Michael.Kang blackfin.kang@gmail.com
+* @version 78.77
+* @date 2011-11-07
+*/
+
+#ifndef __ARM_DYNCOM_THUMB_H__
+#define __ARM_DYNCOM_THUMB_H__
+
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/skyeye_types.h"
+
+enum tdstate {
+ t_undefined, // Undefined Thumb instruction
+ t_decoded, // Instruction decoded to ARM equivalent
+ t_branch, // Thumb branch (already processed)
+ t_uninitialized,
+};
+
+tdstate
+thumb_translate(addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size);
+static inline uint32 get_thumb_instr(uint32 instr, addr_t pc){
+ uint32 tinstr;
+ if ((pc & 0x3) != 0)
+ tinstr = instr >> 16;
+ else
+ tinstr = instr & 0xFFFF;
+ return tinstr;
+}
+
+#endif
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 64760500ce..49ae01a0c9 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -10,7 +10,7 @@
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/armemu.h"
-class ARM_Interpreter : virtual public ARM_Interface {
+class ARM_Interpreter final : virtual public ARM_Interface {
public:
ARM_Interpreter();
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index 3d3545c654..2568b93ef4 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -15,18 +15,11 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-//#include <util.h>
-
-#include <string>
-#include "core/arm/interpreter/armdefs.h"
-#include "core/arm/interpreter/armemu.h"
-#include "core/hle/coprocessor.h"
+#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armemu.h"
#include "core/arm/disassembler/arm_disasm.h"
+#include "core/mem_map.h"
-//#include "ansidecl.h"
-//#include "skyeye.h"
-//extern int skyeye_instr_debug;
-/* Definitions for the support routines. */
static ARMword ModeToBank (ARMword);
static void EnvokeList (ARMul_State *, unsigned int, unsigned int);
@@ -751,7 +744,7 @@ ARMword ARMul_MRC (ARMul_State * state, ARMword instr)
int cpopc = BITS(21, 23) & 0x7;
if (cn == 13 && cm == 0 && cp == 3) { //c13,c0,3; returns CPU svc buffer
- ARMword result = HLE::CallMRC(instr);
+ ARMword result = Memory::KERNEL_MEMORY_VADDR;
if (result != -1) {
return result;
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
index 0ca62780b9..4dac1a8bf4 100644
--- a/src/core/arm/skyeye_common/arm_regformat.h
+++ b/src/core/arm/skyeye_common/arm_regformat.h
@@ -99,5 +99,7 @@ enum arm_regno{
MAX_REG_NUM,
};
-#define VFP_OFFSET(x) (x - VFP_BASE)
+#define CP15(idx) (idx - CP15_BASE)
+#define VFP_OFFSET(x) (x - VFP_BASE)
+
#endif
diff --git a/src/core/arm/skyeye_common/armcpu.h b/src/core/arm/skyeye_common/armcpu.h
index 6b5ea85663..3a029f0e70 100644
--- a/src/core/arm/skyeye_common/armcpu.h
+++ b/src/core/arm/skyeye_common/armcpu.h
@@ -20,16 +20,13 @@
#ifndef __ARM_CPU_H__
#define __ARM_CPU_H__
-//#include <skyeye_thread.h>
-//#include <skyeye_obj.h>
-//#include <skyeye_mach.h>
-//#include <skyeye_exec.h>
#include <stddef.h>
#include <stdio.h>
#include "common/thread.h"
+#include "core/arm/skyeye_common/armdefs.h"
typedef struct ARM_CPU_State_s {
ARMul_State * core;
diff --git a/src/core/arm/skyeye_common/armos.h b/src/core/arm/skyeye_common/armos.h
index 4b58801ad8..ffdadcd1cb 100644
--- a/src/core/arm/skyeye_common/armos.h
+++ b/src/core/arm/skyeye_common/armos.h
@@ -15,14 +15,7 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-//#include "bank_defs.h"
-//#include "dyncom/defines.h"
-
-//typedef struct mmap_area{
-// mem_bank_t bank;
-// void *mmap_addr;
-// struct mmap_area *next;
-//}mmap_area_t;
+#include <stdint.h>
#if FAST_MEMORY
/* in user mode, mmap_base will be on initial brk,
diff --git a/src/core/arm/skyeye_common/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
index b6713ebadb..d4088383f6 100644
--- a/src/core/arm/skyeye_common/skyeye_defs.h
+++ b/src/core/arm/skyeye_common/skyeye_defs.h
@@ -108,4 +108,6 @@ typedef struct generic_arch_s
align_t alignment;
} generic_arch_t;
-#endif
\ No newline at end of file
+typedef u32 addr_t;
+
+#endif
diff --git a/src/core/arm/skyeye_common/skyeye_types.h b/src/core/arm/skyeye_common/skyeye_types.h
new file mode 100644
index 0000000000..e7f022f190
--- /dev/null
+++ b/src/core/arm/skyeye_common/skyeye_types.h
@@ -0,0 +1,55 @@
+/*
+ skyeye_types.h - some data types definition for skyeye debugger
+ Copyright (C) 2003 Skyeye Develop Group
+ for help please send mail to <skyeye-developer@lists.sf.linuxforum.net>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+*/
+/*
+ * 12/16/2006 Michael.Kang <blackfin.kang@gmail.com>
+ */
+
+#ifndef __SKYEYE_TYPES_H
+#define __SKYEYE_TYPES_H
+
+#include <stdint.h>
+
+/*default machine word length */
+
+#ifndef __BEOS__
+/* To avoid the type conflict with the qemu */
+#ifndef QEMU
+typedef uint8_t uint8;
+typedef uint16_t uint16;
+typedef uint32_t uint32;
+typedef uint64_t uint64;
+
+typedef int8_t sint8;
+typedef int16_t sint16;
+typedef int32_t sint32;
+typedef int64_t sint64;
+#endif
+
+typedef uint32_t address_t;
+typedef uint32_t uinteger_t;
+typedef int32_t integer_t;
+
+typedef uint32_t physical_address_t;
+typedef uint32_t generic_address_t;
+
+#endif
+
+#endif
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index a570479114..45208fb139 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -3709,7 +3709,7 @@ VFPLABEL_INST:
{
fault = check_address_validity(cpu, addr, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d, cpu->ExtReg[inst_cream->d]);
}
@@ -3719,13 +3719,13 @@ VFPLABEL_INST:
if (fault) goto MMU_EXCEPTION;
/* Check endianness */
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d*2], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d*2], 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr + 4, phys_addr, cpu->ExtReg[inst_cream->d*2+1], 32);
+ fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[inst_cream->d*2+1], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, inst_cream->d*2+1, inst_cream->d*2, cpu->ExtReg[inst_cream->d*2+1], cpu->ExtReg[inst_cream->d*2]);
}
@@ -3926,7 +3926,7 @@ VFPLABEL_INST:
{
fault = check_address_validity(cpu, addr, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
addr += 4;
@@ -3936,12 +3936,12 @@ VFPLABEL_INST:
/* Careful of endianness, little by default */
fault = check_address_validity(cpu, addr, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
+ fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
addr += 8;
@@ -4048,7 +4048,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
{
if (single)
{
- //fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
#if 0
phys_addr = get_phys_addr(cpu, bb, Addr, 0);
bb = cpu->dyncom_engine->bb;
@@ -4166,7 +4166,7 @@ VFPLABEL_INST: /* encoding 1 */
fault = check_address_validity(cpu, addr, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
addr += 4;
@@ -4177,13 +4177,13 @@ VFPLABEL_INST: /* encoding 1 */
fault = check_address_validity(cpu, addr, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
+ fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_write_memory(core, addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
+ fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
addr += 8;
@@ -4304,7 +4304,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
if (single)
{
- //fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
/* if R(i) is R15? */
#if 0
phys_addr = get_phys_addr(cpu, bb, Addr, 0);
@@ -4321,7 +4321,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
else
{
- //fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
+ //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
#if 0
phys_addr = get_phys_addr(cpu, bb, Addr, 0);
bb = cpu->dyncom_engine->bb;
@@ -4332,7 +4332,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
bb = cpu->dyncom_engine->bb;
//if (fault) goto MMU_EXCEPTION;
- //fault = interpreter_write_memory(core, addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
+ //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
#if 0
phys_addr = get_phys_addr(cpu, bb, ADD(Addr, CONST(4)), 0);
bb = cpu->dyncom_engine->bb;
@@ -4431,7 +4431,7 @@ VFPLABEL_INST:
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, value1, 32);
+ fault = interpreter_read_memory(addr, phys_addr, value1, 32);
if (fault) goto MMU_EXCEPTION;
DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, value1, addr);
cpu->ExtReg[inst_cream->d+i] = value1;
@@ -4443,13 +4443,13 @@ VFPLABEL_INST:
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, value1, 32);
+ fault = interpreter_read_memory(addr, phys_addr, value1, 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr + 4, phys_addr, value2, 32);
+ fault = interpreter_read_memory(addr + 4, phys_addr, value2, 32);
if (fault) goto MMU_EXCEPTION;
DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, value2, value1, addr+4, addr);
cpu->ExtReg[(inst_cream->d+i)*2] = value1;
@@ -4682,7 +4682,7 @@ VFPLABEL_INST:
{
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
+ fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d, cpu->ExtReg[inst_cream->d], addr);
}
@@ -4691,12 +4691,12 @@ VFPLABEL_INST:
unsigned int word1, word2;
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, word1, 32);
+ fault = interpreter_read_memory(addr, phys_addr, word1, 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr + 4, phys_addr, word2, 32);
+ fault = interpreter_read_memory(addr + 4, phys_addr, word2, 32);
if (fault) goto MMU_EXCEPTION;
/* Check endianness */
cpu->ExtReg[inst_cream->d*2] = word1;
@@ -4923,7 +4923,7 @@ VFPLABEL_INST:
{
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, cpu->ExtReg[inst_cream->d+i], addr);
addr += 4;
@@ -4933,12 +4933,12 @@ VFPLABEL_INST:
/* Careful of endianness, little by default */
fault = check_address_validity(cpu, addr, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
+ fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
if (fault) goto MMU_EXCEPTION;
fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
if (fault) goto MMU_EXCEPTION;
- fault = interpreter_read_memory(core, addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
+ fault = interpreter_read_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
if (fault) goto MMU_EXCEPTION;
DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2], addr+4, addr);
addr += 8;
@@ -5058,7 +5058,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
if (single)
{
- //fault = interpreter_write_memory(core, addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
+ //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
/* if R(i) is R15? */
#if 0
phys_addr = get_phys_addr(cpu, bb, Addr, 1);
@@ -5095,7 +5095,7 @@ int DYNCOM_TRANS(vfpinstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc
val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
- //fault = interpreter_write_memory(core, addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
+ //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
//DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
//addr += 8;
Addr = ADD(Addr, CONST(8));
diff --git a/src/core/hle/coprocessor.h b/src/core/hle/coprocessor.h
deleted file mode 100644
index b08d6f3ee5..0000000000
--- a/src/core/hle/coprocessor.h
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright 2014 Citra Emulator Project
-// Licensed under GPLv2
-// Refer to the license.txt file included.
-
-#pragma once
-
-#include "common/common_types.h"
-
-namespace HLE {
-
-/// Coprocessor operations
-enum CoprocessorOperation {
- DATA_SYNCHRONIZATION_BARRIER = 0xE0,
- CALL_GET_THREAD_COMMAND_BUFFER = 0xE1,
-};
-
-/// Call an MRC (move to ARM register from coprocessor) instruction in HLE
-s32 CallMRC(u32 instruction);
-
-} // namespace
From 130efd461d4c0c2fdd4dc3f784dc5cadf869f2b3 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Tue, 7 Oct 2014 17:55:26 -0400
Subject: [PATCH 3/5] ARM: Updated dyncom core to use fast label lookup table
on clang.
---
src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 8739b8c14e..fe1501b59c 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3751,7 +3751,9 @@ void InterpreterMainLoop(ARMul_State* state)
inst_base = (arm_inst *)&inst_buf[ptr]
#define INC_PC(l) ptr += sizeof(arm_inst) + l
-#ifdef __GNUC__
+// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
+// clunky switch statement.
+#if defined __GNUC__ || defined __clang__
#define GOTO_NEXT_INST goto *InstLabel[inst_base->idx]
#else
#define GOTO_NEXT_INST switch(inst_base->idx) { \
@@ -3996,7 +3998,9 @@ void InterpreterMainLoop(ARMul_State* state)
//arm_processor *cpu = (arm_processor *)get_cast_conf_obj(core->cpu_data, "arm_core_t");
arm_processor *cpu = state; //(arm_processor *)(core->cpu_data->obj);
-#if __GNUC__
+ // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
+ // to a clunky switch statement.
+#if defined __GNUC__ || defined __clang__
void *InstLabel[] = {
#define VFP_INTERPRETER_LABEL
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
@@ -6543,7 +6547,7 @@ void InterpreterMainLoop(ARMul_State* state)
DEBUG_LOG(ARM11, "[%llx]\n", InstLabel[i]);
DEBUG_LOG(ARM11, "InstLabel:%d\n", sizeof(InstLabel));
#endif
-#ifdef __GNUC__
+#if defined __GNUC__ || defined __clang__
InterpreterInitInstLength((unsigned long long int *)InstLabel, sizeof(InstLabel));
#endif
#if 0
From 3c823c00287859311a4dfab7e7757c533efc46f1 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Tue, 7 Oct 2014 18:11:55 -0400
Subject: [PATCH 4/5] ARM: Removed unused armos code from SkyEye.
---
src/core/CMakeLists.txt | 1 -
src/core/arm/interpreter/armcopro.cpp | 1 -
src/core/arm/interpreter/armemu.cpp | 3 -
src/core/arm/interpreter/armos.cpp | 742 --------------------------
4 files changed, 747 deletions(-)
delete mode 100644 src/core/arm/interpreter/armos.cpp
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index 9f08277a12..cc0deb004e 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -19,7 +19,6 @@ set(SRCS
arm/interpreter/armemu.cpp
arm/interpreter/arminit.cpp
arm/interpreter/armmmu.cpp
- arm/interpreter/armos.cpp
arm/interpreter/armsupp.cpp
arm/interpreter/armvirt.cpp
arm/interpreter/thumbemu.cpp
diff --git a/src/core/arm/interpreter/armcopro.cpp b/src/core/arm/interpreter/armcopro.cpp
index ee9fa255ae..9de6651d47 100644
--- a/src/core/arm/interpreter/armcopro.cpp
+++ b/src/core/arm/interpreter/armcopro.cpp
@@ -17,7 +17,6 @@
#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/armos.h"
#include "core/arm/skyeye_common/armemu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 7ffc164294..cdcf47ee14 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -28,9 +28,6 @@
//ichfly
//#define callstacker 1
-
-//#include "armos.h"
-
//#include "skyeye_callback.h"
//#include "skyeye_bus.h"
//#include "sim_control.h"
diff --git a/src/core/arm/interpreter/armos.cpp b/src/core/arm/interpreter/armos.cpp
deleted file mode 100644
index 90eb20acc9..0000000000
--- a/src/core/arm/interpreter/armos.cpp
+++ /dev/null
@@ -1,742 +0,0 @@
-/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-/* This file contains a model of Demon, ARM Ltd's Debug Monitor,
-including all the SWI's required to support the C library. The code in
-it is not really for the faint-hearted (especially the abort handling
-code), but it is a complete example. Defining NOOS will disable all the
-fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
-0x11 to halt the emulator. */
-
-//chy 2005-09-12 disable below line
-//#include "config.h"
-
-#include <time.h>
-#include <errno.h>
-#include <string.h>
-#include "core/arm/skyeye_common/skyeye_defs.h"
-#ifndef __USE_LARGEFILE64
-#define __USE_LARGEFILE64 /* When use 64 bit large file need define it! for stat64*/
-#endif
-#include <fcntl.h>
-#include <sys/stat.h>
-
-
-#ifndef O_RDONLY
-#define O_RDONLY 0
-#endif
-#ifndef O_WRONLY
-#define O_WRONLY 1
-#endif
-#ifndef O_RDWR
-#define O_RDWR 2
-#endif
-#ifndef O_BINARY
-#define O_BINARY 0
-#endif
-
-#ifdef __STDC__
-#define unlink(s) remove(s)
-#endif
-
-#ifdef HAVE_UNISTD_H
-#include <unistd.h> /* For SEEK_SET etc */
-#endif
-
-#ifdef __riscos
-extern int _fisatty (FILE *);
-#define isatty_(f) _fisatty(f)
-#else
-#ifdef __ZTC__
-#include <io.h>
-#define isatty_(f) isatty((f)->_file)
-#else
-#ifdef macintosh
-#include <ioctl.h>
-#define isatty_(f) (~ioctl ((f)->_file, FIOINTERACTIVE, NULL))
-#else
-#define isatty_(f) isatty (fileno (f))
-#endif
-#endif
-#endif
-
-#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/armos.h"
-#include "core/arm/skyeye_common/armemu.h"
-
-#ifndef NOOS
-#ifndef VALIDATE
-/* #ifndef ASIM */
-//chy 2005-09-12 disable below line
-//#include "armfpe.h"
-/* #endif */
-#endif
-#endif
-
-#define DUMP_SYSCALL 0
-#define dump(...) do { if (DUMP_SYSCALL) printf(__VA_ARGS__); } while(0)
-//#define debug(...) printf(__VA_ARGS__);
-#define debug(...) ;
-
-extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
-
-#ifndef FOPEN_MAX
-#define FOPEN_MAX 64
-#endif
-
-/***************************************************************************\
-* OS private Information *
-\***************************************************************************/
-
-unsigned arm_dyncom_SWI(ARMul_State * state, ARMword number)
-{
- return ARMul_OSHandleSWI(state, number);
-}
-
-//mmap_area_t *mmap_global = NULL;
-
-static int translate_open_mode[] = {
- O_RDONLY, /* "r" */
- O_RDONLY + O_BINARY, /* "rb" */
- O_RDWR, /* "r+" */
- O_RDWR + O_BINARY, /* "r+b" */
- O_WRONLY + O_CREAT + O_TRUNC, /* "w" */
- O_WRONLY + O_BINARY + O_CREAT + O_TRUNC, /* "wb" */
- O_RDWR + O_CREAT + O_TRUNC, /* "w+" */
- O_RDWR + O_BINARY + O_CREAT + O_TRUNC, /* "w+b" */
- O_WRONLY + O_APPEND + O_CREAT, /* "a" */
- O_WRONLY + O_BINARY + O_APPEND + O_CREAT, /* "ab" */
- O_RDWR + O_APPEND + O_CREAT, /* "a+" */
- O_RDWR + O_BINARY + O_APPEND + O_CREAT /* "a+b" */
-};
-//
-//static void
-//SWIWrite0 (ARMul_State * state, ARMword addr)
-//{
-// ARMword temp;
-//
-// //while ((temp = ARMul_ReadByte (state, addr++)) != 0)
-// while(1){
-// mem_read(8, addr++, &temp);
-// if(temp != 0)
-// (void) fputc ((char) temp, stdout);
-// else
-// break;
-// }
-//}
-//
-//static void
-//WriteCommandLineTo (ARMul_State * state, ARMword addr)
-//{
-// ARMword temp;
-// char *cptr = state->CommandLine;
-// if (cptr == NULL)
-// cptr = "\0";
-// do {
-// temp = (ARMword) * cptr++;
-// //ARMul_WriteByte (state, addr++, temp);
-// mem_write(8, addr++, temp);
-// }
-// while (temp != 0);
-//}
-//
-//static void
-//SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
-//{
-// char dummy[2000];
-// int flags;
-// int i;
-//
-// for (i = 0; (dummy[i] = ARMul_ReadByte (state, name + i)); i++);
-// assert(SWIflags< (sizeof(translate_open_mode)/ sizeof(translate_open_mode[0])));
-// /* Now we need to decode the Demon open mode */
-// flags = translate_open_mode[SWIflags];
-// flags = SWIflags;
-//
-// /* Filename ":tt" is special: it denotes stdin/out */
-// if (strcmp (dummy, ":tt") == 0) {
-// if (flags == O_RDONLY) /* opening tty "r" */
-// state->Reg[0] = 0; /* stdin */
-// else
-// state->Reg[0] = 1; /* stdout */
-// }
-// else {
-// state->Reg[0] = (int) open (dummy, flags, 0666);
-// }
-//}
-//
-//static void
-//SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
-//{
-// int res;
-// int i;
-// char *local = (char*) malloc (len);
-//
-// if (local == NULL) {
-// fprintf (stderr,
-// "sim: Unable to read 0x%ulx bytes - out of memory\n",
-// len);
-// return;
-// }
-//
-// res = read (f, local, len);
-// if (res > 0)
-// for (i = 0; i < res; i++)
-// //ARMul_WriteByte (state, ptr + i, local[i]);
-// mem_write(8, ptr + i, local[i]);
-// free (local);
-// //state->Reg[0] = res == -1 ? -1 : len - res;
-// state->Reg[0] = res;
-//}
-//
-//static void
-//SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
-//{
-// int res;
-// ARMword i;
-// char *local = malloc (len);
-//
-// if (local == NULL) {
-// fprintf (stderr,
-// "sim: Unable to write 0x%lx bytes - out of memory\n",
-// (long unsigned int) len);
-// return;
-// }
-//
-// for (i = 0; i < len; i++){
-// //local[i] = ARMul_ReadByte (state, ptr + i);
-// ARMword data;
-// mem_read(8, ptr + i, &data);
-// local[i] = data & 0xFF;
-// }
-//
-// res = write (f, local, len);
-// //state->Reg[0] = res == -1 ? -1 : len - res;
-// state->Reg[0] = res;
-// free (local);
-//}
-
-//static void
-//SWIflen (ARMul_State * state, ARMword fh)
-//{
-// ARMword addr;
-//
-// if (fh == 0 || fh > FOPEN_MAX) {
-// state->Reg[0] = -1L;
-// return;
-// }
-//
-// addr = lseek (fh, 0, SEEK_CUR);
-//
-// state->Reg[0] = lseek (fh, 0L, SEEK_END);
-// (void) lseek (fh, addr, SEEK_SET);
-//
-//}
-
-/***************************************************************************\
-* The emulator calls this routine when a SWI instruction is encuntered. The *
-* parameter passed is the SWI number (lower 24 bits of the instruction). *
-\***************************************************************************/
-/* ahe-ykl information is retrieved from elf header and the starting value of
- brk_static is in sky_info_t */
-
-/* brk static hold the value of brk */
-static uint32_t brk_static = -1;
-
-unsigned
-ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
-{
- number &= 0xfffff;
- ARMword addr, temp;
-
- switch (number) {
-// case SWI_Syscall:
-// if (state->Reg[7] != 0)
-// return ARMul_OSHandleSWI(state, state->Reg[7]);
-// else
-// return FALSE;
-// case SWI_Read:
-// SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
-// return TRUE;
-//
-// case SWI_GetUID32:
-// state->Reg[0] = getuid();
-// return TRUE;
-//
-// case SWI_GetGID32:
-// state->Reg[0] = getgid();
-// return TRUE;
-//
-// case SWI_GetEUID32:
-// state->Reg[0] = geteuid();
-// return TRUE;
-//
-// case SWI_GetEGID32:
-// state->Reg[0] = getegid();
-// return TRUE;
-//
-// case SWI_Write:
-// SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
-// return TRUE;
-//
-// case SWI_Open:
-// SWIopen (state, state->Reg[0], state->Reg[1]);
-// return TRUE;
-//
-// case SWI_Close:
-// state->Reg[0] = close (state->Reg[0]);
-// return TRUE;
-//
-// case SWI_Seek:{
-// /* We must return non-zero for failure */
-// state->Reg[0] =
-// lseek (state->Reg[0], state->Reg[1],
-// SEEK_SET);
-// return TRUE;
-// }
-//
-// case SWI_ExitGroup:
-// case SWI_Exit:
-// {
-// struct timeval tv;
-// //gettimeofday(&tv,NULL);
-// //printf("In %s, %d sec, %d usec\n", __FUNCTION__, tv.tv_sec, tv.tv_usec);
-// printf("passed %d sec, %lld usec\n", get_clock_sec(), get_clock_us());
-//
-// /* quit here */
-// run_command("quit");
-// return TRUE;
-// }
-// case SWI_Times:{
-// uint32_t dest = state->Reg[0];
-// struct tms now;
-// struct target_tms32 nowret;
-//
-// uint32_t ret = times(&now);
-//
-// if (ret == -1){
-// debug("syscall %s error %d\n", "SWI_Times", ret);
-// state->Reg[0] = ret;
-// return FALSE;
-// }
-//
-// nowret.tms_cstime = now.tms_cstime;
-// nowret.tms_cutime = now.tms_cutime;
-// nowret.tms_stime = now.tms_stime;
-// nowret.tms_utime = now.tms_utime;
-//
-// uint32_t offset;
-// for (offset = 0; offset < sizeof(nowret); offset++) {
-// bus_write(8, dest + offset, *((uint8_t *) &nowret + offset));
-// }
-//
-// state->Reg[0] = ret;
-// return TRUE;
-// }
-//
-// case SWI_Gettimeofday: {
-// uint32_t dest1 = state->Reg[0];
-// uint32_t dest2 = state->Reg[1]; // Unsure of this
-// struct timeval val;
-// struct timezone zone;
-// struct target_timeval32 valret;
-// struct target_timezone32 zoneret;
-//
-// uint32_t ret = gettimeofday(&val, &zone);
-// valret.tv_sec = val.tv_sec;
-// valret.tv_usec = val.tv_usec;
-// zoneret.tz_dsttime = zoneret.tz_dsttime;
-// zoneret.tz_minuteswest = zoneret.tz_minuteswest;
-//
-// if (ret == -1){
-// debug("syscall %s error %d\n", "SWI_Gettimeofday", ret);
-// state->Reg[0] = ret;
-// return FALSE;
-// }
-//
-// uint32_t offset;
-// if (dest1) {
-// for (offset = 0; offset < sizeof(valret); offset++) {
-// bus_write(8, dest1 + offset, *((uint8_t *) &valret + offset));
-// }
-// state->Reg[0] = ret;
-// }
-// if (dest2) {
-// for (offset = 0; offset < sizeof(zoneret); offset++) {
-// bus_write(8, dest2 + offset, *((uint8_t *) &zoneret + offset));
-// }
-// state->Reg[0] = ret;
-// }
-//
-// return TRUE;
-// }
-// case SWI_Brk:
-// /* initialize brk value */
-// /* suppose that brk_static doesn't reach 0xffffffff... */
-// if (brk_static == -1) {
-// brk_static = (get_skyeye_pref()->info).brk;
-// }
-//
-// /* FIXME there might be a need to do a mmap */
-//
-// if(state->Reg[0]){
-// if (get_skyeye_exec_info()->mmap_access) {
-// /* if new brk is greater than current brk, allocate memory */
-// if (state->Reg[0] > brk_static) {
-// uint32_t ret = mmap( (void *) brk_static, state->Reg[0] - brk_static,
-// PROT_WRITE, MAP_PRIVATE | MAP_FIXED | MAP_ANONYMOUS, -1, 0 );
-// if (ret != MAP_FAILED)
-// brk_static = ret;
-// }
-// }
-// brk_static = state->Reg[0];
-// //state->Reg[0] = 0; /* FIXME return value of brk set to be the address on success */
-// } else {
-// state->Reg[0] = brk_static;
-// }
-// return TRUE;
-//
-// case SWI_Break:
-// state->Emulate = FALSE;
-// return TRUE;
-//
-// case SWI_Mmap:{
-// int addr = state->Reg[0];
-// int len = state->Reg[1];
-// int prot = state->Reg[2];
-// int flag = state->Reg[3];
-// int fd = state->Reg[4];
-// int offset = state->Reg[5];
-// mmap_area_t *area = new_mmap_area(addr, len);
-// state->Reg[0] = area->bank.addr;
-// //printf("syscall %d mmap(0x%x,%x,0x%x,0x%x,%d,0x%x) = 0x%x\n",\
-// SWI_Mmap, addr, len, prot, flag, fd, offset, state->Reg[0]);
-// return TRUE;
-// }
-//
-// case SWI_Munmap:
-// state->Reg[0] = 0;
-// return TRUE;
-//
-// case SWI_Mmap2:{
-// int addr = state->Reg[0];
-// int len = state->Reg[1];
-// int prot = state->Reg[2];
-// int flag = state->Reg[3];
-// int fd = state->Reg[4];
-// int offset = state->Reg[5] * 4096; /* page offset */
-// mmap_area_t *area = new_mmap_area(addr, len);
-// state->Reg[0] = area->bank.addr;
-//
-// return TRUE;
-// }
-//
-// case SWI_Breakpoint:
-// //chy 2005-09-12 change below line
-// //state->EndCondition = RDIError_BreakpointReached;
-// //printf ("SKYEYE: in armos.c : should not come here!!!!\n");
-// state->EndCondition = 0;
-// /*modified by ksh to support breakpoiont*/
-// state->Emulate = STOP;
-// return (TRUE);
-// case SWI_Uname:
-// {
-// struct utsname *uts = (uintptr_t) state->Reg[0]; /* uname should write data in this address */
-// struct utsname utsbuf;
-// //printf("Uname size is %x\n", sizeof(utsbuf));
-// char *buf;
-// uintptr_t sp ; /* used as a temporary address */
-//
-//#define COPY_UTS_STRING(addr) \
-// buf = addr; \
-// while(*buf != NULL) { \
-// bus_write(8, sp, *buf); \
-// sp++; \
-// buf++; \
-// }
-//#define COPY_UTS(field) /*printf("%s: %s at %p\n", #field, utsbuf.field, uts->field);*/ \
-// sp = (uintptr_t) uts->field; \
-// COPY_UTS_STRING((&utsbuf)->field);
-//
-// if (uname(&utsbuf) < 0) {
-// printf("syscall uname: utsname error\n");
-// state->Reg[0] = -1;
-// return FALSE;
-// }
-//
-// /* FIXME for now, this is just the host system call
-// Some data should be missing, as it depends on
-// the version of utsname */
-// COPY_UTS(sysname);
-// COPY_UTS(nodename);
-// COPY_UTS(release);
-// COPY_UTS(version);
-// COPY_UTS(machine);
-//
-// state->Reg[0] = 0;
-// return TRUE;
-// }
-// case SWI_Fcntl:
-// {
-// uint32_t fd = state->Reg[0];
-// uint32_t cmd = state->Reg[1];
-// uint32_t arg = state->Reg[2];
-// uint32_t ret;
-//
-// switch(cmd){
-// case (F_GETFD):
-// {
-// ret = fcntl(fd, cmd, arg);
-// //printf("syscall fcntl for getfd not implemented, ret %d\n", ret);
-// state->Reg[0] = ret;
-// return FALSE;
-// }
-// default:
-// break;
-// }
-//
-// printf("syscall fcntl unimplemented fd %x cmd %x\n", fd, cmd);
-// state->Reg[0] = -1;
-// return FALSE;
-//
-// }
-// case SWI_Fstat64:
-// {
-// uint32_t dest = state->Reg[1];
-// uint32_t fd = state->Reg[0];
-// struct stat64 statbuf;
-// struct target_stat64 statret;
-// memset(&statret, 0, sizeof(struct target_stat64));
-// uint32_t ret = fstat64(fd, &statbuf);
-//
-// if (ret == -1){
-// printf("syscall %s returned error\n", "SWI_Fstat");
-// state->Reg[0] = ret;
-// return FALSE;
-// }
-//
-// /* copy statbuf to the process memory space
-// FIXME can't say if endian has an effect here */
-// uint32_t offset;
-// //printf("Fstat system is size %x\n", sizeof(statbuf));
-// //printf("Fstat target is size %x\n", sizeof(statret));
-//
-// /* we copy system structure data stat64 into arm fixed size structure target_stat64 */
-// statret.st_dev = statbuf.st_dev;
-// statret.st_ino = statbuf.st_ino;
-// statret.st_mode = statbuf.st_mode;
-// statret.st_nlink = statbuf.st_nlink;
-// statret.st_uid = statbuf.st_uid;
-// statret.st_gid = statbuf.st_gid;
-// statret.st_rdev = statbuf.st_rdev;
-// statret.st_size = statbuf.st_size;
-// statret.st_blksize = statbuf.st_blksize;
-// statret.st_blocks = statbuf.st_blocks;
-// statret.st32_atime = statbuf.st_atime;
-// statret.st32_mtime = statbuf.st_mtime;
-// statret.st32_ctime = statbuf.st_ctime;
-//
-// for (offset = 0; offset < sizeof(statret); offset++) {
-// bus_write(8, dest + offset, *((uint8_t *) &statret + offset));
-// }
-//
-// state->Reg[0] = ret;
-// return TRUE;
-// }
-// case SWI_Set_tls:
-// {
-// //printf("syscall set_tls unimplemented\n");
-// state->mmu.thread_uro_id = state->Reg[0];
-// state->CP15[CP15_THREAD_URO - CP15_BASE] = state->Reg[0];
-// state->Reg[0] = 0;
-// return FALSE;
-// }
-//#if 0
-// case SWI_Clock:
-// /* return number of centi-seconds... */
-// state->Reg[0] =
-//#ifdef CLOCKS_PER_SEC
-// (CLOCKS_PER_SEC >= 100)
-// ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
-// : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
-//#else
-// /* presume unix... clock() returns microseconds */
-// (ARMword) (clock () / 10000);
-//#endif
-// return (TRUE);
-//
-// case SWI_Time:
-// state->Reg[0] = (ARMword) time (NULL);
-// return (TRUE);
-// case SWI_Flen:
-// SWIflen (state, state->Reg[0]);
-// return (TRUE);
-//
-//#endif
- default:
-
- _dbg_assert_msg_(ARM11, false, "ImplementMe: ARMul_OSHandleSWI!");
-
- return (FALSE);
- }
-}
-//
-///**
-// * @brief For mmap syscall.A mmap_area is a memory bank. Get from ppc.
-// */
-//static mmap_area_t* new_mmap_area(int sim_addr, int len){
-// mmap_area_t *area = (mmap_area_t *)malloc(sizeof(mmap_area_t));
-// if(area == NULL){
-// printf("error, failed %s\n",__FUNCTION__);
-// exit(0);
-// }
-//#if FAST_MEMORY
-// if (mmap_next_base == -1)
-// {
-// mmap_next_base = get_skyeye_exec_info()->brk;
-// }
-//#endif
-//
-// memset(area, 0x0, sizeof(mmap_area_t));
-// area->bank.addr = mmap_next_base;
-// area->bank.len = len;
-// area->bank.bank_write = mmap_mem_write;
-// area->bank.bank_read = mmap_mem_read;
-// area->bank.type = MEMTYPE_RAM;
-// area->bank.objname = "mmap";
-// addr_mapping(&area->bank);
-//
-//#if FAST_MEMORY
-// if (get_skyeye_exec_info()->mmap_access)
-// {
-// /* FIXME check proper flags */
-// /* FIXME we may delete the need of banks up there */
-// uint32_t ret = mmap(mmap_next_base, len, PROT_WRITE | PROT_READ, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-// mmap_next_base = ret;
-// }
-// area->mmap_addr = (uint8_t*)get_dma_addr(mmap_next_base);
-//#else
-// area->mmap_addr = malloc(len);
-// if(area->mmap_addr == NULL){
-// printf("error mmap malloc\n");
-// exit(0);
-// }
-// memset(area->mmap_addr, 0x0, len);
-//#endif
-//
-// area->next = NULL;
-// if(mmap_global){
-// area->next = mmap_global->next;
-// mmap_global->next = area;
-// }else{
-// mmap_global = area;
-// }
-// mmap_next_base = mmap_next_base + len;
-// return area;
-//}
-//
-//static mmap_area_t *get_mmap_area(int addr){
-// mmap_area_t *tmp = mmap_global;
-// while(tmp){
-// if ((tmp->bank.addr <= addr) && (tmp->bank.addr + tmp->bank.len > addr)){
-// return tmp;
-// }
-// tmp = tmp->next;
-// }
-// printf("cannot get mmap area:addr=0x%x\n", addr);
-// return NULL;
-//}
-//
-///**
-// * @brief the mmap_area bank write function. Get from ppc.
-// *
-// * @param size size to write, 8/16/32
-// * @param addr address to write
-// * @param value value to write
-// *
-// * @return sucess return 1,otherwise 0.
-// */
-//static char mmap_mem_write(short size, int addr, uint32_t value){
-// mmap_area_t *area_tmp = get_mmap_area(addr);
-// mem_bank_t *bank_tmp = &area_tmp->bank;
-// int offset = addr - bank_tmp->addr;
-// switch(size){
-// case 8:{
-// //uint8_t value_endian = value;
-// uint8_t value_endian = (uint8_t)value;
-// *(uint8_t *)&(((char *)area_tmp->mmap_addr)[offset]) = value_endian;
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,value_endian);
-// break;
-// }
-// case 16:{
-// //uint16_t value_endian = half_to_BE((uint16_t)value);
-// uint16_t value_endian = ((uint16_t)value);
-// *(uint16_t *)&(((char *)area_tmp->mmap_addr)[offset]) = value_endian;
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,value_endian);
-// break;
-// }
-// case 32:{
-// //uint32_t value_endian = word_to_BE((uint32_t)value);
-// uint32_t value_endian = ((uint32_t)value);
-// *(uint32_t *)&(((char *)area_tmp->mmap_addr)[offset]) = value_endian;
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,value_endian);
-// break;
-// }
-// default:
-// printf("invalid size %d\n",size);
-// return 0;
-// }
-// return 1;
-//}
-//
-///**
-// * @brief the mmap_area bank read function. Get from ppc.
-// *
-// * @param size size to read, 8/16/32
-// * @param addr address to read
-// * @param value value to read
-// *
-// * @return sucess return 1,otherwise 0.
-// */
-//static char mmap_mem_read(short size, int addr, uint32_t * value){
-// mmap_area_t *area_tmp = get_mmap_area(addr);
-// mem_bank_t *bank_tmp = &area_tmp->bank;
-// int offset = addr - bank_tmp->addr;
-// switch(size){
-// case 8:{
-// //*(uint8_t *)value = *(uint8_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]);
-// *value = *(uint8_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]);
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,*(uint32_t*)value);
-// break;
-// }
-// case 16:{
-// //*(uint16_t *)value = half_from_BE(*(uint16_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]));
-// *value = (*(uint16_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]));
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,*(uint16_t*)value);
-// break;
-// }
-// case 32:
-// //*value = (uint32_t)word_from_BE(*(uint32_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]));
-// *value = (uint32_t)(*(uint32_t *)&(((uint8_t *)area_tmp->mmap_addr)[offset]));
-// debug("in %s,size=%d,addr=0x%x,value=0x%x\n",__FUNCTION__,size,addr,*(uint32_t*)value);
-// break;
-// default:
-// printf("invalid size %d\n",size);
-// return 0;
-// }
-// return 1;
-//}
From 818ba32746072af65a7b5ac0f1712bde3388f641 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Tue, 7 Oct 2014 18:56:40 -0400
Subject: [PATCH 5/5] ARM: Removed unnecessary and unused SkyEye MMU code.
Added license header back in. I originally removed this because I mostly rewrote the file, but meh
---
src/core/CMakeLists.txt | 15 -
src/core/arm/dyncom/arm_dyncom.cpp | 1 -
src/core/arm/interpreter/arm_interpreter.cpp | 1 -
src/core/arm/interpreter/armcopro.cpp | 986 +++---------
src/core/arm/interpreter/armmmu.cpp | 238 ---
src/core/arm/interpreter/armvirt.cpp | 745 ++-------
.../arm/interpreter/mmu/arm1176jzf_s_mmu.cpp | 1132 --------------
.../arm/interpreter/mmu/arm1176jzf_s_mmu.h | 37 -
src/core/arm/interpreter/mmu/cache.cpp | 370 -----
src/core/arm/interpreter/mmu/cache.h | 168 --
src/core/arm/interpreter/mmu/maverick.cpp | 1206 --------------
src/core/arm/interpreter/mmu/rb.cpp | 126 --
src/core/arm/interpreter/mmu/rb.h | 55 -
src/core/arm/interpreter/mmu/sa_mmu.cpp | 864 ----------
src/core/arm/interpreter/mmu/sa_mmu.h | 58 -
src/core/arm/interpreter/mmu/tlb.cpp | 307 ----
src/core/arm/interpreter/mmu/tlb.h | 87 --
src/core/arm/interpreter/mmu/wb.cpp | 149 --
src/core/arm/interpreter/mmu/wb.h | 63 -
src/core/arm/interpreter/mmu/xscale_copro.cpp | 1391 -----------------
src/core/arm/skyeye_common/armdefs.h | 1 -
src/core/arm/skyeye_common/armmmu.h | 117 --
22 files changed, 350 insertions(+), 7767 deletions(-)
delete mode 100644 src/core/arm/interpreter/armmmu.cpp
delete mode 100644 src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
delete mode 100644 src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.h
delete mode 100644 src/core/arm/interpreter/mmu/cache.cpp
delete mode 100644 src/core/arm/interpreter/mmu/cache.h
delete mode 100644 src/core/arm/interpreter/mmu/maverick.cpp
delete mode 100644 src/core/arm/interpreter/mmu/rb.cpp
delete mode 100644 src/core/arm/interpreter/mmu/rb.h
delete mode 100644 src/core/arm/interpreter/mmu/sa_mmu.cpp
delete mode 100644 src/core/arm/interpreter/mmu/sa_mmu.h
delete mode 100644 src/core/arm/interpreter/mmu/tlb.cpp
delete mode 100644 src/core/arm/interpreter/mmu/tlb.h
delete mode 100644 src/core/arm/interpreter/mmu/wb.cpp
delete mode 100644 src/core/arm/interpreter/mmu/wb.h
delete mode 100644 src/core/arm/interpreter/mmu/xscale_copro.cpp
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index cc0deb004e..aefbe3375d 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -6,19 +6,10 @@ set(SRCS
arm/dyncom/arm_dyncom_interpreter.cpp
arm/dyncom/arm_dyncom_run.cpp
arm/dyncom/arm_dyncom_thumb.cpp
- arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
- arm/interpreter/mmu/cache.cpp
- arm/interpreter/mmu/maverick.cpp
- arm/interpreter/mmu/rb.cpp
- arm/interpreter/mmu/sa_mmu.cpp
- arm/interpreter/mmu/tlb.cpp
- arm/interpreter/mmu/wb.cpp
- arm/interpreter/mmu/xscale_copro.cpp
arm/interpreter/arm_interpreter.cpp
arm/interpreter/armcopro.cpp
arm/interpreter/armemu.cpp
arm/interpreter/arminit.cpp
- arm/interpreter/armmmu.cpp
arm/interpreter/armsupp.cpp
arm/interpreter/armvirt.cpp
arm/interpreter/thumbemu.cpp
@@ -72,12 +63,6 @@ set(HEADERS
arm/dyncom/arm_dyncom_run.h
arm/dyncom/arm_dyncom_thumb.h
arm/interpreter/arm_interpreter.h
- arm/interpreter/mmu/arm1176jzf_s_mmu.h
- arm/interpreter/mmu/cache.h
- arm/interpreter/mmu/rb.h
- arm/interpreter/mmu/sa_mmu.h
- arm/interpreter/mmu/tlb.h
- arm/interpreter/mmu/wb.h
arm/skyeye_common/arm_regformat.h
arm/skyeye_common/armcpu.h
arm/skyeye_common/armdefs.h
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 7a65669ef1..669b612fc4 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -27,7 +27,6 @@ ARM_DynCom::ARM_DynCom() : ticks(0) {
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->lateabtSig = LOW;
- mmu_init(state);
// Reset the core to initial state
ARMul_CoProInit(state.get());
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 6f6a5913cb..ed44150828 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -22,7 +22,6 @@ ARM_Interpreter::ARM_Interpreter() {
ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->lateabtSig = LOW;
- mmu_init(state);
// Reset the core to initial state
ARMul_CoProInit(state);
diff --git a/src/core/arm/interpreter/armcopro.cpp b/src/core/arm/interpreter/armcopro.cpp
index 9de6651d47..b4ddc3d961 100644
--- a/src/core/arm/interpreter/armcopro.cpp
+++ b/src/core/arm/interpreter/armcopro.cpp
@@ -15,7 +15,6 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/armemu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
@@ -25,817 +24,302 @@
//chy -------
//#include "iwmmxt.h"
-
-//chy 2005-09-19 add CP6 MRC support (for get irq number and base)
-extern unsigned xscale_cp6_mrc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-//chy 2005-09-19---------------
-
-extern unsigned xscale_cp13_init (ARMul_State * state);
-extern unsigned xscale_cp13_exit (ARMul_State * state);
-extern unsigned xscale_cp13_ldc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp13_stc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp13_mrc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp13_mcr (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp13_cdp (ARMul_State * state, unsigned type,
- ARMword instr);
-extern unsigned xscale_cp13_read_reg (ARMul_State * state, unsigned reg,
- ARMword * data);
-extern unsigned xscale_cp13_write_reg (ARMul_State * state, unsigned reg,
- ARMword data);
-extern unsigned xscale_cp14_init (ARMul_State * state);
-extern unsigned xscale_cp14_exit (ARMul_State * state);
-extern unsigned xscale_cp14_ldc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp14_stc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp14_mrc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp14_mcr (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp14_cdp (ARMul_State * state, unsigned type,
- ARMword instr);
-extern unsigned xscale_cp14_read_reg (ARMul_State * state, unsigned reg,
- ARMword * data);
-extern unsigned xscale_cp14_write_reg (ARMul_State * state, unsigned reg,
- ARMword data);
-extern unsigned xscale_cp15_init (ARMul_State * state);
-extern unsigned xscale_cp15_exit (ARMul_State * state);
-extern unsigned xscale_cp15_ldc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp15_stc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp15_mrc (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * data);
-extern unsigned xscale_cp15_mcr (ARMul_State * state, unsigned type,
- ARMword instr, ARMword data);
-extern unsigned xscale_cp15_cdp (ARMul_State * state, unsigned type,
- ARMword instr);
-extern unsigned xscale_cp15_read_reg (ARMul_State * state, unsigned reg,
- ARMword * data);
-extern unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg,
- ARMword data);
-extern unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
- unsigned cpnum);
-
/* Dummy Co-processors. */
static unsigned
-NoCoPro3R (ARMul_State * state,
- unsigned a, ARMword b)
+NoCoPro3R(ARMul_State * state,
+unsigned a, ARMword b)
{
- return ARMul_CANT;
+ return ARMul_CANT;
}
static unsigned
-NoCoPro4R (ARMul_State * state,
- unsigned a,
- ARMword b, ARMword c)
+NoCoPro4R(ARMul_State * state,
+unsigned a,
+ARMword b, ARMword c)
{
- return ARMul_CANT;
+ return ARMul_CANT;
}
static unsigned
-NoCoPro4W (ARMul_State * state,
- unsigned a,
- ARMword b, ARMword * c)
+NoCoPro4W(ARMul_State * state,
+unsigned a,
+ARMword b, ARMword * c)
{
- return ARMul_CANT;
+ return ARMul_CANT;
}
static unsigned
-NoCoPro5R (ARMul_State * state,
- unsigned a,
- ARMword b,
- ARMword c, ARMword d)
+NoCoPro5R(ARMul_State * state,
+unsigned a,
+ARMword b,
+ARMword c, ARMword d)
{
- return ARMul_CANT;
+ return ARMul_CANT;
}
static unsigned
-NoCoPro5W (ARMul_State * state,
- unsigned a,
- ARMword b,
- ARMword * c, ARMword * d )
+NoCoPro5W(ARMul_State * state,
+unsigned a,
+ARMword b,
+ARMword * c, ARMword * d)
{
- return ARMul_CANT;
+ return ARMul_CANT;
}
/* The XScale Co-processors. */
/* Coprocessor 15: System Control. */
-static void write_cp14_reg (unsigned, ARMword);
-static ARMword read_cp14_reg (unsigned);
-
-/* There are two sets of registers for copro 15.
- One set is available when opcode_2 is 0 and
- the other set when opcode_2 >= 1. */
-static ARMword XScale_cp15_opcode_2_is_0_Regs[16];
-static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16];
-/* There are also a set of breakpoint registers
- which are accessed via CRm instead of opcode_2. */
-static ARMword XScale_cp15_DBR1;
-static ARMword XScale_cp15_DBCON;
-static ARMword XScale_cp15_IBCR0;
-static ARMword XScale_cp15_IBCR1;
-
-static unsigned
-XScale_cp15_init (ARMul_State * state)
-{
- int i;
-
- for (i = 16; i--;) {
- XScale_cp15_opcode_2_is_0_Regs[i] = 0;
- XScale_cp15_opcode_2_is_not_0_Regs[i] = 0;
- }
-
- /* Initialise the processor ID. */
- //chy 2003-03-24, is same as cpu id in skyeye_options.c
- //XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
- XScale_cp15_opcode_2_is_0_Regs[0] = 0x69050000;
-
- /* Initialise the cache type. */
- XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA;
-
- /* Initialise the ARM Control Register. */
- XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
-
- return No_exp;
-}
+static void write_cp14_reg(unsigned, ARMword);
+static ARMword read_cp14_reg(unsigned);
/* Check an access to a register. */
static unsigned
-check_cp15_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm, unsigned opcode_1, unsigned opcode_2)
+check_cp15_access(ARMul_State * state,
+unsigned reg,
+unsigned CRm, unsigned opcode_1, unsigned opcode_2)
{
- /* Do not allow access to these register in USER mode. */
- //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
- if (state->Mode == USER26MODE || state->Mode == USER32MODE )
- return ARMul_CANT;
-
- /* Opcode_1should be zero. */
- if (opcode_1 != 0)
- return ARMul_CANT;
-
- /* Different register have different access requirements. */
- switch (reg) {
- case 0:
- case 1:
- /* CRm must be 0. Opcode_2 can be anything. */
- if (CRm != 0)
- return ARMul_CANT;
- break;
- case 2:
- case 3:
- /* CRm must be 0. Opcode_2 must be zero. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 4:
- /* Access not allowed. */
- return ARMul_CANT;
- case 5:
- case 6:
- /* Opcode_2 must be zero. CRm must be 0. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 7:
- /* Permissable combinations:
- Opcode_2 CRm
- 0 5
- 0 6
- 0 7
- 1 5
- 1 6
- 1 10
- 4 10
- 5 2
- 6 5 */
- switch (opcode_2) {
- default:
- return ARMul_CANT;
- case 6:
- if (CRm != 5)
- return ARMul_CANT;
- break;
- case 5:
- if (CRm != 2)
- return ARMul_CANT;
- break;
- case 4:
- if (CRm != 10)
- return ARMul_CANT;
- break;
- case 1:
- if ((CRm != 5) && (CRm != 6) && (CRm != 10))
- return ARMul_CANT;
- break;
- case 0:
- if ((CRm < 5) || (CRm > 7))
- return ARMul_CANT;
- break;
- }
- break;
-
- case 8:
- /* Permissable combinations:
- Opcode_2 CRm
- 0 5
- 0 6
- 0 7
- 1 5
- 1 6 */
- if (opcode_2 > 1)
- return ARMul_CANT;
- if ((CRm < 5) || (CRm > 7))
- return ARMul_CANT;
- if (opcode_2 == 1 && CRm == 7)
- return ARMul_CANT;
- break;
- case 9:
- /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
- if (((CRm != 0) && (CRm != 1))
- || ((opcode_2 != 1) && (opcode_2 != 2)))
- return ARMul_CANT;
- break;
- case 10:
- /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
- if (((CRm != 0) && (CRm != 1))
- || ((opcode_2 != 4) && (opcode_2 != 8)))
- return ARMul_CANT;
- break;
- case 11:
- /* Access not allowed. */
- return ARMul_CANT;
- case 12:
- /* Access not allowed. */
- return ARMul_CANT;
- case 13:
- /* Opcode_2 must be zero. CRm must be 0. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 14:
- /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
- if (opcode_2 != 0)
- return ARMul_CANT;
-
- if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8)
- && (CRm != 9))
- return ARMul_CANT;
- break;
- case 15:
- /* Opcode_2 must be zero. CRm must be 1. */
- if ((CRm != 1) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- default:
- /* Should never happen. */
- return ARMul_CANT;
- }
-
- return ARMul_DONE;
-}
-
-/* Coprocessor 13: Interrupt Controller and Bus Controller. */
-
-/* There are two sets of registers for copro 13.
- One set (of three registers) is available when CRm is 0
- and the other set (of six registers) when CRm is 1. */
-
-static ARMword XScale_cp13_CR0_Regs[16];
-static ARMword XScale_cp13_CR1_Regs[16];
-
-static unsigned
-XScale_cp13_init (ARMul_State * state)
-{
- int i;
-
- for (i = 16; i--;) {
- XScale_cp13_CR0_Regs[i] = 0;
- XScale_cp13_CR1_Regs[i] = 0;
- }
-
- return No_exp;
-}
-
-/* Check an access to a register. */
-
-static unsigned
-check_cp13_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm, unsigned opcode_1, unsigned opcode_2)
-{
- /* Do not allow access to these registers in USER mode. */
- //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
- if (state->Mode == USER26MODE || state->Mode == USER32MODE )
- return ARMul_CANT;
-
- /* The opcodes should be zero. */
- if ((opcode_1 != 0) || (opcode_2 != 0))
- return ARMul_CANT;
-
- /* Do not allow access to these register if bit
- 13 of coprocessor 15's register 15 is zero. */
- if (!CP_ACCESS_ALLOWED (state, 13))
- return ARMul_CANT;
-
- /* Registers 0, 4 and 8 are defined when CRm == 0.
- Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
- For all other CRm values undefined behaviour results. */
- if (CRm == 0) {
- if (reg == 0 || reg == 4 || reg == 8)
- return ARMul_DONE;
- }
- else if (CRm == 1) {
- if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
- return ARMul_DONE;
- }
-
- return ARMul_CANT;
-}
-
-/* Coprocessor 14: Performance Monitoring, Clock and Power management,
- Software Debug. */
-
-static ARMword XScale_cp14_Regs[16];
-
-static unsigned
-XScale_cp14_init (ARMul_State * state)
-{
- int i;
-
- for (i = 16; i--;)
- XScale_cp14_Regs[i] = 0;
-
- return No_exp;
-}
-
-/* Check an access to a register. */
-
-static unsigned
-check_cp14_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm, unsigned opcode1, unsigned opcode2)
-{
- /* Not allowed to access these register in USER mode. */
- //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
- if (state->Mode == USER26MODE || state->Mode == USER32MODE )
- return ARMul_CANT;
-
- /* CRm should be zero. */
- if (CRm != 0)
- return ARMul_CANT;
-
- /* OPcodes should be zero. */
- if (opcode1 != 0 || opcode2 != 0)
- return ARMul_CANT;
-
- /* Accessing registers 4 or 5 has unpredicatable results. */
- if (reg >= 4 && reg <= 5)
- return ARMul_CANT;
-
- return ARMul_DONE;
-}
-
-/* Here's ARMulator's MMU definition. A few things to note:
- 1) It has eight registers, but only two are defined.
- 2) You can only access its registers with MCR and MRC.
- 3) MMU Register 0 (ID) returns 0x41440110
- 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
- controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
- bit 6 controls late abort timimg and bit 7 controls big/little endian. */
-
-static ARMword MMUReg[8];
-
-static unsigned
-MMUInit (ARMul_State * state)
-{
-/* 2004-05-09 chy
--------------------------------------------------------------
-read ARM Architecture Reference Manual
-2.6.5 Data Abort
-There are three Abort Model in ARM arch.
-
-Early Abort Model: used in some ARMv3 and earlier implementations. In this
-model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and
-the base register was unchanged for all other instructions. (oldest)
-
-Base Restored Abort Model: If a Data Abort occurs in an instruction which
-specifies base register writeback, the value in the base register is
-unchanged. (strongarm, xscale)
-
-Base Updated Abort Model: If a Data Abort occurs in an instruction which
-specifies base register writeback, the base register writeback still occurs.
-(arm720T)
-
-read PART B
-chap2 The System Control Coprocessor CP15
-2.4 Register1:control register
-L(bit 6): in some ARMv3 and earlier implementations, the abort model of the
-processor could be configured:
-0=early Abort Model Selected(now obsolete)
-1=Late Abort Model selceted(same as Base Updated Abort Model)
-
-on later processors, this bit reads as 1 and ignores writes.
--------------------------------------------------------------
-So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
- if lateabtSig=0, then it means Base Restored Abort Model
-because the ARMs which skyeye simulates are all belonged to ARMv4,
-so I think MMUReg[1]'s bit 6 should always be 1
-
-*/
-
- MMUReg[1] = state->prog32Sig << 4 |
- state->data32Sig << 5 | 1 << 6 | state->bigendSig << 7;
- //state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
-
-
- NOTICE_LOG(ARM11, "ARMul_ConsolePrint: MMU present");
-
- return TRUE;
-}
-
-static unsigned
-MMUMRC (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * value)
-{
- mmu_mrc (state, instr, value);
- return (ARMul_DONE);
-}
-
-static unsigned
-MMUMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
-{
- mmu_mcr (state, instr, value);
- return (ARMul_DONE);
-}
-
-/* What follows is the Validation Suite Coprocessor. It uses two
- co-processor numbers (4 and 5) and has the follwing functionality.
- Sixteen registers. Both co-processor nuimbers can be used in an MCR
- and MRC to access these registers. CP 4 can LDC and STC to and from
- the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of
- cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a
- number of cycles (specified in a CP register), CDP 2 issues an IRQW
- in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5
- stores a 32 bit time value in a CP register (actually it's the total
- number of N, S, I, C and F cyles). */
-
-static ARMword ValReg[16];
-
-static unsigned
-ValLDC (ARMul_State * state,
- unsigned type, ARMword instr, ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- words = 0;
- else {
- ValReg[BITS (12, 15)] = data;
-
- if (BIT (22))
- /* It's a long access, get two words. */
- if (words++ != 4)
- return ARMul_INC;
- }
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValSTC (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- words = 0;
- else {
- *data = ValReg[BITS (12, 15)];
-
- if (BIT (22))
- /* It's a long access, get two words. */
- if (words++ != 4)
- return ARMul_INC;
- }
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValMRC (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * value)
-{
- *value = ValReg[BITS (16, 19)];
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValMCR (ARMul_State * state,
- unsigned type, ARMword instr, ARMword value)
-{
- ValReg[BITS (16, 19)] = value;
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValCDP (ARMul_State * state, unsigned type, ARMword instr)
-{
- static unsigned int finish = 0;
-
- if (BITS (20, 23) != 0)
- return ARMul_CANT;
-
- if (type == ARMul_FIRST) {
- ARMword howlong;
-
- howlong = ValReg[BITS (0, 3)];
-
- /* First cycle of a busy wait. */
- finish = ARMul_Time (state) + howlong;
-
- return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
- }
- else if (type == ARMul_BUSY) {
- if (ARMul_Time (state) >= finish)
- return ARMul_DONE;
- else
- return ARMul_BUSY;
- }
-
- return ARMul_CANT;
-}
-
-static unsigned
-DoAFIQ (ARMul_State * state)
-{
- state->NfiqSig = LOW;
- return 0;
-}
-
-static unsigned
-DoAIRQ (ARMul_State * state)
-{
- state->NirqSig = LOW;
- return 0;
-}
-
-static unsigned
-IntCDP (ARMul_State * state, unsigned type, ARMword instr)
-{
- static unsigned int finish;
- ARMword howlong;
-
- howlong = ValReg[BITS (0, 3)];
-
- switch ((int) BITS (20, 23)) {
- case 0:
- if (type == ARMul_FIRST) {
- /* First cycle of a busy wait. */
- finish = ARMul_Time (state) + howlong;
-
- return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
- }
- else if (type == ARMul_BUSY) {
- if (ARMul_Time (state) >= finish)
- return ARMul_DONE;
- else
- return ARMul_BUSY;
- }
- return ARMul_DONE;
-
- case 1:
- if (howlong == 0)
- ARMul_Abort (state, ARMul_FIQV);
- else
- ARMul_ScheduleEvent (state, howlong, DoAFIQ);
- return ARMul_DONE;
-
- case 2:
- if (howlong == 0)
- ARMul_Abort (state, ARMul_IRQV);
- else
- ARMul_ScheduleEvent (state, howlong, DoAIRQ);
- return ARMul_DONE;
-
- case 3:
- state->NfiqSig = HIGH;
- return ARMul_DONE;
-
- case 4:
- state->NirqSig = HIGH;
- return ARMul_DONE;
-
- case 5:
- ValReg[BITS (0, 3)] = ARMul_Time (state);
- return ARMul_DONE;
- }
-
- return ARMul_CANT;
+ /* Do not allow access to these register in USER mode. */
+ //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
+ if (state->Mode == USER26MODE || state->Mode == USER32MODE)
+ return ARMul_CANT;
+
+ /* Opcode_1should be zero. */
+ if (opcode_1 != 0)
+ return ARMul_CANT;
+
+ /* Different register have different access requirements. */
+ switch (reg) {
+ case 0:
+ case 1:
+ /* CRm must be 0. Opcode_2 can be anything. */
+ if (CRm != 0)
+ return ARMul_CANT;
+ break;
+ case 2:
+ case 3:
+ /* CRm must be 0. Opcode_2 must be zero. */
+ if ((CRm != 0) || (opcode_2 != 0))
+ return ARMul_CANT;
+ break;
+ case 4:
+ /* Access not allowed. */
+ return ARMul_CANT;
+ case 5:
+ case 6:
+ /* Opcode_2 must be zero. CRm must be 0. */
+ if ((CRm != 0) || (opcode_2 != 0))
+ return ARMul_CANT;
+ break;
+ case 7:
+ /* Permissable combinations:
+ Opcode_2 CRm
+ 0 5
+ 0 6
+ 0 7
+ 1 5
+ 1 6
+ 1 10
+ 4 10
+ 5 2
+ 6 5 */
+ switch (opcode_2) {
+ default:
+ return ARMul_CANT;
+ case 6:
+ if (CRm != 5)
+ return ARMul_CANT;
+ break;
+ case 5:
+ if (CRm != 2)
+ return ARMul_CANT;
+ break;
+ case 4:
+ if (CRm != 10)
+ return ARMul_CANT;
+ break;
+ case 1:
+ if ((CRm != 5) && (CRm != 6) && (CRm != 10))
+ return ARMul_CANT;
+ break;
+ case 0:
+ if ((CRm < 5) || (CRm > 7))
+ return ARMul_CANT;
+ break;
+ }
+ break;
+
+ case 8:
+ /* Permissable combinations:
+ Opcode_2 CRm
+ 0 5
+ 0 6
+ 0 7
+ 1 5
+ 1 6 */
+ if (opcode_2 > 1)
+ return ARMul_CANT;
+ if ((CRm < 5) || (CRm > 7))
+ return ARMul_CANT;
+ if (opcode_2 == 1 && CRm == 7)
+ return ARMul_CANT;
+ break;
+ case 9:
+ /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
+ if (((CRm != 0) && (CRm != 1))
+ || ((opcode_2 != 1) && (opcode_2 != 2)))
+ return ARMul_CANT;
+ break;
+ case 10:
+ /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
+ if (((CRm != 0) && (CRm != 1))
+ || ((opcode_2 != 4) && (opcode_2 != 8)))
+ return ARMul_CANT;
+ break;
+ case 11:
+ /* Access not allowed. */
+ return ARMul_CANT;
+ case 12:
+ /* Access not allowed. */
+ return ARMul_CANT;
+ case 13:
+ /* Opcode_2 must be zero. CRm must be 0. */
+ if ((CRm != 0) || (opcode_2 != 0))
+ return ARMul_CANT;
+ break;
+ case 14:
+ /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
+ if (opcode_2 != 0)
+ return ARMul_CANT;
+
+ if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8)
+ && (CRm != 9))
+ return ARMul_CANT;
+ break;
+ case 15:
+ /* Opcode_2 must be zero. CRm must be 1. */
+ if ((CRm != 1) || (opcode_2 != 0))
+ return ARMul_CANT;
+ break;
+ default:
+ /* Should never happen. */
+ return ARMul_CANT;
+ }
+
+ return ARMul_DONE;
}
/* Install co-processor instruction handlers in this routine. */
unsigned
-ARMul_CoProInit (ARMul_State * state)
+ARMul_CoProInit(ARMul_State * state)
{
- unsigned int i;
+ unsigned int i;
- /* Initialise tham all first. */
- for (i = 0; i < 16; i++)
- ARMul_CoProDetach (state, i);
+ /* Initialise tham all first. */
+ for (i = 0; i < 16; i++)
+ ARMul_CoProDetach(state, i);
- /* Install CoPro Instruction handlers here.
- The format is:
- ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
- LDC routine, STC routine, MRC routine, MCR routine,
- CDP routine, Read Reg routine, Write Reg routine). */
- if (state->is_ep9312) {
- ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4,
- DSPMRC4, DSPMCR4, NULL, NULL, DSPCDP4, NULL, NULL);
- ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5,
- DSPMRC5, DSPMCR5, NULL, NULL, DSPCDP5, NULL, NULL);
- ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL,
- DSPMRC6, DSPMCR6, NULL, NULL, DSPCDP6, NULL, NULL);
- }
- else {
- ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC,
- ValMRC, ValMCR, NULL, NULL, ValCDP, NULL, NULL);
+ /* Install CoPro Instruction handlers here.
+ The format is:
+ ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
+ LDC routine, STC routine, MRC routine, MCR routine,
+ CDP routine, Read Reg routine, Write Reg routine). */
+ if (state->is_v6) {
+ ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC,
+ VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
+ ARMul_CoProAttach(state, 11, VFPInit, NULL, VFPLDC, VFPSTC,
+ VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
- ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL,
- ValMRC, ValMCR, NULL, NULL, IntCDP, NULL, NULL);
- }
-
- if (state->is_XScale) {
- //chy 2005-09-19, for PXA27x's CP6
- if (state->is_pxa27x) {
- ARMul_CoProAttach (state, 6, NULL, NULL,
- NULL, NULL, xscale_cp6_mrc,
- NULL, NULL, NULL, NULL, NULL, NULL);
- }
- //chy 2005-09-19 end-------------
- ARMul_CoProAttach (state, 13, xscale_cp13_init,
- xscale_cp13_exit, xscale_cp13_ldc,
- xscale_cp13_stc, xscale_cp13_mrc,
- xscale_cp13_mcr, NULL, NULL, xscale_cp13_cdp,
- xscale_cp13_read_reg,
- xscale_cp13_write_reg);
-
- ARMul_CoProAttach (state, 14, xscale_cp14_init,
- xscale_cp14_exit, xscale_cp14_ldc,
- xscale_cp14_stc, xscale_cp14_mrc,
- xscale_cp14_mcr, NULL, NULL, xscale_cp14_cdp,
- xscale_cp14_read_reg,
- xscale_cp14_write_reg);
- //chy: 2003-08-24.
- ARMul_CoProAttach (state, 15, xscale_cp15_init,
- xscale_cp15_exit, xscale_cp15_ldc,
- xscale_cp15_stc, xscale_cp15_mrc,
- xscale_cp15_mcr, NULL, NULL, xscale_cp15_cdp,
- xscale_cp15_read_reg,
- xscale_cp15_write_reg);
- }
- else if (state->is_v6) {
- ARMul_CoProAttach (state, 10, VFPInit, NULL, VFPLDC, VFPSTC,
- VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
- ARMul_CoProAttach (state, 11, VFPInit, NULL, VFPLDC, VFPSTC,
- VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
-
- ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
- MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);
- }
- else { //all except xscale
- ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
- // MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
- MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);
- }
-//chy 2003-09-03 do it in future!!!!????
+ /*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
+ MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/
+ }
+ //chy 2003-09-03 do it in future!!!!????
#if 0
- if (state->is_iWMMXt) {
- ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC,
- NULL, NULL, IwmmxtCDP, NULL, NULL);
+ if (state->is_iWMMXt) {
+ ARMul_CoProAttach(state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC,
+ NULL, NULL, IwmmxtCDP, NULL, NULL);
- ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL,
- IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL,
- NULL);
- }
+ ARMul_CoProAttach(state, 1, NULL, NULL, NULL, NULL,
+ IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL,
+ NULL);
+ }
#endif
- //-----------------------------------------------------------------------------
- //chy 2004-05-25, found the user/system code visit CP 1,2, so I add below code.
- ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL,
- ValMRC, ValMCR, NULL, NULL, NULL, NULL, NULL);
- ARMul_CoProAttach (state, 2, NULL, NULL, ValLDC, ValSTC,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL);
- //------------------------------------------------------------------------------
- /* No handlers below here. */
+ /* No handlers below here. */
- /* Call all the initialisation routines. */
- for (i = 0; i < 16; i++)
- if (state->CPInit[i])
- (state->CPInit[i]) (state);
+ /* Call all the initialisation routines. */
+ for (i = 0; i < 16; i++)
+ if (state->CPInit[i])
+ (state->CPInit[i]) (state);
- return TRUE;
+ return TRUE;
}
/* Install co-processor finalisation routines in this routine. */
void
-ARMul_CoProExit (ARMul_State * state)
+ARMul_CoProExit(ARMul_State * state)
{
- register unsigned i;
+ register unsigned i;
- for (i = 0; i < 16; i++)
- if (state->CPExit[i])
- (state->CPExit[i]) (state);
+ for (i = 0; i < 16; i++)
+ if (state->CPExit[i])
+ (state->CPExit[i]) (state);
- for (i = 0; i < 16; i++) /* Detach all handlers. */
- ARMul_CoProDetach (state, i);
+ for (i = 0; i < 16; i++) /* Detach all handlers. */
+ ARMul_CoProDetach(state, i);
}
/* Routines to hook Co-processors into ARMulator. */
void
-ARMul_CoProAttach (ARMul_State * state,
- unsigned number,
- ARMul_CPInits * init,
- ARMul_CPExits * exit,
- ARMul_LDCs * ldc,
- ARMul_STCs * stc,
- ARMul_MRCs * mrc,
- ARMul_MCRs * mcr,
- ARMul_MRRCs * mrrc,
- ARMul_MCRRs * mcrr,
- ARMul_CDPs * cdp,
- ARMul_CPReads * read, ARMul_CPWrites * write)
+ARMul_CoProAttach(ARMul_State * state,
+unsigned number,
+ARMul_CPInits * init,
+ARMul_CPExits * exit,
+ARMul_LDCs * ldc,
+ARMul_STCs * stc,
+ARMul_MRCs * mrc,
+ARMul_MCRs * mcr,
+ARMul_MRRCs * mrrc,
+ARMul_MCRRs * mcrr,
+ARMul_CDPs * cdp,
+ARMul_CPReads * read, ARMul_CPWrites * write)
{
- if (init != NULL)
- state->CPInit[number] = init;
- if (exit != NULL)
- state->CPExit[number] = exit;
- if (ldc != NULL)
- state->LDC[number] = ldc;
- if (stc != NULL)
- state->STC[number] = stc;
- if (mrc != NULL)
- state->MRC[number] = mrc;
- if (mcr != NULL)
- state->MCR[number] = mcr;
- if (mrrc != NULL)
- state->MRRC[number] = mrrc;
- if (mcrr != NULL)
- state->MCRR[number] = mcrr;
- if (cdp != NULL)
- state->CDP[number] = cdp;
- if (read != NULL)
- state->CPRead[number] = read;
- if (write != NULL)
- state->CPWrite[number] = write;
+ if (init != NULL)
+ state->CPInit[number] = init;
+ if (exit != NULL)
+ state->CPExit[number] = exit;
+ if (ldc != NULL)
+ state->LDC[number] = ldc;
+ if (stc != NULL)
+ state->STC[number] = stc;
+ if (mrc != NULL)
+ state->MRC[number] = mrc;
+ if (mcr != NULL)
+ state->MCR[number] = mcr;
+ if (mrrc != NULL)
+ state->MRRC[number] = mrrc;
+ if (mcrr != NULL)
+ state->MCRR[number] = mcrr;
+ if (cdp != NULL)
+ state->CDP[number] = cdp;
+ if (read != NULL)
+ state->CPRead[number] = read;
+ if (write != NULL)
+ state->CPWrite[number] = write;
}
void
-ARMul_CoProDetach (ARMul_State * state, unsigned number)
+ARMul_CoProDetach(ARMul_State * state, unsigned number)
{
- ARMul_CoProAttach (state, number, NULL, NULL,
- NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
- NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL);
+ ARMul_CoProAttach(state, number, NULL, NULL,
+ NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
+ NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL);
- state->CPInit[number] = NULL;
- state->CPExit[number] = NULL;
- state->CPRead[number] = NULL;
- state->CPWrite[number] = NULL;
-}
-
-//chy 2003-09-03:below funs just replace the old ones
-
-/* Set the XScale FSR and FAR registers. */
-
-void
-XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far)
-{
- //if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
- if (!state->is_XScale)
- return;
- //assume opcode2=0 crm =0
- xscale_cp15_write_reg (state, 5, fsr);
- xscale_cp15_write_reg (state, 6, _far);
-}
-
-//chy 2003-09-03 seems 0 is CANT, 1 is DONE ????
-int
-XScale_debug_moe (ARMul_State * state, int moe)
-{
- //chy 2003-09-03 , W/R CP14 reg, now it's no use ????
- printf ("SKYEYE: XScale_debug_moe called !!!!\n");
- return 1;
+ state->CPInit[number] = NULL;
+ state->CPExit[number] = NULL;
+ state->CPRead[number] = NULL;
+ state->CPWrite[number] = NULL;
}
diff --git a/src/core/arm/interpreter/armmmu.cpp b/src/core/arm/interpreter/armmmu.cpp
deleted file mode 100644
index 98fc17ddb3..0000000000
--- a/src/core/arm/interpreter/armmmu.cpp
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- armmmu.c - Memory Management Unit emulation.
- ARMulator extensions for the ARM7100 family.
- Copyright (C) 1999 Ben Williamson
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <assert.h>
-#include <string.h>
-#include "core/arm/skyeye_common/armdefs.h"
-/* two header for arm disassemble */
-//#include "skyeye_arch.h"
-#include "core/arm/skyeye_common/armcpu.h"
-
-
-extern mmu_ops_t xscale_mmu_ops;
-exception_t arm_mmu_write(short size, u32 addr, uint32_t *value);
-exception_t arm_mmu_read(short size, u32 addr, uint32_t *value);
-#define MMU_OPS (state->mmu.ops)
-ARMword skyeye_cachetype = -1;
-
-int
-mmu_init (ARMul_State * state)
-{
- int ret;
-
- state->mmu.control = 0x70;
- state->mmu.translation_table_base = 0xDEADC0DE;
- state->mmu.domain_access_control = 0xDEADC0DE;
- state->mmu.fault_status = 0;
- state->mmu.fault_address = 0;
- state->mmu.process_id = 0;
-
- switch (state->cpu->cpu_val & state->cpu->cpu_mask) {
- //case SA1100:
- //case SA1110:
- // NOTICE_LOG(ARM11, "SKYEYE: use sa11xx mmu ops\n");
- // state->mmu.ops = sa_mmu_ops;
- // break;
- //case PXA250:
- //case PXA270: //xscale
- // NOTICE_LOG(ARM11, "SKYEYE: use xscale mmu ops\n");
- // state->mmu.ops = xscale_mmu_ops;
- // break;
- //case 0x41807200: //arm720t
- //case 0x41007700: //arm7tdmi
- //case 0x41007100: //arm7100
- // NOTICE_LOG(ARM11, "SKYEYE: use arm7100 mmu ops\n");
- // state->mmu.ops = arm7100_mmu_ops;
- // break;
- //case 0x41009200:
- // NOTICE_LOG(ARM11, "SKYEYE: use arm920t mmu ops\n");
- // state->mmu.ops = arm920t_mmu_ops;
- // break;
- //case 0x41069260:
- // NOTICE_LOG(ARM11, "SKYEYE: use arm926ejs mmu ops\n");
- // state->mmu.ops = arm926ejs_mmu_ops;
- // break;
- /* case 0x560f5810: */
- case 0x0007b000:
- NOTICE_LOG(ARM11, "SKYEYE: use arm11jzf-s mmu ops\n");
- state->mmu.ops = arm1176jzf_s_mmu_ops;
- break;
-
- default:
- ERROR_LOG (ARM11,
- "SKYEYE: armmmu.c : mmu_init: unknown cpu_val&cpu_mask 0x%x\n",
- state->cpu->cpu_val & state->cpu->cpu_mask);
- break;
-
- };
- ret = state->mmu.ops.init (state);
- state->mmu_inited = (ret == 0);
- /* initialize mmu_read and mmu_write for disassemble */
- //skyeye_config_t *config = get_current_config();
- //generic_arch_t *arch_instance = get_arch_instance(config->arch->arch_name);
- //arch_instance->mmu_read = arm_mmu_read;
- //arch_instance->mmu_write = arm_mmu_write;
-
- return ret;
-}
-
-int
-mmu_reset (ARMul_State * state)
-{
- if (state->mmu_inited)
- mmu_exit (state);
- return mmu_init (state);
-}
-
-void
-mmu_exit (ARMul_State * state)
-{
- MMU_OPS.exit (state);
- state->mmu_inited = 0;
-}
-
-fault_t
-mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- return MMU_OPS.read_byte (state, virt_addr, data);
-};
-
-fault_t
-mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- return MMU_OPS.read_halfword (state, virt_addr, data);
-};
-
-fault_t
-mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- return MMU_OPS.read_word (state, virt_addr, data);
-};
-
-fault_t
-mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- fault_t fault;
- //static int count = 0;
- //count ++;
- fault = MMU_OPS.write_byte (state, virt_addr, data);
- return fault;
-}
-
-fault_t
-mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- fault_t fault;
- //static int count = 0;
- //count ++;
- fault = MMU_OPS.write_halfword (state, virt_addr, data);
- return fault;
-}
-
-fault_t
-mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- fault_t fault;
- fault = MMU_OPS.write_word (state, virt_addr, data);
-
- /*used for debug for MMU*
-
- if (!fault){
- ARMword tmp;
-
- if (mmu_read_word(state, virt_addr, &tmp)){
- err_msg("load back\n");
- exit(-1);
- }else{
- if (tmp != data){
- err_msg("load back not equal %d %x\n", count, virt_addr);
- }
- }
- }
- */
-
- return fault;
-};
-
-fault_t
-mmu_load_instr (ARMul_State * state, ARMword virt_addr, ARMword * instr)
-{
- return MMU_OPS.load_instr (state, virt_addr, instr);
-}
-
-ARMword
-mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value)
-{
- return MMU_OPS.mrc (state, instr, value);
-}
-
-void
-mmu_mcr (ARMul_State * state, ARMword instr, ARMword value)
-{
- MMU_OPS.mcr (state, instr, value);
-}
-
-/*ywc 20050416*/
-int
-mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr)
-{
- return (MMU_OPS.v2p_dbct (state, virt_addr, phys_addr));
-}
-
-//
-//
-///* dis_mmu_read for disassemble */
-//exception_t arm_mmu_read(short size, uint32_t addr, uint32_t * value)
-//{
-// ARMul_State *state;
-// ARM_CPU_State *cpu = get_current_cpu();
-// state = &cpu->core[0];
-// switch(size){
-// case 8:
-// MMU_OPS.read_byte (state, addr, value);
-// break;
-// case 16:
-// case 32:
-// break;
-// default:
-// ERROR_LOG(ARM11, "Error size %d", size);
-// break;
-// }
-// return No_exp;
-//}
-///* dis_mmu_write for disassemble */
-//exception_t arm_mmu_write(short size, uint32_t addr, uint32_t *value)
-//{
-// ARMul_State *state;
-// ARM_CPU_State *cpu = get_current_cpu();
-// state = &cpu->core[0];
-// switch(size){
-// case 8:
-// MMU_OPS.write_byte (state, addr, value);
-// break;
-// case 16:
-// case 32:
-// break;
-// default:
-// printf("In %s error size %d Line %d\n", __func__, size, __LINE__);
-// break;
-// }
-// return No_exp;
-//}
diff --git a/src/core/arm/interpreter/armvirt.cpp b/src/core/arm/interpreter/armvirt.cpp
index eb3c86cb43..7845d10425 100644
--- a/src/core/arm/interpreter/armvirt.cpp
+++ b/src/core/arm/interpreter/armvirt.cpp
@@ -24,657 +24,142 @@ freed as they might be needed again. A single area of memory may be
defined to generate aborts. */
#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/skyeye_defs.h"
-//#include "code_cov.h"
+#include "core/arm/skyeye_common/armemu.h"
-#ifdef VALIDATE /* for running the validate suite */
-#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
-#define ABORTS 1
-#endif
+#include "core/mem_map.h"
-/* #define ABORTS */
+#define dumpstack 1
+#define dumpstacksize 0x10
+#define maxdmupaddr 0x0033a850
-#ifdef ABORTS /* the memory system will abort */
-/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
- For the new test suite Abort between 8 Mbytes and 26 Mbytes */
-/* #define LOWABORT 32 * 1024
-#define HIGHABORT 32 * 1024 * 1024 */
-#define LOWABORT 8 * 1024 * 1024
-#define HIGHABORT 26 * 1024 * 1024
+/*ARMword ARMul_GetCPSR (ARMul_State * state) {
+return 0;
+}
+ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode) {
+return 0;
+}
+void ARMul_SetCPSR (ARMul_State * state, ARMword value) {
-#endif
+}
+void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) {
-#define NUMPAGES 64 * 1024
-#define PAGESIZE 64 * 1024
-#define PAGEBITS 16
-#define OFFSETBITS 0xffff
-//chy 2003-08-19: seems no use ????
-int SWI_vector_installed = FALSE;
-extern ARMword skyeye_cachetype;
+}*/
-/***************************************************************************\
-* Get a byte into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-static fault_t
-GetByte (ARMul_State * state, ARMword address, ARMword * data)
-{
- fault_t fault;
-
- fault = mmu_read_byte (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-// printf("SKYEYE: GetByte fault %d \n", fault);
- }
- return fault;
+void ARMul_Icycles(ARMul_State * state, unsigned number, ARMword address) {
}
-/***************************************************************************\
-* Get a halfword into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-static fault_t
-GetHalfWord (ARMul_State * state, ARMword address, ARMword * data)
-{
- fault_t fault;
-
- fault = mmu_read_halfword (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-// printf("SKYEYE: GetHalfWord fault %d \n", fault);
- }
- return fault;
+void ARMul_Ccycles(ARMul_State * state, unsigned number, ARMword address) {
}
-/***************************************************************************\
-* Get a Word from Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-
-static fault_t
-GetWord (ARMul_State * state, ARMword address, ARMword * data)
-{
- fault_t fault;
-
- fault = mmu_read_word (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-#if 0
-/* XXX */ extern int hack;
- hack = 1;
-#endif
-#if 0
- printf ("mmu_read_word at 0x%08x: ", address);
- switch (fault) {
- case ALIGNMENT_FAULT:
- printf ("ALIGNMENT_FAULT");
- break;
- case SECTION_TRANSLATION_FAULT:
- printf ("SECTION_TRANSLATION_FAULT");
- break;
- case PAGE_TRANSLATION_FAULT:
- printf ("PAGE_TRANSLATION_FAULT");
- break;
- case SECTION_DOMAIN_FAULT:
- printf ("SECTION_DOMAIN_FAULT");
- break;
- case SECTION_PERMISSION_FAULT:
- printf ("SECTION_PERMISSION_FAULT");
- break;
- case SUBPAGE_PERMISSION_FAULT:
- printf ("SUBPAGE_PERMISSION_FAULT");
- break;
- default:
- printf ("Unrecognized fault number!");
- }
- printf ("\tpc = 0x%08x\n", state->Reg[15]);
-#endif
- }
- return fault;
-}
-
-//2003-07-10 chy: lyh change
-/****************************************************************************\
- * Load a Instrion Word into Virtual Memory *
-\****************************************************************************/
-static fault_t
-LoadInstr (ARMul_State * state, ARMword address, ARMword * instr)
-{
- fault_t fault;
- fault = mmu_load_instr (state, address, instr);
- return fault;
- //if (fault)
- // log_msg("load_instr fault = %d, address = %x\n", fault, address);
-}
-
-/***************************************************************************\
-* Put a byte into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-static fault_t
-PutByte (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
-
- fault = mmu_write_byte (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-// printf("SKYEYE: PutByte fault %d \n", fault);
- }
- return fault;
-}
-
-/***************************************************************************\
-* Put a halfword into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-static fault_t
-PutHalfWord (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
-
- fault = mmu_write_halfword (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-// printf("SKYEYE: PutHalfWord fault %d \n", fault);
- }
- return fault;
-}
-
-/***************************************************************************\
-* Put a Word into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-
-static fault_t
-PutWord (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
-
- fault = mmu_write_word (state, address, data);
- if (fault) {
-//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
-#if 0
-/* XXX */ extern int hack;
- hack = 1;
-#endif
-#if 0
- printf ("mmu_write_word at 0x%08x: ", address);
- switch (fault) {
- case ALIGNMENT_FAULT:
- printf ("ALIGNMENT_FAULT");
- break;
- case SECTION_TRANSLATION_FAULT:
- printf ("SECTION_TRANSLATION_FAULT");
- break;
- case PAGE_TRANSLATION_FAULT:
- printf ("PAGE_TRANSLATION_FAULT");
- break;
- case SECTION_DOMAIN_FAULT:
- printf ("SECTION_DOMAIN_FAULT");
- break;
- case SECTION_PERMISSION_FAULT:
- printf ("SECTION_PERMISSION_FAULT");
- break;
- case SUBPAGE_PERMISSION_FAULT:
- printf ("SUBPAGE_PERMISSION_FAULT");
- break;
- default:
- printf ("Unrecognized fault number!");
- }
- printf ("\tpc = 0x%08x\n", state->Reg[15]);
-#endif
- }
- return fault;
-}
-
-/***************************************************************************\
-* Initialise the memory interface *
-\***************************************************************************/
-
-unsigned
-ARMul_MemoryInit (ARMul_State * state, unsigned int initmemsize)
-{
- return TRUE;
-}
-
-/***************************************************************************\
-* Remove the memory interface *
-\***************************************************************************/
-
-void
-ARMul_MemoryExit (ARMul_State * state)
-{
-}
-
-/***************************************************************************\
-* ReLoad Instruction *
-\***************************************************************************/
-
-ARMword
-ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
-{
- ARMword data;
- fault_t fault;
-
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT) {
- ARMul_PREFETCHABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
-#endif
-#if 0
- /* do profiling for code coverage */
- if (skyeye_config.code_cov.prof_on)
- cov_prof(EXEC_FLAG, address);
-#endif
-#if 1
- if ((isize == 2) && (address & 0x2)) {
- ARMword lo, hi;
- if (!(skyeye_cachetype == INSTCACHE))
- fault = GetHalfWord (state, address, &lo);
- else
- fault = LoadInstr (state, address, &lo);
-#if 0
- if (!fault) {
- if (!(skyeye_cachetype == INSTCACHE))
- fault = GetHalfWord (state, address + isize, &hi);
- else
- fault = LoadInstr (state, address + isize, &hi);
-
- }
-#endif
- if (fault) {
- ARMul_PREFETCHABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
- return lo;
-#if 0
- if (state->bigendSig == HIGH)
- return (lo << 16) | (hi >> 16);
- else
- return ((hi & 0xFFFF) << 16) | (lo >> 16);
-#endif
- }
-#endif
- if (!(skyeye_cachetype == INSTCACHE))
- fault = GetWord (state, address, &data);
- else
- fault = LoadInstr (state, address, &data);
-
- if (fault) {
-
- /* dyf add for s3c6410 no instcache temporary 2010.9.17 */
- if (!(skyeye_cachetype == INSTCACHE)) {
- /* set translation fault on prefetch abort */
- state->mmu.fault_statusi = fault & 0xFF;
- state->mmu.fault_address = address;
- }
- /* add end */
-
- ARMul_PREFETCHABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
-
- return data;
-}
-
-/***************************************************************************\
-* Load Instruction, Sequential Cycle *
-\***************************************************************************/
-
-ARMword
-ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
-{
- state->NumScycles++;
+ARMword ARMul_LoadInstrS(ARMul_State * state, ARMword address, ARMword isize) {
+ state->NumScycles++;
#ifdef HOURGLASS
- if ((state->NumScycles & HOURGLASS_RATE) == 0) {
- HOURGLASS;
- }
+ if ((state->NumScycles & HOURGLASS_RATE) == 0) {
+ HOURGLASS;
+ }
#endif
-
- return ARMul_ReLoadInstr (state, address, isize);
+ if (isize == 2)
+ return (u16)Memory::Read16(address);
+ else
+ return (u32)Memory::Read32(address);
}
-/***************************************************************************\
-* Load Instruction, Non Sequential Cycle *
-\***************************************************************************/
+ARMword ARMul_LoadInstrN(ARMul_State * state, ARMword address, ARMword isize) {
+ state->NumNcycles++;
-ARMword
-ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
+ if (isize == 2)
+ return (u16)Memory::Read16(address);
+ else
+ return (u32)Memory::Read32(address);
+}
+
+ARMword ARMul_ReLoadInstr(ARMul_State * state, ARMword address, ARMword isize) {
+ ARMword data;
+
+ if ((isize == 2) && (address & 0x2)) {
+ ARMword lo;
+ lo = (u16)Memory::Read16(address);
+ return lo;
+ }
+
+ data = (u32)Memory::Read32(address);
+ return data;
+}
+
+ARMword ARMul_ReadWord(ARMul_State * state, ARMword address) {
+ ARMword data;
+ data = Memory::Read32(address);
+ return data;
+}
+
+ARMword ARMul_LoadWordS(ARMul_State * state, ARMword address) {
+ state->NumScycles++;
+ return ARMul_ReadWord(state, address);
+}
+
+ARMword ARMul_LoadWordN(ARMul_State * state, ARMword address) {
+ state->NumNcycles++;
+ return ARMul_ReadWord(state, address);
+}
+
+ARMword ARMul_LoadHalfWord(ARMul_State * state, ARMword address) {
+ state->NumNcycles++;
+ return (u16)Memory::Read16(address);;
+}
+
+ARMword ARMul_ReadByte(ARMul_State * state, ARMword address) {
+ return (u8)Memory::Read8(address);
+}
+
+ARMword ARMul_LoadByte(ARMul_State * state, ARMword address) {
+ state->NumNcycles++;
+ return ARMul_ReadByte(state, address);
+}
+
+void ARMul_StoreHalfWord(ARMul_State * state, ARMword address, ARMword data) {
+ state->NumNcycles++;
+ Memory::Write16(address, data);
+}
+
+void ARMul_StoreByte(ARMul_State * state, ARMword address, ARMword data) {
+ state->NumNcycles++;
+ ARMul_WriteByte(state, address, data);
+}
+
+ARMword ARMul_SwapWord(ARMul_State * state, ARMword address, ARMword data) {
+ ARMword temp;
+ state->NumNcycles++;
+ temp = ARMul_ReadWord(state, address);
+ state->NumNcycles++;
+ Memory::Write32(address, data);
+ return temp;
+}
+
+ARMword ARMul_SwapByte(ARMul_State * state, ARMword address, ARMword data) {
+ ARMword temp;
+ temp = ARMul_LoadByte(state, address);
+ Memory::Write8(address, data);
+ return temp;
+}
+
+void ARMul_WriteWord(ARMul_State * state, ARMword address, ARMword data) {
+ Memory::Write32(address, data);
+}
+
+void ARMul_WriteByte(ARMul_State * state, ARMword address, ARMword data)
{
- state->NumNcycles++;
-
- return ARMul_ReLoadInstr (state, address, isize);
+ Memory::Write8(address, data);
}
-/***************************************************************************\
-* Read Word (but don't tell anyone!) *
-\***************************************************************************/
-
-ARMword
-ARMul_ReadWord (ARMul_State * state, ARMword address)
+void ARMul_StoreWordS(ARMul_State * state, ARMword address, ARMword data)
{
- ARMword data;
- fault_t fault;
-
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT) {
- ARMul_DATAABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
-#endif
-
- fault = GetWord (state, address, &data);
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
- return data;
+ state->NumScycles++;
+ ARMul_WriteWord(state, address, data);
}
-/***************************************************************************\
-* Load Word, Sequential Cycle *
-\***************************************************************************/
-
-ARMword
-ARMul_LoadWordS (ARMul_State * state, ARMword address)
+void ARMul_StoreWordN(ARMul_State * state, ARMword address, ARMword data)
{
- state->NumScycles++;
-
- return ARMul_ReadWord (state, address);
-}
-
-/***************************************************************************\
-* Load Word, Non Sequential Cycle *
-\***************************************************************************/
-
-ARMword
-ARMul_LoadWordN (ARMul_State * state, ARMword address)
-{
- state->NumNcycles++;
-
- return ARMul_ReadWord (state, address);
-}
-
-/***************************************************************************\
-* Load Halfword, (Non Sequential Cycle) *
-\***************************************************************************/
-
-ARMword
-ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
-{
- ARMword data;
- fault_t fault;
-
- state->NumNcycles++;
- fault = GetHalfWord (state, address, &data);
-
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
-
- return data;
-
-}
-
-/***************************************************************************\
-* Read Byte (but don't tell anyone!) *
-\***************************************************************************/
-int ARMul_ICE_ReadByte(ARMul_State * state, ARMword address, ARMword *presult)
-{
- ARMword data;
- fault_t fault;
- fault = GetByte (state, address, &data);
- if (fault) {
- *presult=-1; fault=ALIGNMENT_FAULT; return fault;
- }else{
- *(char *)presult=(unsigned char)(data & 0xff); fault=NO_FAULT; return fault;
- }
-}
-
-
-ARMword
-ARMul_ReadByte (ARMul_State * state, ARMword address)
-{
- ARMword data;
- fault_t fault;
-
- fault = GetByte (state, address, &data);
-
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return ARMul_ABORTWORD;
- }
- else {
- ARMul_CLEARABORT;
- }
-
- return data;
-
-}
-
-/***************************************************************************\
-* Load Byte, (Non Sequential Cycle) *
-\***************************************************************************/
-
-ARMword
-ARMul_LoadByte (ARMul_State * state, ARMword address)
-{
- state->NumNcycles++;
-
- return ARMul_ReadByte (state, address);
-}
-
-/***************************************************************************\
-* Write Word (but don't tell anyone!) *
-\***************************************************************************/
-
-void
-ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
-
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT) {
- ARMul_DATAABORT (address);
- return;
- }
- else {
- ARMul_CLEARABORT;
- }
-#endif
-
- fault = PutWord (state, address, data);
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return;
- }
- else {
- ARMul_CLEARABORT;
- }
-}
-
-/***************************************************************************\
-* Store Word, Sequential Cycle *
-\***************************************************************************/
-
-void
-ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumScycles++;
-
- ARMul_WriteWord (state, address, data);
-}
-
-/***************************************************************************\
-* Store Word, Non Sequential Cycle *
-\***************************************************************************/
-
-void
-ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumNcycles++;
-
- ARMul_WriteWord (state, address, data);
-}
-
-/***************************************************************************\
-* Store HalfWord, (Non Sequential Cycle) *
-\***************************************************************************/
-
-void
-ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
- state->NumNcycles++;
- fault = PutHalfWord (state, address, data);
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return;
- }
- else {
- ARMul_CLEARABORT;
- }
-}
-
-//chy 2006-04-15
-int ARMul_ICE_WriteByte (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
- fault = PutByte (state, address, data);
- if (fault)
- return 1;
- else
- return 0;
-}
-/***************************************************************************\
-* Write Byte (but don't tell anyone!) *
-\***************************************************************************/
-//chy 2003-07-10, add real write byte fun
-void
-ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
-{
- fault_t fault;
- fault = PutByte (state, address, data);
- if (fault) {
- state->mmu.fault_status =
- (fault | (state->mmu.last_domain << 4)) & 0xFF;
- state->mmu.fault_address = address;
- ARMul_DATAABORT (address);
- return;
- }
- else {
- ARMul_CLEARABORT;
- }
-}
-
-/***************************************************************************\
-* Store Byte, (Non Sequential Cycle) *
-\***************************************************************************/
-
-void
-ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumNcycles++;
-
-#ifdef VALIDATE
- if (address == TUBE) {
- if (data == 4)
- state->Emulate = FALSE;
- else
- (void) putc ((char) data, stderr); /* Write Char */
- return;
- }
-#endif
-
- ARMul_WriteByte (state, address, data);
-}
-
-/***************************************************************************\
-* Swap Word, (Two Non Sequential Cycles) *
-\***************************************************************************/
-
-ARMword
-ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp;
-
- state->NumNcycles++;
-
- temp = ARMul_ReadWord (state, address);
-
- state->NumNcycles++;
-
- PutWord (state, address, data);
-
- return temp;
-}
-
-/***************************************************************************\
-* Swap Byte, (Two Non Sequential Cycles) *
-\***************************************************************************/
-
-ARMword
-ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp;
-
- temp = ARMul_LoadByte (state, address);
- ARMul_StoreByte (state, address, data);
-
- return temp;
-}
-
-/***************************************************************************\
-* Count I Cycles *
-\***************************************************************************/
-
-void
-ARMul_Icycles (ARMul_State * state, unsigned number,
- ARMword address)
-{
- state->NumIcycles += number;
- ARMul_CLEARABORT;
-}
-
-/***************************************************************************\
-* Count C Cycles *
-\***************************************************************************/
-
-void
-ARMul_Ccycles (ARMul_State * state, unsigned number,
- ARMword address)
-{
- state->NumCcycles += number;
- ARMul_CLEARABORT;
+ state->NumNcycles++;
+ ARMul_WriteWord(state, address, data);
}
diff --git a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp b/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
deleted file mode 100644
index 07951e0e6c..0000000000
--- a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.cpp
+++ /dev/null
@@ -1,1132 +0,0 @@
-/*
- arm1176jzf_s_mmu.c - ARM920T Memory Management Unit emulation.
- Copyright (C) 2003 Skyeye Develop Group
- for help please send mail to <skyeye-developer@lists.gro.clinux.org>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <assert.h>
-#include <string.h>
-#include <stdint.h>
-
-#include "core/mem_map.h"
-
-#include "core/arm/skyeye_common/skyeye_defs.h"
-
-#include "core/arm/skyeye_common/armdefs.h"
-//#include "bank_defs.h"
-#if 0
-#define TLB_SIZE 1024 * 1024
-#define ASID 255
-static uint32_t tlb_entry_array[TLB_SIZE][ASID];
-static inline void invalidate_all_tlb(ARMul_State *state){
- memset(&tlb_entry_array[0], 0xFF, sizeof(uint32_t) * TLB_SIZE * ASID);
-}
-static inline void invalidate_by_mva(ARMul_State *state, ARMword va){
- memset(&tlb_entry_array[va >> 12][va & 0xFF], 0xFF, sizeof(uint32_t));
- return;
-}
-static inline void invalidate_by_asid(ARMul_State *state, ARMword asid){
- int i;
- for(i = 0; i < TLB_SIZE; i++)
- memset(&tlb_entry_array[i][asid & 0xFF], 0xFF, sizeof(uint32_t));
- return;
-}
-
-static uint32_t get_phys_page(ARMul_State* state, ARMword va){
- uint32_t phys_page = tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF];
- //printf("In %s, for va=0x%x, page=0x%x\n", __func__, va, phys_page);
- return phys_page;
-}
-
-static inline void insert_tlb(ARMul_State* state, ARMword va, ARMword pa){
- //printf("In %s, insert va=0x%x, pa=0x%x\n", __FUNCTION__, va, pa);
- //printf("In %s, insert va=0x%x, va>>12=0x%x, pa=0x%x, pa>>12=0x%x\n", __FUNCTION__, va, va >> 12, pa, pa >> 12);
- tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF] = pa >> 12;
-
- return;
-}
-#endif
-#define BANK0_START 0x50000000
-static void* mem_ptr = NULL;
-
-static int exclusive_detect(ARMul_State* state, ARMword addr){
- #if 0
- for(int i = 0; i < 128; i++){
- if(state->exclusive_tag_array[i] == addr)
- return 0;
- }
- #endif
- if(state->exclusive_tag_array[0] == addr)
- return 0;
- else
- return -1;
-}
-
-static void add_exclusive_addr(ARMul_State* state, ARMword addr){
- #if 0
- for(int i = 0; i < 128; i++){
- if(state->exclusive_tag_array[i] == 0xffffffff){
- state->exclusive_tag_array[i] = addr;
- //printf("In %s, add addr 0x%x\n", __func__, addr);
- return;
- }
- }
- printf("In %s ,can not monitor the addr, out of array\n", __FUNCTION__);
- #endif
- state->exclusive_tag_array[0] = addr;
- return;
-}
-
-static void remove_exclusive(ARMul_State* state, ARMword addr){
- #if 0
- int i;
- for(i = 0; i < 128; i++){
- if(state->exclusive_tag_array[i] == addr){
- state->exclusive_tag_array[i] = 0xffffffff;
- //printf("In %s, remove addr 0x%x\n", __func__, addr);
- return;
- }
- }
- #endif
- state->exclusive_tag_array[0] = 0xFFFFFFFF;
-}
-
-/* This function encodes table 8-2 Interpreting AP bits,
- returning non-zero if access is allowed. */
-static int
-check_perms (ARMul_State *state, int ap, int read)
-{
- int s, r, user;
-
- s = state->mmu.control & CONTROL_SYSTEM;
- r = state->mmu.control & CONTROL_ROM;
- /* chy 2006-02-15 , should consider system mode, don't conside 26bit mode */
-// printf("ap is %x, user is %x, s is %x, read is %x\n", ap, user, s, read);
-// printf("mode is %x\n", state->Mode);
- user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE);
-
- switch (ap) {
- case 0:
- return read && ((s && !user) || r);
- case 1:
- return !user;
- case 2:
- return read || !user;
- case 3:
- return 1;
- }
- return 0;
-}
-
-#if 0
-fault_t
-check_access (ARMul_State *state, ARMword virt_addr, tlb_entry_t *tlb,
- int read)
-{
- int access;
-
- state->mmu.last_domain = tlb->domain;
- access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3;
- if ((access == 0) || (access == 2)) {
- /* It's unclear from the documentation whether this
- should always raise a section domain fault, or if
- it should be a page domain fault in the case of an
- L1 that describes a page table. In the ARM710T
- datasheets, "Figure 8-9: Sequence for checking faults"
- seems to indicate the former, while "Table 8-4: Priority
- encoding of fault status" gives a value for FS[3210] in
- the event of a domain fault for a page. Hmm. */
- return SECTION_DOMAIN_FAULT;
- }
- if (access == 1) {
- /* client access - check perms */
- int subpage, ap;
-#if 0
- switch (tlb->mapping) {
- /*ks 2004-05-09
- * only for XScale
- * Extend Small Page(ESP) Format
- * 31-12 bits the base addr of ESP
- * 11-10 bits SBZ
- * 9-6 bits TEX
- * 5-4 bits AP
- * 3 bit C
- * 2 bit B
- * 1-0 bits 11
- * */
- case TLB_ESMALLPAGE: /* xj */
- subpage = 0;
- /* printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr ); */
- break;
-
- case TLB_TINYPAGE:
- subpage = 0;
- /* printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr ); */
- break;
-
- case TLB_SMALLPAGE:
- subpage = (virt_addr >> 10) & 3;
- break;
- case TLB_LARGEPAGE:
- subpage = (virt_addr >> 14) & 3;
- break;
- case TLB_SECTION:
- subpage = 3;
- break;
- default:
- assert (0);
- subpage = 0; /* cleans a warning */
- }
- ap = (tlb->perms >> (subpage * 2 + 4)) & 3;
- if (!check_perms (state, ap, read)) {
- if (tlb->mapping == TLB_SECTION) {
- return SECTION_PERMISSION_FAULT;
- } else {
- return SUBPAGE_PERMISSION_FAULT;
- }
- }
-#endif
- } else { /* access == 3 */
- /* manager access - don't check perms */
- }
- return NO_FAULT;
-}
-#endif
-
-#if 0
-fault_t
-mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr)
-#endif
-
-/* ap: AP bits value.
- * sop: section or page description 0:section 1:page
- */
-fault_t
-mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *ap, int *sop)
-{
- {
- /* walk the translation tables */
- ARMword l1addr, l1desc;
- if (state->mmu.translation_table_ctrl && virt_addr << state->mmu.translation_table_ctrl >> (32 - state->mmu.translation_table_ctrl - 1)) {
- l1addr = state->mmu.translation_table_base1;
- l1addr = (((l1addr >> 14) << 14) | (virt_addr >> 18)) & ~3;
- } else {
- l1addr = state->mmu.translation_table_base0;
- l1addr = (((l1addr >> (14 - state->mmu.translation_table_ctrl)) << (14 - state->mmu.translation_table_ctrl)) | (virt_addr << state->mmu.translation_table_ctrl) >> (18 + state->mmu.translation_table_ctrl)) & ~3;
- }
-
- /* l1desc = mem_read_word (state, l1addr); */
- if (state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, l1addr, &l1desc, 4);
- else
- l1desc = Memory::Read32(l1addr); //mem_read_raw(32, l1addr, &l1desc);
-
- #if 0
- if (virt_addr == 0xc000d2bc) {
- printf("mmu_control is %x\n", state->mmu.translation_table_ctrl);
- printf("mmu_table_0 is %x\n", state->mmu.translation_table_base0);
- printf("mmu_table_1 is %x\n", state->mmu.translation_table_base1);
- printf("l1addr is %x l1desc is %x\n", l1addr, l1desc);
- // exit(-1);
- }
- #endif
- switch (l1desc & 3) {
- case 0:
- case 3:
- /*
- * according to Figure 3-9 Sequence for checking faults in arm manual,
- * section translation fault should be returned here.
- */
- {
- return SECTION_TRANSLATION_FAULT;
- }
- case 1:
- /* coarse page table */
- {
- ARMword l2addr, l2desc;
-
-
- l2addr = l1desc & 0xFFFFFC00;
- l2addr = (l2addr |
- ((virt_addr & 0x000FF000) >> 10)) &
- ~3;
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, l2addr, &l2desc, 4);
- else
- l2desc = Memory::Read32(l2addr); //mem_read_raw(32, l2addr, &l2desc);
-
- /* chy 2003-09-02 for xscale */
- *ap = (l2desc >> 4) & 0x3;
- *sop = 1; /* page */
-
- switch (l2desc & 3) {
- case 0:
- return PAGE_TRANSLATION_FAULT;
- break;
- case 1:
- *phys_addr = (l2desc & 0xFFFF0000) | (virt_addr & 0x0000FFFF);
- break;
- case 2:
- case 3:
- *phys_addr = (l2desc & 0xFFFFF000) | (virt_addr & 0x00000FFF);
- break;
-
- }
- }
- break;
- case 2:
- /* section */
-
- *ap = (l1desc >> 10) & 3;
- *sop = 0; /* section */
- #if 0
- if (virt_addr == 0xc000d2bc) {
- printf("mmu_control is %x\n", state->mmu.translation_table_ctrl);
- printf("mmu_table_0 is %x\n", state->mmu.translation_table_base0);
- printf("mmu_table_1 is %x\n", state->mmu.translation_table_base1);
- printf("l1addr is %x l1desc is %x\n", l1addr, l1desc);
-// printf("l2addr is %x l2desc is %x\n", l2addr, l2desc);
- printf("ap is %x, sop is %x\n", *ap, *sop);
- printf("mode is %d\n", state->Mode);
-// exit(-1);
- }
- #endif
-
- if (l1desc & 0x30000)
- *phys_addr = (l1desc & 0xFF000000) | (virt_addr & 0x00FFFFFF);
- else
- *phys_addr = (l1desc & 0xFFF00000) | (virt_addr & 0x000FFFFF);
- break;
- }
- }
- return NO_FAULT;
-}
-
-
-static fault_t arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va,
- ARMword data, ARMword datatype);
-static fault_t arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va,
- ARMword *data, ARMword datatype);
-
-int
-arm1176jzf_s_mmu_init (ARMul_State *state)
-{
- state->mmu.control = 0x50078;
- state->mmu.translation_table_base = 0xDEADC0DE;
- state->mmu.domain_access_control = 0xDEADC0DE;
- state->mmu.fault_status = 0;
- state->mmu.fault_address = 0;
- state->mmu.process_id = 0;
- state->mmu.context_id = 0;
- state->mmu.thread_uro_id = 0;
- //invalidate_all_tlb(state);
-
- return No_exp;
-}
-
-void
-arm1176jzf_s_mmu_exit (ARMul_State *state)
-{
-}
-
-
-static fault_t
-arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
-{
- fault_t fault;
- int c; /* cache bit */
- ARMword pa; /* physical addr */
- ARMword perm; /* physical addr access permissions */
- int ap, sop;
-
- static int debug_count = 0; /* used for debug */
-
- //DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- if (MMU_Enabled) {
-// printf("MMU enabled.\n");
-// sleep(1);
- /* align check */
- if ((va & (WORD_SIZE - 1)) && MMU_Aligned) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- } else
- va &= ~(WORD_SIZE - 1);
-
- /* translate tlb */
- fault = mmu_translate (state, va, &pa, &ap, &sop);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault);
- return fault;
- }
-
-
- /* no tlb, only check permission */
- if (!check_perms(state, ap, 1)) {
- if (sop == 0) {
- return SECTION_PERMISSION_FAULT;
- } else {
- return SUBPAGE_PERMISSION_FAULT;
- }
- }
-
-#if 0
- /*check access */
- fault = check_access (state, va, tlb, 1);
- if (fault) {
- DEBUG_LOG(ARM11, "check_fault\n");
- return fault;
- }
-#endif
- }
-
- /*if MMU disabled or C flag is set alloc cache */
- if (MMU_Disabled) {
-// printf("MMU disabled.\n");
-// sleep(1);
- pa = va;
- }
- if(state->space.conf_obj == NULL)
- state->space.read(state->space.conf_obj, pa, instr, 4);
- else
- *instr = Memory::Read32(pa); //mem_read_raw(32, pa, instr);
-
- return NO_FAULT;
-}
-
-static fault_t
-arm1176jzf_s_mmu_read_byte (ARMul_State *state, ARMword virt_addr, ARMword *data)
-{
- /* ARMword temp,offset; */
- fault_t fault;
- fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE);
- return fault;
-}
-
-static fault_t
-arm1176jzf_s_mmu_read_halfword (ARMul_State *state, ARMword virt_addr,
- ARMword *data)
-{
- /* ARMword temp,offset; */
- fault_t fault;
- fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE);
- return fault;
-}
-
-static fault_t
-arm1176jzf_s_mmu_read_word (ARMul_State *state, ARMword virt_addr, ARMword *data)
-{
- return arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-static fault_t
-arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
- ARMword datatype)
-{
- fault_t fault;
- ARMword pa, real_va, temp, offset;
- ARMword perm; /* physical addr access permissions */
- int ap, sop;
-
- //DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- real_va = va;
- /* if MMU disabled, memory_read */
- if (MMU_Disabled) {
-// printf("MMU disabled cpu_id:%x addr:%x.\n", state->mmu.process_id, va);
-// sleep(1);
-
- /* *data = mem_read_word(state, va); */
- if (datatype == ARM_BYTE_TYPE)
- /* *data = mem_read_byte (state, va); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, va, data, 1);
- else
- *data = Memory::Read8(va); //mem_read_raw(8, va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- /* *data = mem_read_halfword (state, va); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, va, data, 2);
- else
- *data = Memory::Read16(va); //mem_read_raw(16, va, data);
- else if (datatype == ARM_WORD_TYPE)
- /* *data = mem_read_word (state, va); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, va, data, 4);
- else
- *data = Memory::Read32(va); //mem_read_raw(32, va, data);
- else {
- ERROR_LOG(ARM11, "SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
- }
-
- return NO_FAULT;
- }
-// printf("MMU enabled.\n");
-// sleep(1);
-
- /* align check */
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
-
- /* va &= ~(WORD_SIZE - 1); */
- #if 0
- uint32_t page_base;
- page_base = get_phys_page(state, va);
- if((page_base & 0xFFF) == 0){
- pa = (page_base << 12) | (va & 0xFFF);
- goto skip_translation;
- }
- #endif
- /*translate va to tlb */
-#if 0
- fault = mmu_translate (state, va, ARM920T_D_TLB (), &tlb);
-#endif
- fault = mmu_translate (state, va, &pa, &ap, &sop);
-#if 0
- if(va ==0xbebb1774 || state->Reg[15] == 0x400ff594){
- //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]);
- printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data);
- int i;
- for(i = 0; i < 16; i++)
- printf("Reg[%d]=0x%x\t", i, state->Reg[i]);
- printf("\n");
- }
-#endif
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- //printf("mmu read fault at %x\n", va);
- //printf("fault is %d\n", fault);
- return fault;
- }
-// printf("va is %x pa is %x\n", va, pa);
-
- /* no tlb, only check permission */
- if (!check_perms(state, ap, 1)) {
- if (sop == 0) {
- return SECTION_PERMISSION_FAULT;
- } else {
- return SUBPAGE_PERMISSION_FAULT;
- }
- }
-#if 0
- /*check access permission */
- fault = check_access (state, va, tlb, 1);
- if (fault)
- return fault;
-#endif
-
- //insert_tlb(state, va, pa);
-skip_translation:
- /* *data = mem_read_word(state, pa); */
- if (datatype == ARM_BYTE_TYPE) {
- /* *data = mem_read_byte (state, pa | (real_va & 3)); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1);
- else
- *data = Memory::Read8(pa | (real_va & 3)); //mem_read_raw(8, pa | (real_va & 3), data);
- /* mem_read_raw(32, pa | (real_va & 3), data); */
- } else if (datatype == ARM_HALFWORD_TYPE) {
- /* *data = mem_read_halfword (state, pa | (real_va & 2)); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2);
- else
- *data = Memory::Read16(pa | (real_va & 3)); //mem_read_raw(16, pa | (real_va & 3), data);
- /* mem_read_raw(32, pa | (real_va & 2), data); */
- } else if (datatype == ARM_WORD_TYPE)
- /* *data = mem_read_word (state, pa); */
- if(state->space.conf_obj != NULL)
- state->space.read(state->space.conf_obj, pa , data, 4);
- else
- *data = Memory::Read32(pa); //mem_read_raw(32, pa, data);
- else {
- ERROR_LOG(ARM11, "SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
- }
- if(0 && (va == 0x2869c)){
- printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr);
- }
-
- /* ldrex or ldrexb */
- if(((state->CurrInstr & 0x0FF000F0) == 0x01900090) ||
- ((state->CurrInstr & 0x0FF000F0) == 0x01d00090)){
- int rn = (state->CurrInstr & 0xF0000) >> 16;
- if(state->Reg[rn] == va){
- add_exclusive_addr(state, pa | (real_va & 3));
- state->exclusive_access_state = 1;
- }
- }
-#if 0
- if (state->pc == 0xc011a868) {
- printf("pa is %x value is %x size is %x\n", pa, data, datatype);
- printf("icounter is %lld\n", state->NumInstrs);
-// exit(-1);
- }
-#endif
-
- return NO_FAULT;
-}
-
-
-static fault_t
-arm1176jzf_s_mmu_write_byte (ARMul_State *state, ARMword virt_addr, ARMword data)
-{
- return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE);
-}
-
-static fault_t
-arm1176jzf_s_mmu_write_halfword (ARMul_State *state, ARMword virt_addr,
- ARMword data)
-{
- return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE);
-}
-
-static fault_t
-arm1176jzf_s_mmu_write_word (ARMul_State *state, ARMword virt_addr, ARMword data)
-{
- return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-
-
-static fault_t
-arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
- ARMword datatype)
-{
- int b;
- ARMword pa, real_va;
- ARMword perm; /* physical addr access permissions */
- fault_t fault;
- int ap, sop;
-
-#if 0
- /8 for sky_printk debugger.*/
- if (va == 0xffffffff) {
- putchar((char)data);
- return 0;
- }
- if (va == 0xBfffffff) {
- putchar((char)data);
- return 0;
- }
-#endif
-
- //DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data);
- va = mmu_pid_va_map (va);
- real_va = va;
-
- if (MMU_Disabled) {
- /* mem_write_word(state, va, data); */
- if (datatype == ARM_BYTE_TYPE)
- /* mem_write_byte (state, va, data); */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, va, &data, 1);
- else
- Memory::Write8(va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- /* mem_write_halfword (state, va, data); */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, va, &data, 2);
- else
- Memory::Write16(va, data);
- else if (datatype == ARM_WORD_TYPE)
- /* mem_write_word (state, va, data); */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, va, &data, 4);
- else
- Memory::Write32(va, data);
- else {
- ERROR_LOG (ARM11, "SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype);
- }
- goto finished_write;
- //return 0;
- }
- /*align check */
- /* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
- va &= ~(WORD_SIZE - 1);
- #if 0
- uint32_t page_base;
- page_base = get_phys_page(state, va);
- if((page_base & 0xFFF) == 0){
- pa = (page_base << 12) | (va & 0xFFF);
- goto skip_translation;
- }
- #endif
- /*tlb translate */
- fault = mmu_translate (state, va, &pa, &ap, &sop);
-#if 0
- if(va ==0xbebb1774 || state->Reg[15] == 0x40102334){
- //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]);
- printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data);
- int i;
- for(i = 0; i < 16; i++)
- printf("Reg[%d]=0x%x\t", i, state->Reg[i]);
- printf("\n");
- }
-#endif
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- //printf("mmu write fault at %x\n", va);
- return fault;
- }
-// printf("va is %x pa is %x\n", va, pa);
-
- /* no tlb, only check permission */
- if (!check_perms(state, ap, 0)) {
- if (sop == 0) {
- return SECTION_PERMISSION_FAULT;
- } else {
- return SUBPAGE_PERMISSION_FAULT;
- }
- }
-
-#if 0
- /* tlb check access */
- fault = check_access (state, va, tlb, 0);
- if (fault) {
- DEBUG_LOG(ARM11, "check_access\n");
- return fault;
- }
-#endif
-#if 0
- if (pa <= 0x502860ff && (pa + 1 << datatype) > 0x502860ff) {
- printf("pa is %x value is %x size is %x\n", pa, data, datatype);
- }
-#endif
-#if 0
- if (state->pc == 0xc011a878) {
- printf("write pa is %x value is %x size is %x\n", pa, data, datatype);
- printf("icounter is %lld\n", state->NumInstrs);
- exit(-1);
- }
-#endif
- //insert_tlb(state, va, pa);
-skip_translation:
- /* strex */
- if(((state->CurrInstr & 0x0FF000F0) == 0x01800090) ||
- ((state->CurrInstr & 0x0FF000F0) == 0x01c00090)){
- /* failed , the address is monitord now. */
- int dest_reg = (state->CurrInstr & 0xF000) >> 12;
- if((exclusive_detect(state, pa | (real_va & 3)) == 0) && (state->exclusive_access_state == 1)){
- remove_exclusive(state, pa | (real_va & 3));
- state->Reg[dest_reg] = 0;
- state->exclusive_access_state = 0;
- }
- else{
- state->Reg[dest_reg] = 1;
- //printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa);
- return NO_FAULT;
- }
- }
-
- if (datatype == ARM_BYTE_TYPE) {
- /* mem_write_byte (state,
- (pa | (real_va & 3)),
- data);
- */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1);
- else
- Memory::Write8((pa | (real_va & 3)), data);
-
- } else if (datatype == ARM_HALFWORD_TYPE)
- /* mem_write_halfword (state,
- (pa |
- (real_va & 2)),
- data);
- */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2);
- else
- Memory::Write16((pa | (real_va & 3)), data);
- else if (datatype == ARM_WORD_TYPE)
- /* mem_write_word (state, pa, data); */
- if(state->space.conf_obj != NULL)
- state->space.write(state->space.conf_obj, pa, &data, 4);
- else
- Memory::Write32(pa, data);
-#if 0
- if (state->NumInstrs > 236403) {
- printf("write memory\n");
- printf("pa is %x value is %x size is %x\n", pa, data, datatype);
- printf("icounter is %lld\n", state->NumInstrs);
- }
-#endif
-finished_write:
-#if DIFF_WRITE
- if(state->icounter > state->debug_icounter){
- if(state->CurrWrite >= 17 ){
- printf("Wrong write array, 0x%x", state->CurrWrite);
- exit(-1);
- }
- uint32 record_data = data;
- if(datatype == ARM_BYTE_TYPE)
- record_data &= 0xFF;
- if(datatype == ARM_HALFWORD_TYPE)
- record_data &= 0xFFFF;
-
- state->WriteAddr[state->CurrWrite] = pa | (real_va & 3);
- state->WriteData[state->CurrWrite] = record_data;
- state->WritePc[state->CurrWrite] = state->Reg[15];
- state->CurrWrite++;
- //printf("In %s, pc=0x%x, addr=0x%x, data=0x%x, CFlag=%d\n", __FUNCTION__, state->Reg[15], pa | (real_va & 3), record_data, state->CFlag);
- }
-#endif
-
- return NO_FAULT;
-}
-
-ARMword
-arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value)
-{
- int creg = BITS (16, 19) & 0xf;
- int OPC_1 = BITS (21, 23) & 0x7;
- int OPC_2 = BITS (5, 7) & 0x7;
- ARMword data;
-
- switch (creg) {
- case MMU_ID:
- if (OPC_2 == 0) {
- data = state->cpu->cpu_val;
- } else if (OPC_2 == 1) {
- /* Cache type:
- * 000 0110 1 000 101 110 0 10 000 101 110 0 10
- * */
- data = 0x0D172172;
- }
- break;
- case MMU_CONTROL:
- /*
- * 6:3 read as 1
- * 10 read as 0
- * 18,16 read as 1
- * */
- data = (state->mmu.control | 0x50078) & 0xFFFFFBFF;
- break;
- case MMU_TRANSLATION_TABLE_BASE:
-#if 0
- data = state->mmu.translation_table_base;
-#endif
- switch (OPC_2) {
- case 0:
- data = state->mmu.translation_table_base0;
- break;
- case 1:
- data = state->mmu.translation_table_base1;
- break;
- case 2:
- data = state->mmu.translation_table_ctrl;
- break;
- default:
- printf ("mmu_mrc read UNKNOWN - p15 c2 opcode2 %d\n", OPC_2);
- break;
- }
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
- data = state->mmu.domain_access_control;
- break;
- case MMU_FAULT_STATUS:
- /* OPC_2 = 0: data FSR value
- * */
- if (OPC_2 == 0)
- data = state->mmu.fault_status;
- if (OPC_2 == 1)
- data = state->mmu.fault_statusi;
- break;
- case MMU_FAULT_ADDRESS:
- data = state->mmu.fault_address;
- break;
- case MMU_PID:
- //data = state->mmu.process_id;
- if(OPC_2 == 0)
- data = state->mmu.process_id;
- else if(OPC_2 == 1)
- data = state->mmu.context_id;
- else if(OPC_2 == 3){
- data = state->mmu.thread_uro_id;
- }
- else{
- printf ("mmu_mcr read UNKNOWN - reg %d\n", creg);
- }
- //printf("SKYEYE In %s, read pid 0x%x, OPC_2 %d, instr=0x%x\n", __FUNCTION__, data, OPC_2, instr);
- //exit(-1);
- break;
- default:
- printf ("mmu_mrc read UNKNOWN - reg %d\n", creg);
- data = 0;
- break;
- }
-/* printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); */
- *value = data;
- return data;
-}
-
-
-static ARMword
-arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value)
-{
- int creg = BITS (16, 19) & 0xf;
- int CRm = BITS (0, 3) & 0xf;
- int OPC_1 = BITS (21, 23) & 0x7;
- int OPC_2 = BITS (5, 7) & 0x7;
- if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) {
- switch (creg) {
- case MMU_CONTROL:
- /*
- * 6:3 read as 1
- * 10 read as 0
- * 18,16 read as 1
- * */
- if(OPC_2 == 0)
- state->mmu.control = (value | 0x50078) & 0xFFFFFBFF;
- else if(OPC_2 == 1)
- state->mmu.auxiliary_control = value;
- else if(OPC_2 == 2)
- state->mmu.coprocessor_access_control = value;
- else
- fprintf(stderr, "In %s, wrong OPC_2 %d\n", __FUNCTION__, OPC_2);
- break;
- case MMU_TRANSLATION_TABLE_BASE:
- switch (OPC_2) {
- /* int i; */
- case 0:
-#if 0
- /* TTBR0 */
- if (state->mmu.translation_table_ctrl & 0x7) {
- for (i = 0; i <= state->mmu.translation_table_ctrl; i++)
- state->mmu.translation_table_base0 &= ~(1 << (5 + i));
- }
-#endif
- state->mmu.translation_table_base0 = (value);
- break;
- case 1:
-#if 0
- /* TTBR1 */
- if (state->mmu.translation_table_ctrl & 0x7) {
- for (i = 0; i <= state->mmu.translation_table_ctrl; i++)
- state->mmu.translation_table_base1 &= 1 << (5 + i);
- }
-#endif
- state->mmu.translation_table_base1 = (value);
- break;
- case 2:
- /* TTBC */
- state->mmu.translation_table_ctrl = value & 0x7;
- break;
- default:
- printf ("mmu_mcr wrote UNKNOWN - cp15 c2 opcode2 %d\n", OPC_2);
- break;
- }
- //printf("SKYEYE In %s, write TLB_BASE 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
- //invalidate_all_tlb(state);
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
- /* printf("mmu_mcr wrote DACR "); */
- state->mmu.domain_access_control = value;
- break;
-
- case MMU_FAULT_STATUS:
- if (OPC_2 == 0)
- state->mmu.fault_status = value & 0xFF;
- if (OPC_2 == 1) {
- printf("set fault status instr\n");
- }
- break;
- case MMU_FAULT_ADDRESS:
- state->mmu.fault_address = value;
- break;
-
- case MMU_CACHE_OPS:
- break;
- case MMU_TLB_OPS:
- {
- switch(CRm){
- case 5: /* ITLB */
- {
- switch(OPC_2){
- case 0: /* invalidate all */
- //invalidate_all_tlb(state);
- break;
- case 1: /* invalidate by MVA */
- //invalidate_by_mva(state, value);
- break;
- case 2: /* invalidate by asid */
- //invalidate_by_asid(state, value);
- break;
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- break;
- }
- break;
- }
- case 6: /* DTLB */
- {
- switch(OPC_2){
- case 0: /* invalidate all */
- //invalidate_all_tlb(state);
- break;
- case 1: /* invalidate by MVA */
- //invalidate_by_mva(state, value);
- break;
- case 2: /* invalidate by asid */
- //invalidate_by_asid(state, value);
- break;
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- break;
- }
- break;
- }
- case 7: /* Unified TLB */
- {
- switch(OPC_2){
- case 0: /* invalidate all */
- //invalidate_all_tlb(state);
- break;
- case 1: /* invalidate by MVA */
- //invalidate_by_mva(state, value);
- break;
- case 2: /* invalidate by asid */
- //invalidate_by_asid(state, value);
- break;
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- break;
- }
- break;
- }
-
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d, CRm=%d\n", creg, CRm);
- break;
- }
- //printf("SKYEYE In %s, write TLB 0x%x OPC_1=%d, OPC_2=%d , CRm=%d instr=0x%x\n", __FUNCTION__, value, OPC_1, OPC_2, CRm, instr);
- }
- break;
- case MMU_CACHE_LOCKDOWN:
- /*
- * FIXME: cache lock down*/
- break;
- case MMU_TLB_LOCKDOWN:
- printf("SKYEYE In %s, write TLB_LOCKDOWN 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
- /* FIXME:tlb lock down */
- break;
- case MMU_PID:
- //printf("SKYEYE In %s, write pid 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
- //state->mmu.process_id = value;
- /*0:24 should be zero. */
- //state->mmu.process_id = value & 0xfe000000;
- if(OPC_2 == 0)
- state->mmu.process_id = value;
- else if(OPC_2 == 1)
- state->mmu.context_id = value;
- else if(OPC_2 == 3){
- state->mmu.thread_uro_id = value;
- }
- else{
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- }
- break;
-
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- break;
- }
- }
-
- return No_exp;
-}
-
-///* teawater add for arm2x86 2005.06.19------------------------------------------- */
-//static int
-//arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr,
-// ARMword *phys_addr)
-//{
-// fault_t fault;
-// int ap, sop;
-//
-// ARMword perm; /* physical addr access permissions */
-// virt_addr = mmu_pid_va_map (virt_addr);
-// if (MMU_Enabled) {
-//
-// /*align check */
-// if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
-// DEBUG_LOG(ARM11, "align\n");
-// return ALIGNMENT_FAULT;
-// } else
-// virt_addr &= ~(WORD_SIZE - 1);
-//
-// /*translate tlb */
-// fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop);
-// if (fault) {
-// DEBUG_LOG(ARM11, "translate\n");
-// return fault;
-// }
-//
-// /* permission check */
-// if (!check_perms(state, ap, 1)) {
-// if (sop == 0) {
-// return SECTION_PERMISSION_FAULT;
-// } else {
-// return SUBPAGE_PERMISSION_FAULT;
-// }
-// }
-//#if 0
-// /*check access */
-// fault = check_access (state, virt_addr, tlb, 1);
-// if (fault) {
-// DEBUG_LOG(ARM11, "check_fault\n");
-// return fault;
-// }
-//#endif
-// }
-//
-// if (MMU_Disabled) {
-// *phys_addr = virt_addr;
-// }
-//
-// return 0;
-//}
-
-/* AJ2D-------------------------------------------------------------------------- */
-
-/*arm1176jzf-s mmu_ops_t*/
-mmu_ops_t arm1176jzf_s_mmu_ops = {
- arm1176jzf_s_mmu_init,
- arm1176jzf_s_mmu_exit,
- arm1176jzf_s_mmu_read_byte,
- arm1176jzf_s_mmu_write_byte,
- arm1176jzf_s_mmu_read_halfword,
- arm1176jzf_s_mmu_write_halfword,
- arm1176jzf_s_mmu_read_word,
- arm1176jzf_s_mmu_write_word,
- arm1176jzf_s_mmu_load_instr,
- arm1176jzf_s_mmu_mcr,
- arm1176jzf_s_mmu_mrc
-/* teawater add for arm2x86 2005.06.19------------------------------------------- */
-/* arm1176jzf_s_mmu_v2p_dbct, */
-/* AJ2D-------------------------------------------------------------------------- */
-};
diff --git a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.h b/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.h
deleted file mode 100644
index 299c6b46b9..0000000000
--- a/src/core/arm/interpreter/mmu/arm1176jzf_s_mmu.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- arm1176JZF-S_mmu.h - ARM1176JZF-S Memory Management Unit emulation.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#ifndef _ARM1176JZF_S_MMU_H_
-#define _ARM1176JZF_S_MMU_H_
-
-#if 0
-typedef struct arm1176jzf-s_mmu_s
-{
- tlb_t i_tlb;
- cache_t i_cache;
-
- tlb_t d_tlb;
- cache_t d_cache;
- wb_t wb_t;
-} arm1176jzf-s_mmu_t;
-#endif
-extern mmu_ops_t arm1176jzf_s_mmu_ops;
-
-ARMword
-arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value);
-#endif /*_ARM1176JZF_S_MMU_H_*/
diff --git a/src/core/arm/interpreter/mmu/cache.cpp b/src/core/arm/interpreter/mmu/cache.cpp
deleted file mode 100644
index cfbc31f1ed..0000000000
--- a/src/core/arm/interpreter/mmu/cache.cpp
+++ /dev/null
@@ -1,370 +0,0 @@
-#include "core/arm/skyeye_common/armdefs.h"
-
-/* mmu cache init
- *
- * @cache_t :cache_t to init
- * @width :cache line width in byte
- * @way :way of each cache set
- * @set :cache set num
- *
- * $ -1: error
- * 0: sucess
- */
-int
-mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode)
-{
- int i, j;
- cache_set_t *sets;
- cache_line_t *lines;
-
- /*alloc cache set */
- sets = NULL;
- lines = NULL;
- //fprintf(stderr, "mmu_cache_init: mallloc beg size %d,sets 0x%x\n", sizeof(cache_set_t) * set,sets);
- //exit(-1);
- sets = (cache_set_t *) malloc (sizeof (cache_set_t) * set);
- if (sets == NULL) {
- ERROR_LOG(ARM11, "set malloc size %d\n", sizeof (cache_set_t) * set);
- goto sets_error;
- }
- //fprintf(stderr, "mmu_cache_init: mallloc end sets 0x%x\n", sets);
- cache_t->sets = sets;
-
- /*init cache set */
- for (i = 0; i < set; i++) {
- /*alloc cache line */
- lines = (cache_line_t *) malloc (sizeof (cache_line_t) * way);
- if (lines == NULL) {
- ERROR_LOG(ARM11, "line malloc size %d\n",
- sizeof (cache_line_t) * way);
- goto lines_error;
- }
- /*init cache line */
- for (j = 0; j < way; j++) {
- lines[j].tag = 0; //invalid
- lines[j].data = (ARMword *) malloc (width);
- if (lines[j].data == NULL) {
- ERROR_LOG(ARM11, "data alloc size %d\n", width);
- goto data_error;
- }
- }
-
- sets[i].lines = lines;
- sets[i].cycle = 0;
-
- }
- cache_t->width = width;
- cache_t->set = set;
- cache_t->way = way;
- cache_t->w_mode = w_mode;
- return 0;
-
- data_error:
- /*free data */
- while (j-- > 0)
- free (lines[j].data);
- /*free data error line */
- free (lines);
- lines_error:
- /*free lines already alloced */
- while (i-- > 0) {
- for (j = 0; j < way; j++)
- free (sets[i].lines[j].data);
- free (sets[i].lines);
- }
- /*free sets */
- free (sets);
- sets_error:
- return -1;
-};
-
-/* free a cache_t's inner data, the ptr self is not freed,
- * when needed do like below:
- * mmu_cache_exit(cache);
- * free(cache_t);
- *
- * @cache_t : the cache_t to free
- */
-
-void
-mmu_cache_exit (cache_s * cache_t)
-{
- int i, j;
- cache_set_t *sets, *set;
- cache_line_t *lines, *line;
-
- /*free all set */
- sets = cache_t->sets;
- for (set = sets, i = 0; i < cache_t->set; i++, set++) {
- /*free all line */
- lines = set->lines;
- for (line = lines, j = 0; j < cache_t->way; j++, line++)
- free (line->data);
- free (lines);
- }
- free (sets);
-}
-
-/* mmu cache search
- *
- * @state :ARMul_State
- * @cache_t :cache_t to search
- * @va :virtual address
- *
- * $ NULL: no cache match
- * cache :cache matched
- */
-cache_line_t *
-mmu_cache_search (ARMul_State * state, cache_s * cache_t, ARMword va)
-{
- int i;
- int set = va_cache_set (va, cache_t);
- ARMword tag = va_cache_align (va, cache_t);
- cache_line_t *cache;
-
- cache_set_t *cache_set = cache_t->sets + set;
- for (i = 0, cache = cache_set->lines; i < cache_t->way; i++, cache++) {
- if ((cache->tag & TAG_VALID_FLAG)
- && (tag == va_cache_align (cache->tag, cache_t)))
- return cache;
- }
- return NULL;
-}
-
-/* mmu cache search by set/index
- *
- * @state :ARMul_State
- * @cache_t :cache_t to search
- * @index :set/index value.
- *
- * $ NULL: no cache match
- * cache :cache matched
- */
-cache_line_t *
-mmu_cache_search_by_index (ARMul_State * state, cache_s * cache_t,
- ARMword index)
-{
- int way = cache_t->way;
- int set_v = index_cache_set (index, cache_t);
- int i = 0, index_v = 0;
- cache_set_t *set;
-
- while ((way >>= 1) >= 1)
- i++;
- index_v = index >> (32 - i);
- set = cache_t->sets + set_v;
-
- return set->lines + index_v;
-}
-
-
-/* mmu cache alloc
- *
- * @state :ARMul_State
- * @cache_t :cache_t to alloc from
- * @va :virtual address that require cache alloc, need not cache aligned
- * @pa :physical address of va
- *
- * $ cache_alloced, always alloc OK
- */
-cache_line_t *
-mmu_cache_alloc (ARMul_State * state, cache_s * cache_t, ARMword va,
- ARMword pa)
-{
- cache_line_t *cache;
- cache_set_t *set;
- int i;
-
- va = va_cache_align (va, cache_t);
- pa = va_cache_align (pa, cache_t);
-
- set = &cache_t->sets[va_cache_set (va, cache_t)];
-
- /*robin-round */
- cache = &set->lines[set->cycle++];
- if (set->cycle == cache_t->way)
- set->cycle = 0;
-
- if (cache_t->w_mode == CACHE_WRITE_BACK) {
- ARMword t;
-
- /*if cache valid, try to write back */
- if (cache->tag & TAG_VALID_FLAG) {
- mmu_cache_write_back (state, cache_t, cache);
- }
- /*read in cache_line */
- t = pa;
- for (i = 0; i < (cache_t->width >> WORD_SHT);
- i++, t += WORD_SIZE) {
- //cache->data[i] = mem_read_word (state, t);
- bus_read(32, t, &cache->data[i]);
- }
- }
- /*store tag and pa */
- cache->tag = va | TAG_VALID_FLAG;
- cache->pa = pa;
-
- return cache;
-};
-
-/* mmu_cache_write_back write cache data to memory
- * @state
- * @cache_t :cache_t of the cache line
- * @cache : cache line
- */
-void
-mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
- cache_line_t * cache)
-{
- ARMword pa = cache->pa;
- int nw = cache_t->width >> WORD_SHT;
- ARMword *data = cache->data;
- int i;
- int t0, t1, t2;
-
- if ((cache->tag & 1) == 0)
- return;
-
- switch (cache->
- tag & ~1 & (TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY)) {
- case 0:
- return;
- case TAG_FIRST_HALF_DIRTY:
- nw /= 2;
- break;
- case TAG_LAST_HALF_DIRTY:
- nw /= 2;
- pa += nw << WORD_SHT;
- data += nw;
- break;
- case TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY:
- break;
- }
- for (i = 0; i < nw; i++, data++, pa += WORD_SIZE)
- //mem_write_word (state, pa, *data);
- bus_write(32, pa, *data);
-
- cache->tag &= ~(TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY);
-};
-
-
-/* mmu_cache_clean: clean a cache of va in cache_t
- *
- * @state :ARMul_State
- * @cache_t :cache_t to clean
- * @va :virtaul address
- */
-void
-mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va)
-{
- cache_line_t *cache;
-
- cache = mmu_cache_search (state, cache_t, va);
- if (cache)
- mmu_cache_write_back (state, cache_t, cache);
-}
-
-/* mmu_cache_clean_by_index: clean a cache by set/index format value
- *
- * @state :ARMul_State
- * @cache_t :cache_t to clean
- * @va :set/index format value
- */
-void
-mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
- ARMword index)
-{
- cache_line_t *cache;
-
- cache = mmu_cache_search_by_index (state, cache_t, index);
- if (cache)
- mmu_cache_write_back (state, cache_t, cache);
-}
-
-/* mmu_cache_invalidate : invalidate a cache of va
- *
- * @state :ARMul_State
- * @cache_t :cache_t to invalid
- * @va :virt_addr to invalid
- */
-void
-mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va)
-{
- cache_line_t *cache;
-
- cache = mmu_cache_search (state, cache_t, va);
- if (cache) {
- mmu_cache_write_back (state, cache_t, cache);
- cache->tag = 0;
- }
-}
-
-/* mmu_cache_invalidate_by_index : invalidate a cache by index format
- *
- * @state :ARMul_State
- * @cache_t :cache_t to invalid
- * @index :set/index data
- */
-void
-mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
- ARMword index)
-{
- cache_line_t *cache;
-
- cache = mmu_cache_search_by_index (state, cache_t, index);
- if (cache) {
- mmu_cache_write_back (state, cache_t, cache);
- cache->tag = 0;
- }
-}
-
-/* mmu_cache_invalidate_all
- *
- * @state:
- * @cache_t
- * */
-void
-mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t)
-{
- int i, j;
- cache_set_t *set;
- cache_line_t *cache;
-
- set = cache_t->sets;
- for (i = 0; i < cache_t->set; i++, set++) {
- cache = set->lines;
- for (j = 0; j < cache_t->way; j++, cache++) {
- mmu_cache_write_back (state, cache_t, cache);
- cache->tag = 0;
- }
- }
-};
-
-void
-mmu_cache_soft_flush (ARMul_State * state, cache_s * cache_t, ARMword pa)
-{
- ARMword set, way;
- cache_line_t *cache;
- pa = (pa / cache_t->width);
- way = pa & (cache_t->way - 1);
- set = (pa / cache_t->way) & (cache_t->set - 1);
- cache = &cache_t->sets[set].lines[way];
-
- mmu_cache_write_back (state, cache_t, cache);
- cache->tag = 0;
-}
-
-cache_line_t* mmu_cache_dirty_cache(ARMul_State *state,cache_s *cache){
- int i;
- int j;
- cache_line_t *cache_line = NULL;
- cache_set_t *cache_set = cache->sets;
- int sets = cache->set;
- for (i = 0; i < sets; i++){
- for(j = 0,cache_line = &cache_set[i].lines[0]; j < cache->way; j++,cache_line++){
- if((cache_line->tag & TAG_FIRST_HALF_DIRTY) || (cache_line->tag & TAG_LAST_HALF_DIRTY))
- return cache_line;
- }
- }
- return NULL;
-}
diff --git a/src/core/arm/interpreter/mmu/cache.h b/src/core/arm/interpreter/mmu/cache.h
deleted file mode 100644
index d308d9b874..0000000000
--- a/src/core/arm/interpreter/mmu/cache.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef _MMU_CACHE_H_
-#define _MMU_CACHE_H_
-
-typedef struct cache_line_t
-{
- ARMword tag; /* cache line align address |
- bit2: last half dirty
- bit1: first half dirty
- bit0: cache valid flag
- */
- ARMword pa; /*physical address */
- ARMword *data; /*array of cached data */
-} cache_line_t;
-#define TAG_VALID_FLAG 0x00000001
-#define TAG_FIRST_HALF_DIRTY 0x00000002
-#define TAG_LAST_HALF_DIRTY 0x00000004
-
-/*cache set association*/
-typedef struct cache_set_s
-{
- cache_line_t *lines;
- int cycle;
-} cache_set_t;
-
-enum
-{
- CACHE_WRITE_BACK,
- CACHE_WRITE_THROUGH,
-};
-
-typedef struct cache_s
-{
- int width; /*bytes in a line */
- int way; /*way of set asscociate */
- int set; /*num of set */
- int w_mode; /*write back or write through */
- //int a_mode; /*alloc mode: random or round-bin*/
- cache_set_t *sets;
- /**/} cache_s;
-
-typedef struct cache_desc_s
-{
- int width;
- int way;
- int set;
- int w_mode;
-// int a_mode;
-} cache_desc_t;
-
-
-/*virtual address to cache set index*/
-#define va_cache_set(va, cache_t) \
- (((va) / (cache_t)->width) & ((cache_t)->set - 1))
-/*virtual address to cahce line aligned*/
-#define va_cache_align(va, cache_t) \
- ((va) & ~((cache_t)->width - 1))
-/*virtaul address to cache line word index*/
-#define va_cache_index(va, cache_t) \
- (((va) & ((cache_t)->width - 1)) >> WORD_SHT)
-
-/*see Page 558 in arm manual*/
-/*set/index format value to cache set value*/
-#define index_cache_set(index, cache_t) \
- (((index) / (cache_t)->width) & ((cache_t)->set - 1))
-
-/*************************cache********************/
-/* mmu cache init
- *
- * @cache_t :cache_t to init
- * @width :cache line width in byte
- * @way :way of each cache set
- * @set :cache set num
- * @w_mode :cache w_mode
- *
- * $ -1: error
- * 0: sucess
- */
-int
-mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode);
-
-/* free a cache_t's inner data, the ptr self is not freed,
- * when needed do like below:
- * mmu_cache_exit(cache);
- * free(cache_t);
- *
- * @cache_t : the cache_t to free
- */
-void mmu_cache_exit (cache_s * cache_t);
-
-/* mmu cache search
- *
- * @state :ARMul_State
- * @cache_t :cache_t to search
- * @va :virtual address
- *
- * $ NULL: no cache match
- * cache :cache matched
- * */
-cache_line_t *mmu_cache_search (ARMul_State * state, cache_s * cache_t,
- ARMword va);
-
-/* mmu cache search by set/index
- *
- * @state :ARMul_State
- * @cache_t :cache_t to search
- * @index :set/index value.
- *
- * $ NULL: no cache match
- * cache :cache matched
- * */
-
-cache_line_t *mmu_cache_search_by_index (ARMul_State * state,
- cache_s * cache_t, ARMword index);
-
-/* mmu cache alloc
- *
- * @state :ARMul_State
- * @cache_t :cache_t to alloc from
- * @va :virtual address that require cache alloc, need not cache aligned
- * @pa :physical address of va
- *
- * $ cache_alloced, always alloc OK
- */
-cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
- ARMword va, ARMword pa);
-
-/* mmu_cache_write_back write cache data to memory
- *
- * @state:
- * @cache_t :cache_t of the cache line
- * @cache : cache line
- */
-void
-mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
- cache_line_t * cache);
-
-/* mmu_cache_clean: clean a cache of va in cache_t
- *
- * @state :ARMul_State
- * @cache_t :cache_t to clean
- * @va :virtaul address
- */
-void mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va);
-void
-mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
- ARMword index);
-
-/* mmu_cache_invalidate : invalidate a cache of va
- *
- * @state :ARMul_State
- * @cache_t :cache_t to invalid
- * @va :virt_addr to invalid
- */
-void
-mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va);
-
-void
-mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
- ARMword index);
-
-void mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t);
-
-void
-mmu_cache_soft_flush (ARMul_State * state, cache_s * cache_t, ARMword pa);
-
-cache_line_t* mmu_cache_dirty_cache(ARMul_State * state, cache_s * cache_t);
-
-#endif /*_MMU_CACHE_H_*/
diff --git a/src/core/arm/interpreter/mmu/maverick.cpp b/src/core/arm/interpreter/mmu/maverick.cpp
deleted file mode 100644
index a07d4742b5..0000000000
--- a/src/core/arm/interpreter/mmu/maverick.cpp
+++ /dev/null
@@ -1,1206 +0,0 @@
-/* maverick.c -- Cirrus/DSP co-processor interface.
- Copyright (C) 2003 Free Software Foundation, Inc.
- Contributed by Aldy Hernandez (aldyh@redhat.com).
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#include <assert.h>
-
-#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/armemu.h"
-
-
-/*#define CIRRUS_DEBUG 1 */
-#if CIRRUS_DEBUG
-# define printfdbg printf
-#else
-# define printfdbg printf_nothing
-#endif
-
-#define POS64(i) ( (~(i)) >> 63 )
-#define NEG64(i) ( (i) >> 63 )
-
-/* Define Co-Processor instruction handlers here. */
-
-/* Here's ARMulator's DSP definition. A few things to note:
- 1) it has 16 64-bit registers and 4 72-bit accumulators
- 2) you can only access its registers with MCR and MRC. */
-
-/* We can't define these in here because this file might not be linked
- unless the target is arm9e-*. They are defined in wrapper.c.
- Eventually the simulator should be made to handle any coprocessor
- at run time. */
-struct maverick_regs
-{
- union
- {
- int i;
- float f;
- } upper;
-
- union
- {
- int i;
- float f;
- } lower;
-};
-
-union maverick_acc_regs
-{
- long double ld; /* Acc registers are 72-bits. */
-};
-
-struct maverick_regs DSPregs[16];
-union maverick_acc_regs DSPacc[4];
-ARMword DSPsc;
-
-#define DEST_REG (BITS (12, 15))
-#define SRC1_REG (BITS (16, 19))
-#define SRC2_REG (BITS (0, 3))
-
-static int lsw_int_index, msw_int_index;
-static int lsw_float_index, msw_float_index;
-
-static double mv_getRegDouble (int);
-static long long mv_getReg64int (int);
-static void mv_setRegDouble (int, double val);
-static void mv_setReg64int (int, long long val);
-
-static union
-{
- double d;
- long long ll;
- int ints[2];
-} reg_conv;
-
-static void
-printf_nothing (const char *foo, ...)
-{
-}
-
-static void
-cirrus_not_implemented (const char *insn)
-{
- fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn);
- fprintf (stderr, "aborting!\n");
-
- // skyeye_exit (1);
-}
-
-static unsigned
-DSPInit (ARMul_State * state)
-{
- NOTICE_LOG(ARM11, "ARMul_ConsolePrint: DSP present");
- return TRUE;
-}
-
-unsigned
-DSPMRC4 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * value)
-{
- switch (BITS (5, 7)) {
- case 0: /* cfmvrdl */
- /* Move lower half of a DF stored in a DSP reg into an Arm reg. */
- printfdbg ("cfmvrdl\n");
- printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i);
- printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
-
- *value = (ARMword) DSPregs[SRC1_REG].lower.i;
- break;
-
- case 1: /* cfmvrdh */
- /* Move upper half of a DF stored in a DSP reg into an Arm reg. */
- printfdbg ("cfmvrdh\n");
- printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i);
- printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
-
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- break;
-
- case 2: /* cfmvrs */
- /* Move SF from upper half of a DSP register to an Arm register. */
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- printfdbg ("cfmvrs = mvf%d <-- %f\n",
- SRC1_REG, DSPregs[SRC1_REG].upper.f);
- break;
-
-#ifdef doesnt_work
- case 4: /* cfcmps */
- {
- float a, b;
- int n, z, c, v;
-
- a = DSPregs[SRC1_REG].upper.f;
- b = DSPregs[SRC2_REG].upper.f;
-
- printfdbg ("cfcmps\n");
- printfdbg ("\tcomparing %f and %f\n", a, b);
-
- z = a == b; /* zero */
- n = a != b; /* negative */
- v = a > b; /* overflow */
- c = 0; /* carry */
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-
- case 5: /* cfcmpd */
- {
- double a, b;
- int n, z, c, v;
-
- a = mv_getRegDouble (SRC1_REG);
- b = mv_getRegDouble (SRC2_REG);
-
- printfdbg ("cfcmpd\n");
- printfdbg ("\tcomparing %g and %g\n", a, b);
-
- z = a == b; /* zero */
- n = a != b; /* negative */
- v = a > b; /* overflow */
- c = 0; /* carry */
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-#else
- case 4: /* cfcmps */
- {
- float a, b;
- int n, z, c, v;
-
- a = DSPregs[SRC1_REG].upper.f;
- b = DSPregs[SRC2_REG].upper.f;
-
- printfdbg ("cfcmps\n");
- printfdbg ("\tcomparing %f and %f\n", a, b);
-
- z = a == b; /* zero */
- n = a < b; /* negative */
- c = a > b; /* carry */
- v = 0; /* fixme */
- printfdbg ("\tz = %d, n = %d\n", z, n);
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-
- case 5: /* cfcmpd */
- {
- double a, b;
- int n, z, c, v;
-
- a = mv_getRegDouble (SRC1_REG);
- b = mv_getRegDouble (SRC2_REG);
-
- printfdbg ("cfcmpd\n");
- printfdbg ("\tcomparing %g and %g\n", a, b);
-
- z = a == b; /* zero */
- n = a < b; /* negative */
- c = a > b; /* carry */
- v = 0; /* fixme */
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-#endif
- default:
- fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMRC5 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * value)
-{
- switch (BITS (5, 7)) {
- case 0: /* cfmvr64l */
- /* Move lower half of 64bit int from Cirrus to Arm. */
- *value = (ARMword) DSPregs[SRC1_REG].lower.i;
- printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n",
- DEST_REG, (int) *value);
- break;
-
- case 1: /* cfmvr64h */
- /* Move upper half of 64bit int from Cirrus to Arm. */
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- printfdbg ("cfmvr64h <-- %d\n", (int) *value);
- break;
-
- case 4: /* cfcmp32 */
- {
- int res;
- int n, z, c, v;
- unsigned int a, b;
-
- printfdbg ("cfcmp32 mvfx%d - mvfx%d\n", SRC1_REG,
- SRC2_REG);
-
- /* FIXME: see comment for cfcmps. */
- a = DSPregs[SRC1_REG].lower.i;
- b = DSPregs[SRC2_REG].lower.i;
-
- res = DSPregs[SRC1_REG].lower.i -
- DSPregs[SRC2_REG].lower.i;
- /* zero */
- z = res == 0;
- /* negative */
- n = res < 0;
- /* overflow */
- v = SubOverflow (DSPregs[SRC1_REG].lower.i,
- DSPregs[SRC2_REG].lower.i, res);
- /* carry */
- c = (NEG (a) && POS (b) ||
- (NEG (a) && POS (res)) || (POS (b)
- && POS (res)));
-
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-
- case 5: /* cfcmp64 */
- {
- long long res;
- int n, z, c, v;
- unsigned long long a, b;
-
- printfdbg ("cfcmp64 mvdx%d - mvdx%d\n", SRC1_REG,
- SRC2_REG);
-
- /* fixme: see comment for cfcmps. */
-
- a = mv_getReg64int (SRC1_REG);
- b = mv_getReg64int (SRC2_REG);
-
- res = mv_getReg64int (SRC1_REG) -
- mv_getReg64int (SRC2_REG);
- /* zero */
- z = res == 0;
- /* negative */
- n = res < 0;
- /* overflow */
- v = ((NEG64 (a) && POS64 (b) && POS64 (res))
- || (POS64 (a) && NEG64 (b) && NEG64 (res)));
- /* carry */
- c = (NEG64 (a) && POS64 (b) ||
- (NEG64 (a) && POS64 (res)) || (POS64 (b)
- && POS64 (res)));
-
- *value = (n << 31) | (z << 30) | (c << 29) | (v <<
- 28);
- break;
- }
-
- default:
- fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMRC6 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * value)
-{
- switch (BITS (5, 7)) {
- case 0: /* cfmval32 */
- cirrus_not_implemented ("cfmval32");
- break;
-
- case 1: /* cfmvam32 */
- cirrus_not_implemented ("cfmvam32");
- break;
-
- case 2: /* cfmvah32 */
- cirrus_not_implemented ("cfmvah32");
- break;
-
- case 3: /* cfmva32 */
- cirrus_not_implemented ("cfmva32");
- break;
-
- case 4: /* cfmva64 */
- cirrus_not_implemented ("cfmva64");
- break;
-
- case 5: /* cfmvsc32 */
- cirrus_not_implemented ("cfmvsc32");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR4 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword value)
-{
- switch (BITS (5, 7)) {
- case 0: /* cfmvdlr */
- /* Move the lower half of a DF value from an Arm register into
- the lower half of a Cirrus register. */
- printfdbg ("cfmvdlr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].lower.i = (int) value;
- break;
-
- case 1: /* cfmvdhr */
- /* Move the upper half of a DF value from an Arm register into
- the upper half of a Cirrus register. */
- printfdbg ("cfmvdhr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- case 2: /* cfmvsr */
- /* Move SF from Arm register into upper half of Cirrus register. */
- printfdbg ("cfmvsr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR5 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword value)
-{
- union
- {
- int s;
- unsigned int us;
- } val;
-
- switch (BITS (5, 7)) {
- case 0: /* cfmv64lr */
- /* Move lower half of a 64bit int from an ARM register into the
- lower half of a DSP register and sign extend it. */
- printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG,
- (int) value);
- DSPregs[SRC1_REG].lower.i = (int) value;
- break;
-
- case 1: /* cfmv64hr */
- /* Move upper half of a 64bit int from an ARM register into the
- upper half of a DSP register. */
- printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n",
- SRC1_REG, (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- case 2: /* cfrshl32 */
- printfdbg ("cfrshl32\n");
- val.us = value;
- if (val.s > 0)
- DSPregs[SRC2_REG].lower.i =
- DSPregs[SRC1_REG].lower.i << value;
- else
- DSPregs[SRC2_REG].lower.i =
- DSPregs[SRC1_REG].lower.i >> -value;
- break;
-
- case 3: /* cfrshl64 */
- printfdbg ("cfrshl64\n");
- val.us = value;
- if (val.s > 0)
- mv_setReg64int (SRC2_REG,
- mv_getReg64int (SRC1_REG) << value);
- else
- mv_setReg64int (SRC2_REG,
- mv_getReg64int (SRC1_REG) >> -value);
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR6 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword value)
-{
- switch (BITS (5, 7)) {
- case 0: /* cfmv32al */
- cirrus_not_implemented ("cfmv32al");
- break;
-
- case 1: /* cfmv32am */
- cirrus_not_implemented ("cfmv32am");
- break;
-
- case 2: /* cfmv32ah */
- cirrus_not_implemented ("cfmv32ah");
- break;
-
- case 3: /* cfmv32a */
- cirrus_not_implemented ("cfmv32a");
- break;
-
- case 4: /* cfmv64a */
- cirrus_not_implemented ("cfmv64a");
- break;
-
- case 5: /* cfmv32sc */
- cirrus_not_implemented ("cfmv32sc");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPLDC4 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA) {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22)) { /* it's a long access, get two words */
- /* cfldrd */
-
- printfdbg
- ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n",
- data, words, state->bigendSig, DEST_REG);
-
- if (words == 0) {
- if (state->bigendSig)
- DSPregs[DEST_REG].upper.i = (int) data;
- else
- DSPregs[DEST_REG].lower.i = (int) data;
- }
- else {
- if (state->bigendSig)
- DSPregs[DEST_REG].lower.i = (int) data;
- else
- DSPregs[DEST_REG].upper.i = (int) data;
- }
-
- ++words;
-
- if (words == 2) {
- printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG,
- mv_getRegDouble (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else {
- /* Get just one word. */
-
- /* cfldrs */
- printfdbg ("cfldrs\n");
-
- DSPregs[DEST_REG].upper.i = (int) data;
-
- printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG,
- DSPregs[DEST_REG].upper.f);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPLDC5 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA) {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22)) {
- /* It's a long access, get two words. */
-
- /* cfldr64 */
- printfdbg ("cfldr64: %d\n", data);
-
- if (words == 0) {
- if (state->bigendSig)
- DSPregs[DEST_REG].upper.i = (int) data;
- else
- DSPregs[DEST_REG].lower.i = (int) data;
- }
- else {
- if (state->bigendSig)
- DSPregs[DEST_REG].lower.i = (int) data;
- else
- DSPregs[DEST_REG].upper.i = (int) data;
- }
-
- ++words;
-
- if (words == 2) {
- printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG,
- mv_getReg64int (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else {
- /* Get just one word. */
-
- /* cfldr32 */
- printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data);
-
- /* 32bit ints should be sign extended to 64bits when loaded. */
- mv_setReg64int (DEST_REG, (long long) data);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPSTC4 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA) {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22)) {
- /* It's a long access, get two words. */
- /* cfstrd */
- printfdbg ("cfstrd\n");
-
- if (words == 0) {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- }
- else {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- }
-
- ++words;
-
- if (words == 2) {
- printfdbg ("\tmem = mvd%d = %g\n", DEST_REG,
- mv_getRegDouble (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else {
- /* Get just one word. */
- /* cfstrs */
- printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG,
- DSPregs[DEST_REG].upper.f);
-
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPSTC5 (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA) {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22)) {
- /* It's a long access, store two words. */
- /* cfstr64 */
- printfdbg ("cfstr64\n");
-
- if (words == 0) {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- }
- else {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- }
-
- ++words;
-
- if (words == 2) {
- printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG,
- mv_getReg64int (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else {
- /* Store just one word. */
- /* cfstr32 */
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
-
- printfdbg ("cfstr32 MEM = %d\n", (int) *data);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPCDP4 (ARMul_State * state, unsigned type, ARMword instr)
-{
- int opcode2;
-
- opcode2 = BITS (5, 7);
-
- switch (BITS (20, 21)) {
- case 0:
- switch (opcode2) {
- case 0: /* cfcpys */
- printfdbg ("cfcpys mvf%d = mvf%d = %f\n",
- DEST_REG, SRC1_REG,
- DSPregs[SRC1_REG].upper.f);
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f;
- break;
-
- case 1: /* cfcpyd */
- printfdbg ("cfcpyd mvd%d = mvd%d = %g\n",
- DEST_REG, SRC1_REG,
- mv_getRegDouble (SRC1_REG));
- mv_setRegDouble (DEST_REG,
- mv_getRegDouble (SRC1_REG));
- break;
-
- case 2: /* cfcvtds */
- printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n",
- DEST_REG, SRC1_REG,
- (float) mv_getRegDouble (SRC1_REG));
- DSPregs[DEST_REG].upper.f =
- (float) mv_getRegDouble (SRC1_REG);
- break;
-
- case 3: /* cfcvtsd */
- printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n",
- DEST_REG, SRC1_REG,
- (double) DSPregs[SRC1_REG].upper.f);
- mv_setRegDouble (DEST_REG,
- (double) DSPregs[SRC1_REG].upper.f);
- break;
-
- case 4: /* cfcvt32s */
- printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n",
- DEST_REG, SRC1_REG,
- (float) DSPregs[SRC1_REG].lower.i);
- DSPregs[DEST_REG].upper.f =
- (float) DSPregs[SRC1_REG].lower.i;
- break;
-
- case 5: /* cfcvt32d */
- printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n",
- DEST_REG, SRC1_REG,
- (double) DSPregs[SRC1_REG].lower.i);
- mv_setRegDouble (DEST_REG,
- (double) DSPregs[SRC1_REG].lower.i);
- break;
-
- case 6: /* cfcvt64s */
- printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n",
- DEST_REG, SRC1_REG,
- (float) mv_getReg64int (SRC1_REG));
- DSPregs[DEST_REG].upper.f =
- (float) mv_getReg64int (SRC1_REG);
- break;
-
- case 7: /* cfcvt64d */
- printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n",
- DEST_REG, SRC1_REG,
- (double) mv_getReg64int (SRC1_REG));
- mv_setRegDouble (DEST_REG,
- (double) mv_getReg64int (SRC1_REG));
- break;
- }
- break;
-
- case 1:
- switch (opcode2) {
- case 0: /* cfmuls */
- printfdbg ("cfmuls mvf%d = mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[SRC1_REG].upper.f *
- DSPregs[SRC2_REG].upper.f);
-
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- * DSPregs[SRC2_REG].upper.f;
- break;
-
- case 1: /* cfmuld */
- printfdbg ("cfmuld mvd%d = mvd%d = %g\n",
- DEST_REG,
- SRC1_REG,
- mv_getRegDouble (SRC1_REG) *
- mv_getRegDouble (SRC2_REG));
-
- mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)
- * mv_getRegDouble (SRC2_REG));
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n",
- instr);
- cirrus_not_implemented ("unknown");
- break;
- }
- break;
-
- case 3:
- switch (opcode2) {
- case 0: /* cfabss */
- DSPregs[DEST_REG].upper.f =
- (DSPregs[SRC1_REG].upper.f <
- 0.0F ? -DSPregs[SRC1_REG].upper.
- f : DSPregs[SRC1_REG].upper.f);
- printfdbg ("cfabss mvf%d = |mvf%d| = %f\n", DEST_REG,
- SRC1_REG, DSPregs[DEST_REG].upper.f);
- break;
-
- case 1: /* cfabsd */
- mv_setRegDouble (DEST_REG,
- (mv_getRegDouble (SRC1_REG) < 0.0 ?
- -mv_getRegDouble (SRC1_REG)
- : mv_getRegDouble (SRC1_REG)));
- printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n",
- DEST_REG, SRC1_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 2: /* cfnegs */
- DSPregs[DEST_REG].upper.f =
- -DSPregs[SRC1_REG].upper.f;
- printfdbg ("cfnegs mvf%d = -mvf%d = %f\n", DEST_REG,
- SRC1_REG, DSPregs[DEST_REG].upper.f);
- break;
-
- case 3: /* cfnegd */
- mv_setRegDouble (DEST_REG,
- -mv_getRegDouble (SRC1_REG));
- printfdbg ("cfnegd mvd%d = -mvd%d = %g\n", DEST_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 4: /* cfadds */
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- + DSPregs[SRC2_REG].upper.f;
- printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 5: /* cfaddd */
- mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)
- + mv_getRegDouble (SRC2_REG));
- printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n",
- DEST_REG,
- SRC1_REG, SRC2_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 6: /* cfsubs */
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- - DSPregs[SRC2_REG].upper.f;
- printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 7: /* cfsubd */
- mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)
- - mv_getRegDouble (SRC2_REG));
- printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n",
- DEST_REG,
- SRC1_REG, SRC2_REG,
- mv_getRegDouble (DEST_REG));
- break;
- }
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPCDP5 (ARMul_State * state, unsigned type, ARMword instr)
-{
- int opcode2;
- char shift;
-
- opcode2 = BITS (5, 7);
-
- /* Shift constants are 7bit signed numbers in bits 0..3|5..7. */
- shift = BITS (0, 3) | (BITS (5, 7)) << 4;
- if (shift & 0x40)
- shift |= 0xc0;
-
- switch (BITS (20, 21)) {
- case 0:
- /* cfsh32 */
- printfdbg ("cfsh32 %s amount=%d\n",
- shift < 0 ? "right" : "left", shift);
- if (shift < 0)
- /* Negative shift is a right shift. */
- DSPregs[DEST_REG].lower.i =
- DSPregs[SRC1_REG].lower.i >> -shift;
- else
- /* Positive shift is a left shift. */
- DSPregs[DEST_REG].lower.i =
- DSPregs[SRC1_REG].lower.i << shift;
- break;
-
- case 1:
- switch (opcode2) {
- case 0: /* cfmul32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- * DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 1: /* cfmul64 */
- mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG)
- * mv_getReg64int (SRC2_REG));
- printfdbg
- ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 2: /* cfmac32 */
- DSPregs[DEST_REG].lower.i
- +=
- DSPregs[SRC1_REG].lower.i *
- DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 3: /* cfmsc32 */
- DSPregs[DEST_REG].lower.i
- -=
- DSPregs[SRC1_REG].lower.i *
- DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 4: /* cfcvts32 */
- /* fixme: this should round */
- DSPregs[DEST_REG].lower.i =
- (int) DSPregs[SRC1_REG].upper.f;
- printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n", DEST_REG,
- SRC1_REG, DSPregs[DEST_REG].lower.i);
- break;
-
- case 5: /* cfcvtd32 */
- /* fixme: this should round */
- DSPregs[DEST_REG].lower.i =
- (int) mv_getRegDouble (SRC1_REG);
- printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n", DEST_REG,
- SRC1_REG, DSPregs[DEST_REG].lower.i);
- break;
-
- case 6: /* cftruncs32 */
- DSPregs[DEST_REG].lower.i =
- (int) DSPregs[SRC1_REG].upper.f;
- printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n",
- DEST_REG, SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 7: /* cftruncd32 */
- DSPregs[DEST_REG].lower.i =
- (int) mv_getRegDouble (SRC1_REG);
- printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n",
- DEST_REG, SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
- }
- break;
-
- case 2:
- /* cfsh64 */
- printfdbg ("cfsh64\n");
-
- if (shift < 0)
- /* Negative shift is a right shift. */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG) >> -shift);
- else
- /* Positive shift is a left shift. */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG) << shift);
- printfdbg ("\t%llx\n", mv_getReg64int (DEST_REG));
- break;
-
- case 3:
- switch (opcode2) {
- case 0: /* cfabs32 */
- DSPregs[DEST_REG].lower.i =
- (DSPregs[SRC1_REG].lower.i <
- 0 ? -DSPregs[SRC1_REG].lower.
- i : DSPregs[SRC1_REG].lower.i);
- printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 1: /* cfabs64 */
- mv_setReg64int (DEST_REG,
- (mv_getReg64int (SRC1_REG) < 0
- ? -mv_getReg64int (SRC1_REG)
- : mv_getReg64int (SRC1_REG)));
- printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 2: /* cfneg32 */
- DSPregs[DEST_REG].lower.i =
- -DSPregs[SRC1_REG].lower.i;
- printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 3: /* cfneg64 */
- mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG));
- printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 4: /* cfadd32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- + DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 5: /* cfadd64 */
- mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG)
- + mv_getReg64int (SRC2_REG));
- printfdbg
- ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 6: /* cfsub32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- - DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 7: /* cfsub64 */
- mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG)
- - mv_getReg64int (SRC2_REG));
- printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n",
- DEST_REG, SRC1_REG, SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
- }
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPCDP6 (ARMul_State * state, unsigned type, ARMword instr)
-{
- int opcode2;
-
- opcode2 = BITS (5, 7);
-
- switch (BITS (20, 21)) {
- case 0:
- /* cfmadd32 */
- cirrus_not_implemented ("cfmadd32");
- break;
-
- case 1:
- /* cfmsub32 */
- cirrus_not_implemented ("cfmsub32");
- break;
-
- case 2:
- /* cfmadda32 */
- cirrus_not_implemented ("cfmadda32");
- break;
-
- case 3:
- /* cfmsuba32 */
- cirrus_not_implemented ("cfmsuba32");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr);
- }
-
- return ARMul_DONE;
-}
-
-/* Conversion functions.
-
- 32-bit integers are stored in the LOWER half of a 64-bit physical
- register.
-
- Single precision floats are stored in the UPPER half of a 64-bit
- physical register. */
-
-static double
-mv_getRegDouble (int regnum)
-{
- reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i;
- reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i;
- return reg_conv.d;
-}
-
-static void
-mv_setRegDouble (int regnum, double val)
-{
- reg_conv.d = val;
- DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index];
- DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index];
-}
-
-static long long
-mv_getReg64int (int regnum)
-{
- reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i;
- reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i;
- return reg_conv.ll;
-}
-
-static void
-mv_setReg64int (int regnum, long long val)
-{
- reg_conv.ll = val;
- DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index];
- DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index];
-}
-
-/* Compute LSW in a double and a long long. */
-
-void
-mv_compute_host_endianness (ARMul_State * state)
-{
- static union
- {
- long long ll;
- int ints[2];
- int i;
- double d;
- float floats[2];
- float f;
- } conv;
-
- /* Calculate where's the LSW in a 64bit int. */
- conv.ll = 45;
-
- if (conv.ints[0] == 0) {
- msw_int_index = 0;
- lsw_int_index = 1;
- }
- else {
- assert (conv.ints[1] == 0);
- msw_int_index = 1;
- lsw_int_index = 0;
- }
-
- /* Calculate where's the LSW in a double. */
- conv.d = 3.0;
-
- if (conv.ints[0] == 0) {
- msw_float_index = 0;
- lsw_float_index = 1;
- }
- else {
- assert (conv.ints[1] == 0);
- msw_float_index = 1;
- lsw_float_index = 0;
- }
-
- printfdbg ("lsw_int_index %d\n", lsw_int_index);
- printfdbg ("lsw_float_index %d\n", lsw_float_index);
-}
diff --git a/src/core/arm/interpreter/mmu/rb.cpp b/src/core/arm/interpreter/mmu/rb.cpp
deleted file mode 100644
index 600c9d8c8b..0000000000
--- a/src/core/arm/interpreter/mmu/rb.cpp
+++ /dev/null
@@ -1,126 +0,0 @@
-#include "core/arm/skyeye_common/armdefs.h"
-
-/*chy 2004-06-06, fix bug found by wenye@cs.ucsb.edu*/
-ARMword rb_masks[] = {
- 0x0, //RB_INVALID
- 4, //RB_1
- 16, //RB_4
- 32, //RB_8
-};
-
-/*mmu_rb_init
- * @rb_t :rb_t to init
- * @num :number of entry
- * */
-int
-mmu_rb_init (rb_s * rb_t, int num)
-{
- int i;
- rb_entry_t *entrys;
-
- entrys = (rb_entry_t *) malloc (sizeof (*entrys) * num);
- if (entrys == NULL) {
- printf ("SKYEYE:mmu_rb_init malloc error\n");
- return -1;
- }
- for (i = 0; i < num; i++) {
- entrys[i].type = RB_INVALID;
- entrys[i].fault = NO_FAULT;
- }
-
- rb_t->entrys = entrys;
- rb_t->num = num;
- return 0;
-}
-
-/*mmu_rb_exit*/
-void
-mmu_rb_exit (rb_s * rb_t)
-{
- free (rb_t->entrys);
-};
-
-/*mmu_rb_search
- * @rb_t :rb_t to serach
- * @va :va address to math
- *
- * $ NULL :not match
- * NO-NULL:
- * */
-rb_entry_t *
-mmu_rb_search (rb_s * rb_t, ARMword va)
-{
- int i;
- rb_entry_t *rb = rb_t->entrys;
-
- DEBUG_LOG(ARM11, "va = %x\n", va);
- for (i = 0; i < rb_t->num; i++, rb++) {
- //2004-06-06 lyh bug from wenye@cs.ucsb.edu
- if (rb->type) {
- if ((va >= rb->va)
- && (va < (rb->va + rb_masks[rb->type])))
- return rb;
- }
- }
- return NULL;
-};
-
-void
-mmu_rb_invalidate_entry (rb_s * rb_t, int i)
-{
- rb_t->entrys[i].type = RB_INVALID;
-}
-
-void
-mmu_rb_invalidate_all (rb_s * rb_t)
-{
- int i;
-
- for (i = 0; i < rb_t->num; i++)
- mmu_rb_invalidate_entry (rb_t, i);
-};
-
-void
-mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb, int type, ARMword va)
-{
- rb_entry_t *rb;
- int i;
- ARMword max_start, min_end;
- fault_t fault;
- tlb_entry_t *tlb;
-
- /*align va according to type */
- va &= ~(rb_masks[type] - 1);
- /*invalidate all RB match [va, va + rb_masks[type]] */
- for (rb = rb_t->entrys, i = 0; i < rb_t->num; i++, rb++) {
- if (rb->type) {
- max_start = max (va, rb->va);
- min_end =
- min (va + rb_masks[type],
- rb->va + rb_masks[rb->type]);
- if (max_start < min_end)
- rb->type = RB_INVALID;
- }
- }
- /*load word */
- rb = &rb_t->entrys[i_rb];
- rb->type = type;
- fault = translate (state, va, D_TLB (), &tlb);
- if (fault) {
- rb->fault = fault;
- return;
- }
- fault = check_access (state, va, tlb, 1);
- if (fault) {
- rb->fault = fault;
- return;
- }
-
- rb->fault = NO_FAULT;
- va = tlb_va_to_pa (tlb, va);
- //2004-06-06 lyh bug from wenye@cs.ucsb.edu
- for (i = 0; i < (rb_masks[type] / 4); i++, va += WORD_SIZE) {
- //rb->data[i] = mem_read_word (state, va);
- bus_read(32, va, &rb->data[i]);
- };
-}
diff --git a/src/core/arm/interpreter/mmu/rb.h b/src/core/arm/interpreter/mmu/rb.h
deleted file mode 100644
index 7bf0ebb263..0000000000
--- a/src/core/arm/interpreter/mmu/rb.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _MMU_RB_H
-#define _MMU_RB_H
-
-enum rb_type_t
-{
- RB_INVALID = 0, //invalid
- RB_1, //1 word
- RB_4, //4 word
- RB_8, //8 word
-};
-
-/*bytes of each rb_type*/
-extern ARMword rb_masks[];
-
-#define RB_WORD_NUM 8
-typedef struct rb_entry_s
-{
- ARMword data[RB_WORD_NUM]; //array to store data
- ARMword va; //first word va
- int type; //rb type
- fault_t fault; //fault set by rb alloc
-} rb_entry_t;
-
-typedef struct rb_s
-{
- int num;
- rb_entry_t *entrys;
-} rb_s;
-
-/*mmu_rb_init
- * @rb_t :rb_t to init
- * @num :number of entry
- * */
-int mmu_rb_init (rb_s * rb_t, int num);
-
-/*mmu_rb_exit*/
-void mmu_rb_exit (rb_s * rb_t);
-
-
-/*mmu_rb_search
- * @rb_t :rb_t to serach
- * @va :va address to math
- *
- * $ NULL :not match
- * NO-NULL:
- * */
-rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
-
-
-void mmu_rb_invalidate_entry (rb_s * rb_t, int i);
-void mmu_rb_invalidate_all (rb_s * rb_t);
-void mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb,
- int type, ARMword va);
-
-#endif /*_MMU_RB_H_*/
diff --git a/src/core/arm/interpreter/mmu/sa_mmu.cpp b/src/core/arm/interpreter/mmu/sa_mmu.cpp
deleted file mode 100644
index 27f9ec8e0e..0000000000
--- a/src/core/arm/interpreter/mmu/sa_mmu.cpp
+++ /dev/null
@@ -1,864 +0,0 @@
-/*
- armmmu.c - Memory Management Unit emulation.
- ARMulator extensions for the ARM7100 family.
- Copyright (C) 1999 Ben Williamson
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <assert.h>
-#include <string.h>
-
-#include "core/arm/skyeye_common/armdefs.h"
-
-/**
- * The interface of read data from bus
- */
-int bus_read(short size, int addr, uint32_t * value) {
- ERROR_LOG(ARM11, "unimplemented bus_read");
- return 0;
-}
-
-/**
- * The interface of write data from bus
- */
-int bus_write(short size, int addr, uint32_t value) {
- ERROR_LOG(ARM11, "unimplemented bus_write");
- return 0;
-}
-
-
-typedef struct sa_mmu_desc_s
-{
- int i_tlb;
- cache_desc_t i_cache;
-
- int d_tlb;
- cache_desc_t main_d_cache;
- cache_desc_t mini_d_cache;
- int rb;
- wb_desc_t wb;
-} sa_mmu_desc_t;
-
-static sa_mmu_desc_t sa11xx_mmu_desc = {
- 32,
- {32, 32, 16, CACHE_WRITE_BACK},
-
- 32,
- {32, 32, 8, CACHE_WRITE_BACK},
- {32, 2, 8, CACHE_WRITE_BACK},
- 4,
- //{8, 4}, for word size
- {8, 16}, //for byte size, chy 2003-07-11
-};
-
-static fault_t sa_mmu_write (ARMul_State * state, ARMword va, ARMword data,
- ARMword datatype);
-static fault_t sa_mmu_read (ARMul_State * state, ARMword va, ARMword * data,
- ARMword datatype);
-static fault_t update_cache (ARMul_State * state, ARMword va, ARMword data,
- ARMword datatype, cache_line_t * cache,
- cache_s * cache_t, ARMword real_va);
-
-void
-mmu_wb_write_bytes (ARMul_State * state, wb_s * wb_t, ARMword pa,
- ARMbyte * data, int n);
-int
-sa_mmu_init (ARMul_State * state)
-{
- sa_mmu_desc_t *desc;
- cache_desc_t *c_desc;
-
- state->mmu.control = 0x70;
- state->mmu.translation_table_base = 0xDEADC0DE;
- state->mmu.domain_access_control = 0xDEADC0DE;
- state->mmu.fault_status = 0;
- state->mmu.fault_address = 0;
- state->mmu.process_id = 0;
-
- desc = &sa11xx_mmu_desc;
- if (mmu_tlb_init (I_TLB (), desc->i_tlb)) {
- ERROR_LOG(ARM11, "i_tlb init %d\n", -1);
- goto i_tlb_init_error;
- }
-
- c_desc = &desc->i_cache;
- if (mmu_cache_init (I_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "i_cache init %d\n", -1);
- goto i_cache_init_error;
- }
-
- if (mmu_tlb_init (D_TLB (), desc->d_tlb)) {
- ERROR_LOG(ARM11, "d_tlb init %d\n", -1);
- goto d_tlb_init_error;
- }
-
- c_desc = &desc->main_d_cache;
- if (mmu_cache_init (MAIN_D_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "main_d_cache init %d\n", -1);
- goto main_d_cache_init_error;
- }
-
- c_desc = &desc->mini_d_cache;
- if (mmu_cache_init (MINI_D_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "mini_d_cache init %d\n", -1);
- goto mini_d_cache_init_error;
- }
-
- if (mmu_wb_init (WB (), desc->wb.num, desc->wb.nb)) {
- ERROR_LOG(ARM11, "wb init %d\n", -1);
- goto wb_init_error;
- }
-
- if (mmu_rb_init (RB (), desc->rb)) {
- ERROR_LOG(ARM11, "rb init %d\n", -1);
- goto rb_init_error;
- }
- return 0;
-
- rb_init_error:
- mmu_wb_exit (WB ());
- wb_init_error:
- mmu_cache_exit (MINI_D_CACHE ());
- mini_d_cache_init_error:
- mmu_cache_exit (MAIN_D_CACHE ());
- main_d_cache_init_error:
- mmu_tlb_exit (D_TLB ());
- d_tlb_init_error:
- mmu_cache_exit (I_CACHE ());
- i_cache_init_error:
- mmu_tlb_exit (I_TLB ());
- i_tlb_init_error:
- return -1;
-}
-
-void
-sa_mmu_exit (ARMul_State * state)
-{
- mmu_rb_exit (RB ());
- mmu_wb_exit (WB ());
- mmu_cache_exit (MINI_D_CACHE ());
- mmu_cache_exit (MAIN_D_CACHE ());
- mmu_tlb_exit (D_TLB ());
- mmu_cache_exit (I_CACHE ());
- mmu_tlb_exit (I_TLB ());
-};
-
-
-static fault_t
-sa_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr)
-{
- fault_t fault;
- tlb_entry_t *tlb;
- cache_line_t *cache;
- int c; //cache bit
- ARMword pa; //physical addr
-
- static int debug_count = 0; //used for debug
-
- DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- if (MMU_Enabled) {
- /*align check */
- if ((va & (WORD_SIZE - 1)) && MMU_Aligned) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
- else
- va &= ~(WORD_SIZE - 1);
-
- /*translate tlb */
- fault = translate (state, va, I_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
-
- /*check access */
- fault = check_access (state, va, tlb, 1);
- if (fault) {
- DEBUG_LOG(ARM11, "check_fault\n");
- return fault;
- }
- }
-
- /*search cache no matter MMU enabled/disabled */
- cache = mmu_cache_search (state, I_CACHE (), va);
- if (cache) {
- *instr = cache->data[va_cache_index (va, I_CACHE ())];
- return NO_FAULT;
- }
-
- /*if MMU disabled or C flag is set alloc cache */
- if (MMU_Disabled) {
- c = 1;
- pa = va;
- }
- else {
- c = tlb_c_flag (tlb);
- pa = tlb_va_to_pa (tlb, va);
- }
-
- if (c) {
- int index;
-
- debug_count++;
- cache = mmu_cache_alloc (state, I_CACHE (), va, pa);
- index = va_cache_index (va, I_CACHE ());
- *instr = cache->data[va_cache_index (va, I_CACHE ())];
- }
- else
- //*instr = mem_read_word (state, pa);
- bus_read(32, pa, instr);
-
- return NO_FAULT;
-};
-
-
-
-static fault_t
-sa_mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- //ARMword temp,offset;
- fault_t fault;
- fault = sa_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE);
- return fault;
-}
-
-static fault_t
-sa_mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- //ARMword temp,offset;
- fault_t fault;
- fault = sa_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE);
- return fault;
-}
-
-static fault_t
-sa_mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data)
-{
- return sa_mmu_read (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-
-
-
-static fault_t
-sa_mmu_read (ARMul_State * state, ARMword va, ARMword * data,
- ARMword datatype)
-{
- fault_t fault;
- rb_entry_t *rb;
- tlb_entry_t *tlb;
- cache_line_t *cache;
- ARMword pa, real_va, temp, offset;
-
- DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- real_va = va;
- /*if MMU disabled, memory_read */
- if (MMU_Disabled) {
- //*data = mem_read_word(state, va);
- if (datatype == ARM_BYTE_TYPE)
- //*data = mem_read_byte (state, va);
- bus_read(8, va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //*data = mem_read_halfword (state, va);
- bus_read(16, va, data);
- else if (datatype == ARM_WORD_TYPE)
- //*data = mem_read_word (state, va);
- bus_read(32, va, data);
- else {
- printf ("SKYEYE:1 sa_mmu_read error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
-
- return NO_FAULT;
- }
-
- /*align check */
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- } // else
-
- va &= ~(WORD_SIZE - 1);
-
- /*translate va to tlb */
- fault = translate (state, va, D_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
- /*check access permission */
- fault = check_access (state, va, tlb, 1);
- if (fault)
- return fault;
- /*search in read buffer */
- rb = mmu_rb_search (RB (), va);
- if (rb) {
- if (rb->fault)
- return rb->fault;
- *data = rb->data[(va & (rb_masks[rb->type] - 1)) >> WORD_SHT];
- goto datatrans;
- //return 0;
- };
- /*search main cache */
- cache = mmu_cache_search (state, MAIN_D_CACHE (), va);
- if (cache) {
- *data = cache->data[va_cache_index (va, MAIN_D_CACHE ())];
- goto datatrans;
- //return 0;
- }
- /*search mini cache */
- cache = mmu_cache_search (state, MINI_D_CACHE (), va);
- if (cache) {
- *data = cache->data[va_cache_index (va, MINI_D_CACHE ())];
- goto datatrans;
- //return 0;
- }
-
- /*get phy_addr */
- pa = tlb_va_to_pa (tlb, va);
- if ((pa >= 0xe0000000) && (pa < 0xe8000000)) {
- if (tlb_c_flag (tlb)) {
- if (tlb_b_flag (tlb)) {
- mmu_cache_soft_flush (state, MAIN_D_CACHE (),
- pa);
- }
- else {
- mmu_cache_soft_flush (state, MINI_D_CACHE (),
- pa);
- }
- }
- return NO_FAULT;
- }
-
- /*if Buffer, drain Write Buffer first */
- if (tlb_b_flag (tlb))
- mmu_wb_drain_all (state, WB ());
-
- /*alloc cache or mem_read */
- if (tlb_c_flag (tlb) && MMU_DCacheEnabled) {
- cache_s *cache_t;
-
- if (tlb_b_flag (tlb))
- cache_t = MAIN_D_CACHE ();
- else
- cache_t = MINI_D_CACHE ();
- cache = mmu_cache_alloc (state, cache_t, va, pa);
- *data = cache->data[va_cache_index (va, cache_t)];
- }
- else {
- //*data = mem_read_word(state, pa);
- if (datatype == ARM_BYTE_TYPE)
- //*data = mem_read_byte (state, pa | (real_va & 3));
- bus_read(8, pa | (real_va & 3), data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //*data = mem_read_halfword (state, pa | (real_va & 2));
- bus_read(16, pa | (real_va & 2), data);
- else if (datatype == ARM_WORD_TYPE)
- //*data = mem_read_word (state, pa);
- bus_read(32, pa, data);
- else {
- printf ("SKYEYE:2 sa_mmu_read error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
- return NO_FAULT;
- }
-
-
- datatrans:
- if (datatype == ARM_HALFWORD_TYPE) {
- temp = *data;
- offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */
- *data = (temp >> offset) & 0xffff;
- }
- else if (datatype == ARM_BYTE_TYPE) {
- temp = *data;
- offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */
- *data = (temp >> offset & 0xffL);
- }
- end:
- return NO_FAULT;
-}
-
-
-static fault_t
-sa_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- return sa_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE);
-}
-
-static fault_t
-sa_mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- return sa_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE);
-}
-
-static fault_t
-sa_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data)
-{
- return sa_mmu_write (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-
-
-static fault_t
-sa_mmu_write (ARMul_State * state, ARMword va, ARMword data, ARMword datatype)
-{
- tlb_entry_t *tlb;
- cache_line_t *cache;
- int b;
- ARMword pa, real_va;
- fault_t fault;
-
- DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data);
- va = mmu_pid_va_map (va);
- real_va = va;
-
- /*search instruction cache */
- cache = mmu_cache_search (state, I_CACHE (), va);
- if (cache) {
- update_cache (state, va, data, datatype, cache, I_CACHE (),
- real_va);
- }
-
- if (MMU_Disabled) {
- //mem_write_word(state, va, data);
- if (datatype == ARM_BYTE_TYPE)
- //mem_write_byte (state, va, data);
- bus_write(8, va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //mem_write_halfword (state, va, data);
- bus_write(16, va, data);
- else if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, va, data);
- bus_write(32, va, data);
- else {
- printf ("SKYEYE:1 sa_mmu_write error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
-
- return NO_FAULT;
- }
- /*align check */
- //if ((va & (WORD_SIZE - 1)) && MMU_Aligned){
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- } //else
- va &= ~(WORD_SIZE - 1);
- /*tlb translate */
- fault = translate (state, va, D_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
- /*tlb check access */
- fault = check_access (state, va, tlb, 0);
- if (fault) {
- DEBUG_LOG(ARM11, "check_access\n");
- return fault;
- }
- /*search main cache */
- cache = mmu_cache_search (state, MAIN_D_CACHE (), va);
- if (cache) {
- update_cache (state, va, data, datatype, cache,
- MAIN_D_CACHE (), real_va);
- }
- else {
- /*search mini cache */
- cache = mmu_cache_search (state, MINI_D_CACHE (), va);
- if (cache) {
- update_cache (state, va, data, datatype, cache,
- MINI_D_CACHE (), real_va);
- }
- }
-
- if (!cache) {
- b = tlb_b_flag (tlb);
- pa = tlb_va_to_pa (tlb, va);
- if (b) {
- if (MMU_WBEnabled) {
- if (datatype == ARM_WORD_TYPE)
- mmu_wb_write_bytes (state, WB (), pa,
- (ARMbyte*)&data, 4);
- else if (datatype == ARM_HALFWORD_TYPE)
- mmu_wb_write_bytes (state, WB (),
- (pa |
- (real_va & 2)),
- (ARMbyte*)&data, 2);
- else if (datatype == ARM_BYTE_TYPE)
- mmu_wb_write_bytes (state, WB (),
- (pa |
- (real_va & 3)),
- (ARMbyte*)&data, 1);
-
- }
- else {
- if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, pa, data);
- bus_write(32, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- /*
- mem_write_halfword (state,
- (pa |
- (real_va & 2)),
- data);
- */
- bus_write(16, pa | (real_va & 2), data);
- else if (datatype == ARM_BYTE_TYPE)
- /*
- mem_write_byte (state,
- (pa | (real_va & 3)),
- data);
- */
- bus_write(8, pa | (real_va & 3), data);
- }
- }
- else {
- mmu_wb_drain_all (state, WB ());
-
- if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, pa, data);
- bus_write(32, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- /*
- mem_write_halfword (state,
- (pa | (real_va & 2)),
- data);
- */
- bus_write(16, pa | (real_va & 2), data);
- else if (datatype == ARM_BYTE_TYPE)
- /*
- mem_write_byte (state, (pa | (real_va & 3)),
- data);
- */
- bus_write(8, pa | (real_va & 3), data);
- }
- }
- return NO_FAULT;
-}
-
-static fault_t
-update_cache (ARMul_State * state, ARMword va, ARMword data, ARMword datatype,
- cache_line_t * cache, cache_s * cache_t, ARMword real_va)
-{
- ARMword temp, offset;
-
- ARMword index = va_cache_index (va, cache_t);
-
- //cache->data[index] = data;
-
- if (datatype == ARM_WORD_TYPE)
- cache->data[index] = data;
- else if (datatype == ARM_HALFWORD_TYPE) {
- temp = cache->data[index];
- offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */
- cache->data[index] =
- (temp & ~(0xffffL << offset)) | ((data & 0xffffL) <<
- offset);
- }
- else if (datatype == ARM_BYTE_TYPE) {
- temp = cache->data[index];
- offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */
- cache->data[index] =
- (temp & ~(0xffL << offset)) | ((data & 0xffL) <<
- offset);
- }
-
- if (index < (cache_t->width >> (WORD_SHT + 1)))
- cache->tag |= TAG_FIRST_HALF_DIRTY;
- else
- cache->tag |= TAG_LAST_HALF_DIRTY;
-
- return NO_FAULT;
-}
-
-ARMword
-sa_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value)
-{
- mmu_regnum_t creg = (mmu_regnum_t)(BITS (16, 19) & 15);
- ARMword data;
-
- switch (creg) {
- case MMU_ID:
-// printf("mmu_mrc read ID ");
- data = 0x41007100; /* v3 */
- data = state->cpu->cpu_val;
- break;
- case MMU_CONTROL:
-// printf("mmu_mrc read CONTROL");
- data = state->mmu.control;
- break;
- case MMU_TRANSLATION_TABLE_BASE:
-// printf("mmu_mrc read TTB ");
- data = state->mmu.translation_table_base;
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
-// printf("mmu_mrc read DACR ");
- data = state->mmu.domain_access_control;
- break;
- case MMU_FAULT_STATUS:
-// printf("mmu_mrc read FSR ");
- data = state->mmu.fault_status;
- break;
- case MMU_FAULT_ADDRESS:
-// printf("mmu_mrc read FAR ");
- data = state->mmu.fault_address;
- break;
- case MMU_PID:
- data = state->mmu.process_id;
- default:
- printf ("mmu_mrc read UNKNOWN - reg %d\n", creg);
- data = 0;
- break;
- }
-// printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]);
- *value = data;
- return data;
-}
-
-void
-sa_mmu_cache_ops (ARMul_State * state, ARMword instr, ARMword value)
-{
- int CRm, OPC_2;
-
- CRm = BITS (0, 3);
- OPC_2 = BITS (5, 7);
-
- if (OPC_2 == 0 && CRm == 7) {
- mmu_cache_invalidate_all (state, I_CACHE ());
- mmu_cache_invalidate_all (state, MAIN_D_CACHE ());
- mmu_cache_invalidate_all (state, MINI_D_CACHE ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 5) {
- mmu_cache_invalidate_all (state, I_CACHE ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 6) {
- mmu_cache_invalidate_all (state, MAIN_D_CACHE ());
- mmu_cache_invalidate_all (state, MINI_D_CACHE ());
- return;
- }
-
- if (OPC_2 == 1 && CRm == 6) {
- mmu_cache_invalidate (state, MAIN_D_CACHE (), value);
- mmu_cache_invalidate (state, MINI_D_CACHE (), value);
- return;
- }
-
- if (OPC_2 == 1 && CRm == 0xa) {
- mmu_cache_clean (state, MAIN_D_CACHE (), value);
- mmu_cache_clean (state, MINI_D_CACHE (), value);
- return;
- }
-
- if (OPC_2 == 4 && CRm == 0xa) {
- mmu_wb_drain_all (state, WB ());
- return;
- }
- ERROR_LOG(ARM11, "Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm);
-}
-
-static void
-sa_mmu_tlb_ops (ARMul_State * state, ARMword instr, ARMword value)
-{
- int CRm, OPC_2;
-
- CRm = BITS (0, 3);
- OPC_2 = BITS (5, 7);
-
-
- if (OPC_2 == 0 && CRm == 0x7) {
- mmu_tlb_invalidate_all (state, I_TLB ());
- mmu_tlb_invalidate_all (state, D_TLB ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 0x5) {
- mmu_tlb_invalidate_all (state, I_TLB ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 0x6) {
- mmu_tlb_invalidate_all (state, D_TLB ());
- return;
- }
-
- if (OPC_2 == 1 && CRm == 0x6) {
- mmu_tlb_invalidate_entry (state, D_TLB (), value);
- return;
- }
-
- ERROR_LOG(ARM11, "Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm);
-}
-
-static void
-sa_mmu_rb_ops (ARMul_State * state, ARMword instr, ARMword value)
-{
- int CRm, OPC_2;
-
- CRm = BITS (0, 3);
- OPC_2 = BITS (5, 7);
-
- if (OPC_2 == 0x0 && CRm == 0x0) {
- mmu_rb_invalidate_all (RB ());
- return;
- }
-
- if (OPC_2 == 0x2) {
- int idx = CRm & 0x3;
- int type = ((CRm >> 2) & 0x3) + 1;
-
- if ((idx < 4) && (type < 4))
- mmu_rb_load (state, RB (), idx, type, value);
- return;
- }
-
- if ((OPC_2 == 1) && (CRm < 4)) {
- mmu_rb_invalidate_entry (RB (), CRm);
- return;
- }
-
- ERROR_LOG(ARM11, "Unknow OPC_2 = %x CRm = %x\n", OPC_2, CRm);
-}
-
-static ARMword
-sa_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value)
-{
- mmu_regnum_t creg = (mmu_regnum_t)(BITS (16, 19) & 15);
- if (!strncmp (state->cpu->cpu_arch_name, "armv4", 5)) {
- switch (creg) {
- case MMU_CONTROL:
-// printf("mmu_mcr wrote CONTROL ");
- state->mmu.control = (value | 0x70) & 0xFFFD;
- break;
- case MMU_TRANSLATION_TABLE_BASE:
-// printf("mmu_mcr wrote TTB ");
- state->mmu.translation_table_base =
- value & 0xFFFFC000;
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
-// printf("mmu_mcr wrote DACR ");
- state->mmu.domain_access_control = value;
- break;
-
- case MMU_FAULT_STATUS:
- state->mmu.fault_status = value & 0xFF;
- break;
- case MMU_FAULT_ADDRESS:
- state->mmu.fault_address = value;
- break;
-
- case MMU_CACHE_OPS:
- sa_mmu_cache_ops (state, instr, value);
- break;
- case MMU_TLB_OPS:
- sa_mmu_tlb_ops (state, instr, value);
- break;
- case MMU_SA_RB_OPS:
- sa_mmu_rb_ops (state, instr, value);
- break;
- case MMU_SA_DEBUG:
- break;
- case MMU_SA_CP15_R15:
- break;
- case MMU_PID:
- //2004-06-06 lyh, bug provided by wen ye wenye@cs.ucsb.edu
- state->mmu.process_id = value & 0x7e000000;
- break;
-
- default:
- printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
- break;
- }
- }
- return 0;
-}
-
-//teawater add for arm2x86 2005.06.24-------------------------------------------
-static int
-sa_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr, ARMword * phys_addr)
-{
- fault_t fault;
- tlb_entry_t *tlb;
-
- virt_addr = mmu_pid_va_map (virt_addr);
- if (MMU_Enabled) {
-
- /*align check */
- if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
- else
- virt_addr &= ~(WORD_SIZE - 1);
-
- /*translate tlb */
- fault = translate (state, virt_addr, I_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
-
- /*check access */
- fault = check_access (state, virt_addr, tlb, 1);
- if (fault) {
- DEBUG_LOG(ARM11, "check_fault\n");
- return fault;
- }
- }
-
- if (MMU_Disabled) {
- *phys_addr = virt_addr;
- }
- else {
- *phys_addr = tlb_va_to_pa (tlb, virt_addr);
- }
-
- return (0);
-}
-
-//AJ2D--------------------------------------------------------------------------
-
-/*sa mmu_ops_t*/
-mmu_ops_t sa_mmu_ops = {
- sa_mmu_init,
- sa_mmu_exit,
- sa_mmu_read_byte,
- sa_mmu_write_byte,
- sa_mmu_read_halfword,
- sa_mmu_write_halfword,
- sa_mmu_read_word,
- sa_mmu_write_word,
- sa_mmu_load_instr,
- sa_mmu_mcr,
- sa_mmu_mrc,
-//teawater add for arm2x86 2005.06.24-------------------------------------------
- sa_mmu_v2p_dbct,
-//AJ2D--------------------------------------------------------------------------
-};
diff --git a/src/core/arm/interpreter/mmu/sa_mmu.h b/src/core/arm/interpreter/mmu/sa_mmu.h
deleted file mode 100644
index 64b1c5470c..0000000000
--- a/src/core/arm/interpreter/mmu/sa_mmu.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- sa_mmu.h - StrongARM Memory Management Unit emulation.
- ARMulator extensions for SkyEye.
- <lyhost@263.net>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#ifndef _SA_MMU_H_
-#define _SA_MMU_H_
-
-
-/**
- * The interface of read data from bus
- */
-int bus_read(short size, int addr, uint32_t * value);
-
-/**
- * The interface of write data from bus
- */
-int bus_write(short size, int addr, uint32_t value);
-
-
-typedef struct sa_mmu_s
-{
- tlb_s i_tlb;
- cache_s i_cache;
-
- tlb_s d_tlb;
- cache_s main_d_cache;
- cache_s mini_d_cache;
- rb_s rb_t;
- wb_s wb_t;
-} sa_mmu_t;
-
-#define I_TLB() (&state->mmu.u.sa_mmu.i_tlb)
-#define I_CACHE() (&state->mmu.u.sa_mmu.i_cache)
-
-#define D_TLB() (&state->mmu.u.sa_mmu.d_tlb)
-#define MAIN_D_CACHE() (&state->mmu.u.sa_mmu.main_d_cache)
-#define MINI_D_CACHE() (&state->mmu.u.sa_mmu.mini_d_cache)
-#define WB() (&state->mmu.u.sa_mmu.wb_t)
-#define RB() (&state->mmu.u.sa_mmu.rb_t)
-
-extern mmu_ops_t sa_mmu_ops;
-#endif /*_SA_MMU_H_*/
diff --git a/src/core/arm/interpreter/mmu/tlb.cpp b/src/core/arm/interpreter/mmu/tlb.cpp
deleted file mode 100644
index 88c2a8bc54..0000000000
--- a/src/core/arm/interpreter/mmu/tlb.cpp
+++ /dev/null
@@ -1,307 +0,0 @@
-#include <assert.h>
-
-#include "core/arm/skyeye_common/armdefs.h"
-
-ARMword tlb_masks[] = {
- 0x00000000, /* TLB_INVALID */
- 0xFFFFF000, /* TLB_SMALLPAGE */
- 0xFFFF0000, /* TLB_LARGEPAGE */
- 0xFFF00000, /* TLB_SECTION */
- 0xFFFFF000, /*TLB_ESMALLPAGE, have TEX attirbute, only for XScale */
- 0xFFFFFC00 /* TLB_TINYPAGE */
-};
-
-/* This function encodes table 8-2 Interpreting AP bits,
- returning non-zero if access is allowed. */
-static int
-check_perms (ARMul_State * state, int ap, int read)
-{
- int s, r, user;
-
- s = state->mmu.control & CONTROL_SYSTEM;
- r = state->mmu.control & CONTROL_ROM;
- //chy 2006-02-15 , should consider system mode, don't conside 26bit mode
- user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE);
-
- switch (ap) {
- case 0:
- return read && ((s && !user) || r);
- case 1:
- return !user;
- case 2:
- return read || !user;
- case 3:
- return 1;
- }
- return 0;
-}
-
-fault_t
-check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
- int read)
-{
- int access;
-
- state->mmu.last_domain = tlb->domain;
- access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3;
- if ((access == 0) || (access == 2)) {
- /* It's unclear from the documentation whether this
- should always raise a section domain fault, or if
- it should be a page domain fault in the case of an
- L1 that describes a page table. In the ARM710T
- datasheets, "Figure 8-9: Sequence for checking faults"
- seems to indicate the former, while "Table 8-4: Priority
- encoding of fault status" gives a value for FS[3210] in
- the event of a domain fault for a page. Hmm. */
- return SECTION_DOMAIN_FAULT;
- }
- if (access == 1) {
- /* client access - check perms */
- int subpage, ap;
-
- switch (tlb->mapping) {
- /*ks 2004-05-09
- * only for XScale
- * Extend Small Page(ESP) Format
- * 31-12 bits the base addr of ESP
- * 11-10 bits SBZ
- * 9-6 bits TEX
- * 5-4 bits AP
- * 3 bit C
- * 2 bit B
- * 1-0 bits 11
- * */
- case TLB_ESMALLPAGE: //xj
- subpage = 0;
- //printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr );
- break;
-
- case TLB_TINYPAGE:
- subpage = 0;
- //printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr );
- break;
-
- case TLB_SMALLPAGE:
- subpage = (virt_addr >> 10) & 3;
- break;
- case TLB_LARGEPAGE:
- subpage = (virt_addr >> 14) & 3;
- break;
- case TLB_SECTION:
- subpage = 3;
- break;
- default:
- assert (0);
- subpage = 0; /* cleans a warning */
- }
- ap = (tlb->perms >> (subpage * 2 + 4)) & 3;
- if (!check_perms (state, ap, read)) {
- if (tlb->mapping == TLB_SECTION) {
- return SECTION_PERMISSION_FAULT;
- }
- else {
- return SUBPAGE_PERMISSION_FAULT;
- }
- }
- }
- else { /* access == 3 */
- /* manager access - don't check perms */
- }
- return NO_FAULT;
-}
-
-fault_t
-translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
- tlb_entry_t ** tlb)
-{
- *tlb = mmu_tlb_search (state, tlb_t, virt_addr);
- if (!*tlb) {
- /* walk the translation tables */
- ARMword l1addr, l1desc;
- tlb_entry_t entry;
-
- l1addr = state->mmu.translation_table_base & 0xFFFFC000;
- l1addr = (l1addr | (virt_addr >> 18)) & ~3;
- //l1desc = mem_read_word (state, l1addr);
- bus_read(32, l1addr, &l1desc);
- switch (l1desc & 3) {
- case 0:
- /*
- * according to Figure 3-9 Sequence for checking faults in arm manual,
- * section translation fault should be returned here.
- */
- {
- return SECTION_TRANSLATION_FAULT;
- }
- case 3:
- /* fine page table */
- // dcl 2006-01-08
- {
- ARMword l2addr, l2desc;
-
- l2addr = l1desc & 0xFFFFF000;
- l2addr = (l2addr |
- ((virt_addr & 0x000FFC00) >> 8)) &
- ~3;
- //l2desc = mem_read_word (state, l2addr);
- bus_read(32, l2addr, &l2desc);
-
- entry.virt_addr = virt_addr;
- entry.phys_addr = l2desc;
- entry.perms = l2desc & 0x00000FFC;
- entry.domain = (l1desc >> 5) & 0x0000000F;
- switch (l2desc & 3) {
- case 0:
- state->mmu.last_domain = entry.domain;
- return PAGE_TRANSLATION_FAULT;
- case 3:
- entry.mapping = TLB_TINYPAGE;
- break;
- case 1:
- // this is untested
- entry.mapping = TLB_LARGEPAGE;
- break;
- case 2:
- // this is untested
- entry.mapping = TLB_SMALLPAGE;
- break;
- }
- }
- break;
- case 1:
- /* coarse page table */
- {
- ARMword l2addr, l2desc;
-
- l2addr = l1desc & 0xFFFFFC00;
- l2addr = (l2addr |
- ((virt_addr & 0x000FF000) >> 10)) &
- ~3;
- //l2desc = mem_read_word (state, l2addr);
- bus_read(32, l2addr, &l2desc);
-
- entry.virt_addr = virt_addr;
- entry.phys_addr = l2desc;
- entry.perms = l2desc & 0x00000FFC;
- entry.domain = (l1desc >> 5) & 0x0000000F;
- //printf("SKYEYE:PAGE virt_addr = %x,l1desc=%x,phys_addr=%x\n",virt_addr,l1desc,entry.phys_addr);
- //chy 2003-09-02 for xscale
- switch (l2desc & 3) {
- case 0:
- state->mmu.last_domain = entry.domain;
- return PAGE_TRANSLATION_FAULT;
- case 3:
- if (!state->is_XScale) {
- state->mmu.last_domain =
- entry.domain;
- return PAGE_TRANSLATION_FAULT;
- };
- //ks 2004-05-09 xscale shold use Extend Small Page
- //entry.mapping = TLB_SMALLPAGE;
- entry.mapping = TLB_ESMALLPAGE; //xj
- break;
- case 1:
- entry.mapping = TLB_LARGEPAGE;
- break;
- case 2:
- entry.mapping = TLB_SMALLPAGE;
- break;
- }
- }
- break;
- case 2:
- /* section */
- //printf("SKYEYE:WARNING: not implement section mapping incompletely\n");
- //printf("SKYEYE:SECTION virt_addr = %x,l1desc=%x\n",virt_addr,l1desc);
- //return SECTION_DOMAIN_FAULT;
- //#if 0
- entry.virt_addr = virt_addr;
- entry.phys_addr = l1desc;
- entry.perms = l1desc & 0x00000C0C;
- entry.domain = (l1desc >> 5) & 0x0000000F;
- entry.mapping = TLB_SECTION;
- break;
- //#endif
- }
- entry.virt_addr &= tlb_masks[entry.mapping];
- entry.phys_addr &= tlb_masks[entry.mapping];
-
- /* place entry in the tlb */
- *tlb = &tlb_t->entrys[tlb_t->cycle];
- tlb_t->cycle = (tlb_t->cycle + 1) % tlb_t->num;
- **tlb = entry;
- }
- state->mmu.last_domain = (*tlb)->domain;
- return NO_FAULT;
-}
-
-int
-mmu_tlb_init (tlb_s * tlb_t, int num)
-{
- tlb_entry_t *e;
- int i;
-
- e = (tlb_entry_t *) malloc (sizeof (*e) * num);
- if (e == NULL) {
- ERROR_LOG(ARM11, "malloc size %d\n", sizeof (*e) * num);
- goto tlb_malloc_error;
- }
- tlb_t->entrys = e;
- for (i = 0; i < num; i++, e++)
- e->mapping = TLB_INVALID;
- tlb_t->cycle = 0;
- tlb_t->num = num;
- return 0;
-
- tlb_malloc_error:
- return -1;
-}
-
-void
-mmu_tlb_exit (tlb_s * tlb_t)
-{
- free (tlb_t->entrys);
-};
-
-void
-mmu_tlb_invalidate_all (ARMul_State * state, tlb_s * tlb_t)
-{
- int entry;
-
- for (entry = 0; entry < tlb_t->num; entry++) {
- tlb_t->entrys[entry].mapping = TLB_INVALID;
- }
- tlb_t->cycle = 0;
-}
-
-void
-mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr)
-{
- tlb_entry_t *tlb;
-
- tlb = mmu_tlb_search (state, tlb_t, addr);
- if (tlb) {
- tlb->mapping = TLB_INVALID;
- }
-}
-
-tlb_entry_t *
-mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t, ARMword virt_addr)
-{
- int entry;
-
- for (entry = 0; entry < tlb_t->num; entry++) {
- tlb_entry_t *tlb;
- ARMword mask;
-
- tlb = &(tlb_t->entrys[entry]);
- if (tlb->mapping == TLB_INVALID) {
- continue;
- }
- mask = tlb_masks[tlb->mapping];
- if ((virt_addr & mask) == (tlb->virt_addr & mask)) {
- return tlb;
- }
- }
- return NULL;
-}
diff --git a/src/core/arm/interpreter/mmu/tlb.h b/src/core/arm/interpreter/mmu/tlb.h
deleted file mode 100644
index 40856567bb..0000000000
--- a/src/core/arm/interpreter/mmu/tlb.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef _MMU_TLB_H_
-#define _MMU_TLB_H_
-
-typedef enum tlb_mapping_t
-{
- TLB_INVALID = 0,
- TLB_SMALLPAGE = 1,
- TLB_LARGEPAGE = 2,
- TLB_SECTION = 3,
- TLB_ESMALLPAGE = 4,
- TLB_TINYPAGE = 5
-} tlb_mapping_t;
-
-extern ARMword tlb_masks[];
-
-/* Permissions bits in a TLB entry:
- *
- * 31 12 11 10 9 8 7 6 5 4 3 2 1 0
- * +-------------+-----+-----+-----+-----+---+---+-------+
- * Page:| | ap3 | ap2 | ap1 | ap0 | C | B | |
- * +-------------+-----+-----+-----+-----+---+---+-------+
- *
- * 31 12 11 10 9 4 3 2 1 0
- * +-------------+-----+-----------------+---+---+-------+
- * Section: | | AP | | C | B | |
- * +-------------+-----+-----------------+---+---+-------+
- */
-
-/*
-section:
- section base address [31:20]
- AP - table 8-2, page 8-8
- domain
- C,B
-
-page:
- page base address [31:16] or [31:12]
- ap[3:0]
- domain (from L1)
- C,B
-*/
-
-
-typedef struct tlb_entry_t
-{
- ARMword virt_addr;
- ARMword phys_addr;
- ARMword perms;
- ARMword domain;
- tlb_mapping_t mapping;
-} tlb_entry_t;
-
-typedef struct tlb_s
-{
- int num; /*num of tlb entry */
- int cycle; /*current tlb cycle */
- tlb_entry_t *entrys;
-} tlb_s;
-
-
-#define tlb_c_flag(tlb) \
- ((tlb)->perms & 0x8)
-#define tlb_b_flag(tlb) \
- ((tlb)->perms & 0x4)
-
-#define tlb_va_to_pa(tlb, va) ((tlb->phys_addr & tlb_masks[tlb->mapping]) | (va & ~tlb_masks[tlb->mapping]))
-fault_t
-check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
- int read);
-
-fault_t
-translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
- tlb_entry_t ** tlb);
-
-int mmu_tlb_init (tlb_s * tlb_t, int num);
-
-void mmu_tlb_exit (tlb_s * tlb_t);
-
-void mmu_tlb_invalidate_all (ARMul_State * state, tlb_s * tlb_t);
-
-void
-mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr);
-
-tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t,
- ARMword virt_addr);
-
-#endif /*_MMU_TLB_H_*/
diff --git a/src/core/arm/interpreter/mmu/wb.cpp b/src/core/arm/interpreter/mmu/wb.cpp
deleted file mode 100644
index 5ddda41ee3..0000000000
--- a/src/core/arm/interpreter/mmu/wb.cpp
+++ /dev/null
@@ -1,149 +0,0 @@
-#include "core/arm/skyeye_common/armdefs.h"
-
-/* wb_init
- * @wb_t :wb_t to init
- * @num :num of entrys
- * @nb :num of byte of each entry
- *
- * $ -1:error
- * 0:ok
- * */
-int
-mmu_wb_init (wb_s * wb_t, int num, int nb)
-{
- int i;
- wb_entry_t *entrys, *wb;
-
- entrys = (wb_entry_t *) malloc (sizeof (*entrys) * num);
- if (entrys == NULL) {
- ERROR_LOG(ARM11, "malloc size %d\n", sizeof (*entrys) * num);
- goto entrys_malloc_error;
- }
-
- for (wb = entrys, i = 0; i < num; i++, wb++) {
- /*chy 2004-06-06, fix bug found by wenye@cs.ucsb.edu */
- //wb->data = (ARMword *)malloc(sizeof(ARMword) * nb);
- wb->data = (ARMbyte *) malloc (nb);
- if (wb->data == NULL) {
- ERROR_LOG(ARM11, "malloc size of %d\n", nb);
- goto data_malloc_error;
- }
-
- };
-
- wb_t->first = wb_t->last = wb_t->used = 0;
- wb_t->num = num;
- wb_t->nb = nb;
- wb_t->entrys = entrys;
- return 0;
-
- data_malloc_error:
- while (--i >= 0)
- free (entrys[i].data);
- free (entrys);
- entrys_malloc_error:
- return -1;
-};
-
-/* wb_exit
- * @wb_t :wb_t to exit
- * */
-void
-mmu_wb_exit (wb_s * wb_t)
-{
- int i;
- wb_entry_t *wb;
-
- wb = wb_t->entrys;
- for (i = 0; i < wb_t->num; i++, wb++) {
- free (wb->data);
- }
- free (wb_t->entrys);
-};
-
-/* wb_write_words :put words in Write Buffer
- * @state: ARMul_State
- * @wb_t: write buffer
- * @pa: physical address
- * @data: data ptr
- * @n number of word to write
- *
- * Note: write buffer merge is not implemented, can be done late
- * */
-void
-mmu_wb_write_bytes (ARMul_State * state, wb_s * wb_t, ARMword pa,
- ARMbyte * data, int n)
-{
- int i;
- wb_entry_t *wb;
-
- while (n) {
- if (wb_t->num == wb_t->used) {
- /*clean the last wb entry */
- ARMword t;
-
- wb = &wb_t->entrys[wb_t->last];
- t = wb->pa;
- for (i = 0; i < wb->nb; i++) {
- //mem_write_byte (state, t, wb->data[i]);
- bus_write(8, t, wb->data[i]);
- //t += WORD_SIZE;
- t++;
- }
- wb_t->last++;
- if (wb_t->last == wb_t->num)
- wb_t->last = 0;
- wb_t->used--;
- }
-
- wb = &wb_t->entrys[wb_t->first];
- i = (n < wb_t->nb) ? n : wb_t->nb;
-
- wb->pa = pa;
- //pa += i << WORD_SHT;
- pa += i;
-
- wb->nb = i;
- //memcpy(wb->data, data, i << WORD_SHT);
- memcpy (wb->data, data, i);
- data += i;
- n -= i;
- wb_t->first++;
- if (wb_t->first == wb_t->num)
- wb_t->first = 0;
- wb_t->used++;
- };
-//teawater add for set_dirty fflash cache function 2005.07.18-------------------
-#ifdef DBCT
- if (!skyeye_config.no_dbct) {
- tb_setdirty (state, pa, NULL);
- }
-#endif
-//AJ2D--------------------------------------------------------------------------
-}
-
-/* wb_drain_all
- * @wb_t wb_t to drain
- * */
-void
-mmu_wb_drain_all (ARMul_State * state, wb_s * wb_t)
-{
- ARMword pa;
- wb_entry_t *wb;
- int i;
-
- while (wb_t->used) {
- wb = &wb_t->entrys[wb_t->last];
- pa = wb->pa;
- for (i = 0; i < wb->nb; i++) {
- //mem_write_byte (state, pa, wb->data[i]);
- bus_write(8, pa, wb->data[i]);
- //pa += WORD_SIZE;
- pa++;
- }
- wb_t->last++;
- if (wb_t->last == wb_t->num)
- wb_t->last = 0;
- wb_t->used--;
- };
-}
diff --git a/src/core/arm/interpreter/mmu/wb.h b/src/core/arm/interpreter/mmu/wb.h
deleted file mode 100644
index 8fb7de9460..0000000000
--- a/src/core/arm/interpreter/mmu/wb.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef _MMU_WB_H_
-#define _MMU_WB_H_
-
-typedef struct wb_entry_s
-{
- ARMword pa; //phy_addr
- ARMbyte *data; //data
- int nb; //number byte to write
-} wb_entry_t;
-
-typedef struct wb_s
-{
- int num; //number of wb_entry
- int nb; //number of byte of each entry
- int first; //
- int last; //
- int used; //
- wb_entry_t *entrys;
-} wb_s;
-
-typedef struct wb_desc_s
-{
- int num;
- int nb;
-} wb_desc_t;
-
-/* wb_init
- * @wb_t :wb_t to init
- * @num :num of entrys
- * @nw :num of word of each entry
- *
- * $ -1:error
- * 0:ok
- * */
-int mmu_wb_init (wb_s * wb_t, int num, int nb);
-
-
-/* wb_exit
- * @wb_t :wb_t to exit
- * */
-void mmu_wb_exit (wb_s * wb);
-
-
-/* wb_write_bytes :put bytess in Write Buffer
- * @state: ARMul_State
- * @wb_t: write buffer
- * @pa: physical address
- * @data: data ptr
- * @n number of byte to write
- *
- * Note: write buffer merge is not implemented, can be done late
- * */
-void
-mmu_wb_write_bytess (ARMul_State * state, wb_s * wb_t, ARMword pa,
- ARMbyte * data, int n);
-
-
-/* wb_drain_all
- * @wb_t wb_t to drain
- * */
-void mmu_wb_drain_all (ARMul_State * state, wb_s * wb_t);
-
-#endif /*_MMU_WB_H_*/
diff --git a/src/core/arm/interpreter/mmu/xscale_copro.cpp b/src/core/arm/interpreter/mmu/xscale_copro.cpp
deleted file mode 100644
index cf91fd9330..0000000000
--- a/src/core/arm/interpreter/mmu/xscale_copro.cpp
+++ /dev/null
@@ -1,1391 +0,0 @@
-/*
- armmmu.c - Memory Management Unit emulation.
- ARMulator extensions for the ARM7100 family.
- Copyright (C) 1999 Ben Williamson
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <assert.h>
-#include <string.h>
-
-#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/armemu.h"
-
-/*#include "pxa.h" */
-
-/* chy 2005-09-19 */
-
-/* extern pxa270_io_t pxa270_io; */
-/* chy 2005-09-19 -----end */
-
-typedef struct xscale_mmu_desc_s
-{
- int i_tlb;
- cache_desc_t i_cache;
-
- int d_tlb;
- cache_desc_t main_d_cache;
- cache_desc_t mini_d_cache;
- //int rb; xscale has no read buffer
- wb_desc_t wb;
-} xscale_mmu_desc_t;
-
-static xscale_mmu_desc_t pxa_mmu_desc = {
- 32,
- {32, 32, 32, CACHE_WRITE_BACK},
-
- 32,
- {32, 32, 32, CACHE_WRITE_BACK},
- {32, 2, 8, CACHE_WRITE_BACK},
- {8, 16}, //for byte size,
-};
-
-//chy 2005-09-19 for cp6
-#define CR0_ICIP 0
-#define CR1_ICMR 1
-//chy 2005-09-19 ---end
-//----------- for cp14-----------------
-#define CCLKCFG 6
-#define PWRMODE 7
-typedef struct xscale_cp14_reg_s
-{
- unsigned cclkcfg; //reg6
- unsigned pwrmode; //reg7
-} xscale_cp14_reg_s;
-
-xscale_cp14_reg_s pxa_cp14_regs;
-
-//--------------------------------------
-
-static fault_t xscale_mmu_write (ARMul_State * state, ARMword va,
- ARMword data, ARMword datatype);
-static fault_t xscale_mmu_read (ARMul_State * state, ARMword va,
- ARMword * data, ARMword datatype);
-
-ARMword xscale_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value);
-ARMword xscale_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value);
-
-
-/* jeff add 2010.9.26 for pxa270 cp6*/
-#define PXA270_ICMR 0x40D00004
-#define PXA270_ICPR 0x40D00010
-#define PXA270_ICLR 0x40D00008
-//chy 2005-09-19 for xscale pxa27x cp6
-unsigned
-xscale_cp6_mrc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- //printf("SKYEYE: xscale_cp6_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,state->Reg[15], instr);
-
- switch (reg) {
- case CR0_ICIP: { // cp 6 reg 0
- //printf("cp6_mrc cr0 ICIP \n");
- /* *data = (pxa270_io.icmr & pxa270_io.icpr) & ~pxa270_io.iclr; */
- /* use bus_read get the pxa270 machine registers 2010.9.26 jeff*/
- int icmr, icpr, iclr;
- bus_read(32, PXA270_ICMR, (uint32_t*)&icmr);
- bus_read(32, PXA270_ICPR, (uint32_t*)&icpr);
- bus_read(32, PXA270_ICLR, (uint32_t*)&iclr);
- *data = (icmr & icpr) & ~iclr;
- }
- break;
- case CR1_ICMR: { // cp 6 reg 1
- //printf("cp6_mrc cr1 ICMR\n");
- /* *data = pxa270_io.icmr; */
- int icmr;
- /* use bus_read get the pxa270 machine registers 2010.9.26 jeff*/
- bus_read(32, PXA270_ICMR, (uint32_t*)&icmr);
- *data = icmr;
- }
- break;
- default:
- *data = 0;
- printf ("SKYEYE:cp6_mrc unknown cp6 regs!!!!!!\n");
- printf ("SKYEYE: xscale_cp6_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n", opcode_2, CRm, reg, state->Reg[15], instr);
- break;
- }
- return 0;
-}
-
-//chy 2005-09-19 end
-//xscale cp13 ----------------------------------------------------
-unsigned
-xscale_cp13_init (ARMul_State * state)
-{
- //printf("SKYEYE: xscale_cp13_init: begin\n");
- return 0;
-}
-
-unsigned
-xscale_cp13_exit (ARMul_State * state)
-{
- //printf("SKYEYE: xscale_cp13_exit: begin\n");
- return 0;
-}
-
-unsigned
-xscale_cp13_ldc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword data)
-{
- printf ("SKYEYE: xscale_cp13_ldc: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp13_stc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- printf ("SKYEYE: xscale_cp13_stc: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp13_mrc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- printf ("SKYEYE: xscale_cp13_mrc: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp13_mcr (ARMul_State * state, unsigned type, ARMword instr,
- ARMword data)
-{
- printf ("SKYEYE: xscale_cp13_mcr: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp13_cdp (ARMul_State * state, unsigned type, ARMword instr)
-{
- printf ("SKYEYE: xscale_cp13_cdp: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp13_read_reg (ARMul_State * state, unsigned reg, ARMword * data)
-{
- printf ("SKYEYE: xscale_cp13_read_reg: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- return 0;
- //exit(-1);
-}
-
-unsigned
-xscale_cp13_write_reg (ARMul_State * state, unsigned reg, ARMword data)
-{
- printf ("SKYEYE: xscale_cp13_write_reg: ERROR isn't existed,");
- SKYEYE_OUTREGS (stderr);
- fprintf (stderr, "\n");
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-//------------------------------------------------------------------
-//xscale cp14 ----------------------------------------------------
-unsigned
-xscale_cp14_init (ARMul_State * state)
-{
- //printf("SKYEYE: xscale_cp14_init: begin\n");
- pxa_cp14_regs.cclkcfg = 0;
- pxa_cp14_regs.pwrmode = 0;
- return 0;
-}
-
-unsigned
-xscale_cp14_exit (ARMul_State * state)
-{
- //printf("SKYEYE: xscale_cp14_exit: begin\n");
- return 0;
-}
-
-unsigned
-xscale_cp14_ldc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword data)
-{
- printf ("SKYEYE: xscale_cp14_ldc: ERROR isn't existed, reg15 0x%x\n",
- state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp14_stc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- printf ("SKYEYE: xscale_cp14_stc: ERROR isn't existed, reg15 0x%x\n",
- state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-
-unsigned
-xscale_cp14_mrc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- //printf("SKYEYE: xscale_cp14_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\
- state->Reg[15], instr);
-
- switch (reg) {
- case CCLKCFG: // cp 14 reg 6
- //printf("cp14_mrc cclkcfg \n");
- *data = pxa_cp14_regs.cclkcfg;
- break;
- case PWRMODE: // cp 14 reg 7
- //printf("cp14_mrc pwrmode \n");
- *data = pxa_cp14_regs.pwrmode;
- break;
- default:
- *data = 0;
- printf ("SKYEYE:cp14_mrc unknown cp14 regs!!!!!!\n");
- break;
- }
- return 0;
-}
-unsigned xscale_cp14_mcr (ARMul_State * state, unsigned type, ARMword instr,
- ARMword data)
-{
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- //printf("SKYEYE: xscale_cp14_mcr:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\
- state->Reg[15], instr);
-
- switch (reg) {
- case CCLKCFG: // cp 14 reg 6
- //printf("cp14_mcr cclkcfg \n");
- pxa_cp14_regs.cclkcfg = data & 0xf;
- break;
- case PWRMODE: // cp 14 reg 7
- //printf("cp14_mcr pwrmode \n");
- pxa_cp14_regs.pwrmode = data & 0x3;
- break;
- default:printf ("SKYEYE: cp14_mcr unknown cp14 regs!!!!!!\n");
- break;
- }
- return 0;
-}
-unsigned xscale_cp14_cdp (ARMul_State * state, unsigned type, ARMword instr)
-{
- printf ("SKYEYE: xscale_cp14_cdp: ERROR isn't existed, reg15 0x%x\n",
- state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-unsigned xscale_cp14_read_reg (ARMul_State * state, unsigned reg,
- ARMword * data)
-{
- printf ("SKYEYE: xscale_cp14_read_reg: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
- return 0; //No matter return value, only for compiler.
-}
-unsigned xscale_cp14_write_reg (ARMul_State * state, unsigned reg,
- ARMword data)
-{
- printf ("SKYEYE: xscale_cp14_write_reg: ERROR isn't existed, reg15 0x%x\n", state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
-
- return 0; //No matter return value, only for compiler.
-}
-
-//------------------------------------------------------------------
-//cp15 -------------------------------------
-unsigned xscale_cp15_ldc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword data)
-{
- printf ("SKYEYE: xscale_cp15_ldc: ERROR isn't existed\n");
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
-
- return 0; //No matter return value, only for compiler.
-}
-unsigned xscale_cp15_stc (ARMul_State * state, unsigned type, ARMword instr,
- ARMword * data)
-{
- printf ("SKYEYE: xscale_cp15_stc: ERROR isn't existed\n");
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
-
- return 0; //No matter return value, only for compiler.
-}
-unsigned xscale_cp15_cdp (ARMul_State * state, unsigned type, ARMword instr)
-{
- printf ("SKYEYE: xscale_cp15_cdp: ERROR isn't existed\n");
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
-
- return 0; //No matter return value, only for compiler.
-}
-unsigned xscale_cp15_read_reg (ARMul_State * state, unsigned reg,
- ARMword * data)
-{
-//chy 2003-09-03: for xsacle_cp15_cp_access_allowed
- if (reg == 15) {
- *data = state->mmu.copro_access;
- //printf("SKYEYE: xscale_cp15_read_reg: reg 0x%x,data %x\n",reg,*data);
- return 0;
- }
- printf ("SKYEYE: xscale_cp15_read_reg: reg 0x%x, ERROR isn't existed\n", reg);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
-
- return 0; //No matter return value, only for compiler.
-}
-
-//chy 2003-09-03 used by macro CP_ACCESS_ALLOWED in armemu.h
-unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
- unsigned cpnum)
-{
- unsigned data;
-
- xscale_cp15_read_reg (state, reg, &data);
- //printf("SKYEYE: cp15_cp_access_allowed data %x, cpnum %x, result %x\n", data, cpnum, (data & 1<<cpnum));
- if (data & 1 << cpnum)
- return 1;
- else
- return 0;
-}
-
-unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg,
- ARMword value)
-{
- switch (reg) {
- case MMU_FAULT_STATUS:
- //printf("SKYEYE:cp15_write_reg wrote FS val 0x%x \n",value);
- state->mmu.fault_status = value & 0x6FF;
- break;
- case MMU_FAULT_ADDRESS:
- //printf("SKYEYE:cp15_write_reg wrote FA val 0x%x \n",value);
- state->mmu.fault_address = value;
- break;
- default:
- printf ("SKYEYE: xscale_cp15_write_reg: reg 0x%x R15 %x ERROR isn't existed\n", reg, state->Reg[15]);
- SKYEYE_OUTREGS (stderr);
- // skyeye_exit (-1);
- }
- return 0;
-}
-
-unsigned
-xscale_cp15_init (ARMul_State * state)
-{
- xscale_mmu_desc_t *desc;
- cache_desc_t *c_desc;
-
- state->mmu.control = 0;
- state->mmu.translation_table_base = 0xDEADC0DE;
- state->mmu.domain_access_control = 0xDEADC0DE;
- state->mmu.fault_status = 0;
- state->mmu.fault_address = 0;
- state->mmu.process_id = 0;
- state->mmu.cache_type = 0xB1AA1AA; //0000 1011 0001 1010 1010 0001 1010 1010
- state->mmu.aux_control = 0;
-
- desc = &pxa_mmu_desc;
-
- if (mmu_tlb_init (I_TLB (), desc->i_tlb)) {
- ERROR_LOG(ARM11, "i_tlb init %d\n", -1);
- goto i_tlb_init_error;
- }
-
- c_desc = &desc->i_cache;
- if (mmu_cache_init (I_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "i_cache init %d\n", -1);
- goto i_cache_init_error;
- }
-
- if (mmu_tlb_init (D_TLB (), desc->d_tlb)) {
- ERROR_LOG(ARM11, "d_tlb init %d\n", -1);
- goto d_tlb_init_error;
- }
-
- c_desc = &desc->main_d_cache;
- if (mmu_cache_init (MAIN_D_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "main_d_cache init %d\n", -1);
- goto main_d_cache_init_error;
- }
-
- c_desc = &desc->mini_d_cache;
- if (mmu_cache_init (MINI_D_CACHE (), c_desc->width, c_desc->way,
- c_desc->set, c_desc->w_mode)) {
- ERROR_LOG(ARM11, "mini_d_cache init %d\n", -1);
- goto mini_d_cache_init_error;
- }
-
- if (mmu_wb_init (WB (), desc->wb.num, desc->wb.nb)) {
- ERROR_LOG(ARM11, "wb init %d\n", -1);
- goto wb_init_error;
- }
-#if 0
- if (mmu_rb_init (RB (), desc->rb)) {
- ERROR_LOG(ARM11, "rb init %d\n", -1);
- goto rb_init_error;
- }
-#endif
-
- return 0;
-#if 0
- rb_init_error:
- mmu_wb_exit (WB ());
-#endif
- wb_init_error:
- mmu_cache_exit (MINI_D_CACHE ());
- mini_d_cache_init_error:
- mmu_cache_exit (MAIN_D_CACHE ());
- main_d_cache_init_error:
- mmu_tlb_exit (D_TLB ());
- d_tlb_init_error:
- mmu_cache_exit (I_CACHE ());
- i_cache_init_error:
- mmu_tlb_exit (I_TLB ());
- i_tlb_init_error:
- return -1;
-}
-
-unsigned
-xscale_cp15_exit (ARMul_State * state)
-{
- //mmu_rb_exit(RB());
- mmu_wb_exit (WB ());
- mmu_cache_exit (MINI_D_CACHE ());
- mmu_cache_exit (MAIN_D_CACHE ());
- mmu_tlb_exit (D_TLB ());
- mmu_cache_exit (I_CACHE ());
- mmu_tlb_exit (I_TLB ());
- return 0;
-};
-
-
-static fault_t
- xscale_mmu_load_instr (ARMul_State * state, ARMword va,
- ARMword * instr)
-{
- fault_t fault;
- tlb_entry_t *tlb;
- cache_line_t *cache;
- int c; //cache bit
- ARMword pa; //physical addr
-
- static int debug_count = 0; //used for debug
-
- DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- if (MMU_Enabled) {
- /*align check */
- if ((va & (INSN_SIZE - 1)) && MMU_Aligned) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
- else
- va &= ~(INSN_SIZE - 1);
-
- /*translate tlb */
- fault = translate (state, va, I_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
-
- /*check access */
- fault = check_access (state, va, tlb, 1);
- if (fault) {
- DEBUG_LOG(ARM11, "check_fault\n");
- return fault;
- }
- }
- //chy 2003-09-02 for test, don't use cache ?????
-#if 0
- /*search cache no matter MMU enabled/disabled */
- cache = mmu_cache_search (state, I_CACHE (), va);
- if (cache) {
- *instr = cache->data[va_cache_index (va, I_CACHE ())];
- return 0;
- }
-#endif
- /*if MMU disabled or C flag is set alloc cache */
- if (MMU_Disabled) {
- c = 1;
- pa = va;
- }
- else {
- c = tlb_c_flag (tlb);
- pa = tlb_va_to_pa (tlb, va);
- }
-
- //chy 2003-09-03 only read mem, don't use cache now,will change later ????
- //*instr = mem_read_word (state, pa);
- bus_read(32, pa, instr);
-#if 0
-//-----------------------------------------------------------
- //chy 2003-09-02 for test????
- if (pa >= 0xa01c8000 && pa <= 0xa01c8020) {
- printf ("SKYEYE:load_instr: pa %x, va %x,instr %x, R15 %x\n",
- pa, va, *instr, state->Reg[15]);
- }
-
-//----------------------------------------------------------------------
-#endif
- return NO_FAULT;
-
- if (c) {
- int index;
-
- debug_count++;
- cache = mmu_cache_alloc (state, I_CACHE (), va, pa);
- index = va_cache_index (va, I_CACHE ());
- *instr = cache->data[va_cache_index (va, I_CACHE ())];
- }
- else
- //*instr = mem_read_word (state, pa);
- bus_read(32, pa, instr);
-
- return NO_FAULT;
-};
-
-
-
-static fault_t
- xscale_mmu_read_byte (ARMul_State * state, ARMword virt_addr,
- ARMword * data)
-{
- //ARMword temp,offset;
- fault_t fault;
- fault = xscale_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE);
- return fault;
-}
-
-static fault_t
- xscale_mmu_read_halfword (ARMul_State * state, ARMword virt_addr,
- ARMword * data)
-{
- //ARMword temp,offset;
- fault_t fault;
- fault = xscale_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE);
- return fault;
-}
-
-static fault_t
- xscale_mmu_read_word (ARMul_State * state, ARMword virt_addr,
- ARMword * data)
-{
- return xscale_mmu_read (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-
-
-
-static fault_t
- xscale_mmu_read (ARMul_State * state, ARMword va, ARMword * data,
- ARMword datatype)
-{
- fault_t fault;
-// rb_entry_t *rb;
- tlb_entry_t *tlb;
- cache_line_t *cache;
- ARMword pa, real_va, temp, offset;
- //chy 2003-09-02 for test ????
- static unsigned chyst1 = 0, chyst2 = 0;
-
- DEBUG_LOG(ARM11, "va = %x\n", va);
-
- va = mmu_pid_va_map (va);
- real_va = va;
- /*if MMU disabled, memory_read */
- if (MMU_Disabled) {
- //*data = mem_read_word(state, va);
- if (datatype == ARM_BYTE_TYPE)
- //*data = mem_read_byte (state, va);
- bus_read(8, va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //*data = mem_read_halfword (state, va);
- bus_read(16, va, data);
- else if (datatype == ARM_WORD_TYPE)
- //*data = mem_read_word (state, va);
- bus_read(32, va, data);
- else {
- printf ("SKYEYE:1 xscale_mmu_read error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
-
- return NO_FAULT;
- }
-
- /*align check */
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- } // else
-
- va &= ~(WORD_SIZE - 1);
-
- /*translate va to tlb */
- fault = translate (state, va, D_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
- /*check access permission */
- fault = check_access (state, va, tlb, 1);
- if (fault)
- return fault;
-
-#if 0
-//------------------------------------------------
-//chy 2003-09-02 for test only ,should commit ????
- if (datatype == ARM_WORD_TYPE) {
- if (real_va >= 0xffff0000 && real_va <= 0xffff0020) {
- pa = tlb_va_to_pa (tlb, va);
- *data = mem_read_word (state, pa);
- chyst1++;
- printf ("**SKYEYE:mmu_read word %d: pa %x, va %x, data %x, R15 %x\n", chyst1, pa, real_va, *data, state->Reg[15]);
- /*
- cache==mmu_cache_search(state,MAIN_D_CACHE(),va);
- if(cache){
- *data = cache->data[va_cache_index(va, MAIN_D_CACHE())];
- printf("cached data %x\n",*data);
- }else printf("no cached data\n");
- */
- }
- }
-//-------------------------------------------------
-#endif
-#if 0
- /*search in read buffer */
- rb = mmu_rb_search (RB (), va);
- if (rb) {
- if (rb->fault)
- return rb->fault;
- *data = rb->data[(va & (rb_masks[rb->type] - 1)) >> WORD_SHT];
- goto datatrans;
- //return 0;
- };
-#endif
-
- /*2004-07-19 chy: add support of xscale MMU CacheDisabled option */
- if (MMU_CacheDisabled) {
- //if(1){ can be used to test cache error
- /*get phy_addr */
- pa = tlb_va_to_pa (tlb, real_va);
- if (datatype == ARM_BYTE_TYPE)
- //*data = mem_read_byte (state, pa);
- bus_read(8, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //*data = mem_read_halfword (state, pa);
- bus_read(16, pa, data);
- else if (datatype == ARM_WORD_TYPE)
- //*data = mem_read_word (state, pa);
- bus_read(32, pa, data);
- else {
- printf ("SKYEYE:MMU_CacheDisabled xscale_mmu_read error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
- return NO_FAULT;
- }
-
-
- /*search main cache */
- cache = mmu_cache_search (state, MAIN_D_CACHE (), va);
- if (cache) {
- *data = cache->data[va_cache_index (va, MAIN_D_CACHE ())];
-#if 0
-//------------------------------------------------------------------------
-//chy 2003-09-02 for test only ,should commit ????
- if (real_va >= 0xffff0000 && real_va <= 0xffff0020) {
- pa = tlb_va_to_pa (tlb, va);
- chyst2++;
- printf ("**SKYEYE:mmu_read wordk:cache %d: pa %x, va %x, data %x, R15 %x\n", chyst2, pa, real_va, *data, state->Reg[15]);
- }
-//-------------------------------------------------------------------
-#endif
- goto datatrans;
- //return 0;
- }
- //chy 2003-08-24, now maybe we don't need minidcache ????
-#if 0
- /*search mini cache */
- cache = mmu_cache_search (state, MINI_D_CACHE (), va);
- if (cache) {
- *data = cache->data[va_cache_index (va, MINI_D_CACHE ())];
- goto datatrans;
- //return 0;
- }
-#endif
- /*get phy_addr */
- pa = tlb_va_to_pa (tlb, va);
- //chy 2003-08-24 , in xscale it means what ?????
-#if 0
- if ((pa >= 0xe0000000) && (pa < 0xe8000000)) {
-
- if (tlb_c_flag (tlb)) {
- if (tlb_b_flag (tlb)) {
- mmu_cache_soft_flush (state, MAIN_D_CACHE (),
- pa);
- }
- else {
- mmu_cache_soft_flush (state, MINI_D_CACHE (),
- pa);
- }
- }
- return 0;
- }
-#endif
- //chy 2003-08-24, check phy addr
- //ywc 2004-11-30, inactive this check because of using 0xc0000000 as the framebuffer start address
- /*
- if(pa >= 0xb0000000){
- printf("SKYEYE:xscale_mmu_read: phy address 0x%x error,reg[15] 0x%x\n",pa,state->Reg[15]);
- return 0;
- }
- */
-
- //chy 2003-08-24, now maybe we don't need wb ????
-#if 0
- /*if Buffer, drain Write Buffer first */
- if (tlb_b_flag (tlb))
- mmu_wb_drain_all (state, WB ());
-#endif
- /*alloc cache or mem_read */
- if (tlb_c_flag (tlb) && MMU_DCacheEnabled) {
- cache_s *cache_t;
-
- if (tlb_b_flag (tlb))
- cache_t = MAIN_D_CACHE ();
- else
- cache_t = MINI_D_CACHE ();
- cache = mmu_cache_alloc (state, cache_t, va, pa);
- *data = cache->data[va_cache_index (va, cache_t)];
- }
- else {
- //*data = mem_read_word(state, pa);
- if (datatype == ARM_BYTE_TYPE)
- //*data = mem_read_byte (state, pa | (real_va & 3));
- bus_read(8, pa | (real_va & 3), data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //*data = mem_read_halfword (state, pa | (real_va & 2));
- bus_read(16, pa | (real_va & 2), data);
- else if (datatype == ARM_WORD_TYPE)
- //*data = mem_read_word (state, pa);
- bus_read(32, pa, data);
- else {
- printf ("SKYEYE:2 xscale_mmu_read error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
- return NO_FAULT;
- }
-
-
- datatrans:
- if (datatype == ARM_HALFWORD_TYPE) {
- temp = *data;
- offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */
- *data = (temp >> offset) & 0xffff;
- }
- else if (datatype == ARM_BYTE_TYPE) {
- temp = *data;
- offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */
- *data = (temp >> offset & 0xffL);
- }
- end:
- return NO_FAULT;
-}
-
-
-static fault_t
- xscale_mmu_write_byte (ARMul_State * state, ARMword virt_addr,
- ARMword data)
-{
- return xscale_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE);
-}
-
-static fault_t
- xscale_mmu_write_halfword (ARMul_State * state, ARMword virt_addr,
- ARMword data)
-{
- return xscale_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE);
-}
-
-static fault_t
- xscale_mmu_write_word (ARMul_State * state, ARMword virt_addr,
- ARMword data)
-{
- return xscale_mmu_write (state, virt_addr, data, ARM_WORD_TYPE);
-}
-
-
-
-static fault_t
- xscale_mmu_write (ARMul_State * state, ARMword va, ARMword data,
- ARMword datatype)
-{
- tlb_entry_t *tlb;
- cache_line_t *cache;
- cache_s *cache_t;
- int b;
- ARMword pa, real_va, temp, offset;
- fault_t fault;
-
- ARMword index;
-//chy 2003-09-02 for test ????
-// static unsigned chyst1=0,chyst2=0;
-
- DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data);
- va = mmu_pid_va_map (va);
- real_va = va;
-
- if (MMU_Disabled) {
- //mem_write_word(state, va, data);
- if (datatype == ARM_BYTE_TYPE)
- //mem_write_byte (state, va, data);
- bus_write(8, va, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //mem_write_halfword (state, va, data);
- bus_write(16, va, data);
- else if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, va, data);
- bus_write(32, va, data);
- else {
- printf ("SKYEYE:1 xscale_mmu_write error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
-
- return NO_FAULT;
- }
- /*align check */
- if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
- ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- } //else
- va &= ~(WORD_SIZE - 1);
- /*tlb translate */
- fault = translate (state, va, D_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
- /*tlb check access */
- fault = check_access (state, va, tlb, 0);
- if (fault) {
- DEBUG_LOG(ARM11, "check_access\n");
- return fault;
- }
-
- /*2004-07-19 chy: add support for xscale MMU_CacheDisabled */
- if (MMU_CacheDisabled) {
- //if(1){ can be used to test the cache error
- /*get phy_addr */
- pa = tlb_va_to_pa (tlb, real_va);
- if (datatype == ARM_BYTE_TYPE)
- //mem_write_byte (state, pa, data);
- bus_write(8, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //mem_write_halfword (state, pa, data);
- bus_write(16, pa, data);
- else if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, pa, data);
- bus_write(32, pa , data);
- else {
- printf ("SKYEYE:MMU_CacheDisabled xscale_mmu_write error: unknown data type %d\n", datatype);
- // skyeye_exit (-1);
- }
-
- return NO_FAULT;
- }
-
- /*search main cache */
- b = tlb_b_flag (tlb);
- pa = tlb_va_to_pa (tlb, va);
- cache = mmu_cache_search (state, MAIN_D_CACHE (), va);
- if (cache) {
- cache_t = MAIN_D_CACHE ();
- goto has_cache;
- }
- //chy 2003-08-24, now maybe we don't need minidcache ????
-#if 0
- /*search mini cache */
- cache = mmu_cache_search (state, MINI_D_CACHE (), va);
- if (cache) {
- cache_t = MINI_D_CACHE ();
- goto has_cache;
- }
-#endif
- b = tlb_b_flag (tlb);
- pa = tlb_va_to_pa (tlb, va);
- //chy 2003-08-24, check phy addr 0xa0000000, size 0x04000000
- //ywc 2004-11-30, inactive this check because of using 0xc0000000 as the framebuffer start address
- /*
- if(pa >= 0xb0000000){
- printf("SKYEYE:xscale_mmu_write phy address 0x%x error,reg[15] 0x%x\n",pa,state->Reg[15]);
- return 0;
- }
- */
-
- //chy 2003-08-24, now maybe we don't need WB ????
-#if 0
- if (b) {
- if (MMU_WBEnabled) {
- if (datatype == ARM_WORD_TYPE)
- mmu_wb_write_bytes (state, WB (), pa, &data,
- 4);
- else if (datatype == ARM_HALFWORD_TYPE)
- mmu_wb_write_bytes (state, WB (),
- (pa | (real_va & 2)),
- &data, 2);
- else if (datatype == ARM_BYTE_TYPE)
- mmu_wb_write_bytes (state, WB (),
- (pa | (real_va & 3)),
- &data, 1);
-
- }
- else {
- if (datatype == ARM_WORD_TYPE)
- mem_write_word (state, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- mem_write_halfword (state,
- (pa | (real_va & 2)),
- data);
- else if (datatype == ARM_BYTE_TYPE)
- mem_write_byte (state, (pa | (real_va & 3)),
- data);
- }
- }
- else {
-
- mmu_wb_drain_all (state, WB ());
-
- if (datatype == ARM_WORD_TYPE)
- mem_write_word (state, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- mem_write_halfword (state, (pa | (real_va & 2)),
- data);
- else if (datatype == ARM_BYTE_TYPE)
- mem_write_byte (state, (pa | (real_va & 3)), data);
- }
-#endif
- //chy 2003-08-24, just write phy addr
- if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, pa, data);
- bus_write(32, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //mem_write_halfword (state, (pa | (real_va & 2)), data);
- bus_write(16, pa | (real_va & 2), data);
- else if (datatype == ARM_BYTE_TYPE)
- //mem_write_byte (state, (pa | (real_va & 3)), data);
- bus_write(8, (pa | (real_va & 3)), data);
-#if 0
-//-------------------------------------------------------------
-//chy 2003-09-02 for test ????
- if (datatype == ARM_WORD_TYPE) {
- if (real_va >= 0xffff0000 && real_va <= 0xffff0020) {
- printf ("**SKYEYE:mmu_write word: pa %x, va %x, data %x, R15 %x \n", pa, real_va, data, state->Reg[15]);
- }
- }
-//--------------------------------------------------------------
-#endif
- return NO_FAULT;
-
- has_cache:
- index = va_cache_index (va, cache_t);
- //cache->data[index] = data;
-
- if (datatype == ARM_WORD_TYPE)
- cache->data[index] = data;
- else if (datatype == ARM_HALFWORD_TYPE) {
- temp = cache->data[index];
- offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */
- cache->data[index] =
- (temp & ~(0xffffL << offset)) | ((data & 0xffffL) <<
- offset);
- }
- else if (datatype == ARM_BYTE_TYPE) {
- temp = cache->data[index];
- offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */
- cache->data[index] =
- (temp & ~(0xffL << offset)) | ((data & 0xffL) <<
- offset);
- }
-
- if (index < (cache_t->width >> (WORD_SHT + 1)))
- cache->tag |= TAG_FIRST_HALF_DIRTY;
- else
- cache->tag |= TAG_LAST_HALF_DIRTY;
-//-------------------------------------------------------------
-//chy 2003-09-03 be sure the changed value will be in memory as soon as possible, so I cache can get the newest value
-#if 0
- {
- if (datatype == ARM_WORD_TYPE)
- mem_write_word (state, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- mem_write_halfword (state, (pa | (real_va & 2)),
- data);
- else if (datatype == ARM_BYTE_TYPE)
- mem_write_byte (state, (pa | (real_va & 3)), data);
- }
-#endif
-#if 0
-//chy 2003-09-02 for test ????
- if (datatype == ARM_WORD_TYPE) {
- if (real_va >= 0xffff0000 && real_va <= 0xffff0020) {
- printf ("**SKYEYE:mmu_write word:cache: pa %x, va %x, data %x, R15 %x\n", pa, real_va, data, state->Reg[15]);
- }
- }
-//-------------------------------------------------------------
-#endif
- if (datatype == ARM_WORD_TYPE)
- //mem_write_word (state, pa, data);
- bus_write(32, pa, data);
- else if (datatype == ARM_HALFWORD_TYPE)
- //mem_write_halfword (state, (pa | (real_va & 2)), data);
- bus_write(16, pa | (real_va & 2), data);
- else if (datatype == ARM_BYTE_TYPE)
- //mem_write_byte (state, (pa | (real_va & 3)), data);
- bus_write(8, (pa | (real_va & 3)), data);
- return NO_FAULT;
-}
-
-ARMword xscale_cp15_mrc (ARMul_State * state,
- unsigned type, ARMword instr, ARMword * value)
-{
- return xscale_mmu_mrc (state, instr, value);
-}
-
-ARMword xscale_mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value)
-{
- ARMword data;
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
- mmu_regnum_t creg = (mmu_regnum_t)reg;
-
-/*
- printf("SKYEYE: xscale_cp15_mrc:opcode_2 0x%x, CRm 0x%x, reg 0x%x,reg[15] 0x%x, instr %x\n",opcode_2,CRm,reg,\
- state->Reg[15], instr);
-*/
- switch (creg) {
- case MMU_ID: //XSCALE_CP15
- //printf("mmu_mrc read ID \n");
- data = (opcode_2 ? state->mmu.cache_type : state->cpu->
- cpu_val);
- break;
- case MMU_CONTROL: //XSCALE_CP15_AUX_CONTROL
- //printf("mmu_mrc read CONTROL \n");
- data = (opcode_2 ? state->mmu.aux_control : state->mmu.
- control);
- break;
- case MMU_TRANSLATION_TABLE_BASE:
- //printf("mmu_mrc read TTB \n");
- data = state->mmu.translation_table_base;
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
- //printf("mmu_mrc read DACR \n");
- data = state->mmu.domain_access_control;
- break;
- case MMU_FAULT_STATUS:
- //printf("mmu_mrc read FSR \n");
- data = state->mmu.fault_status;
- break;
- case MMU_FAULT_ADDRESS:
- //printf("mmu_mrc read FAR \n");
- data = state->mmu.fault_address;
- break;
- case MMU_PID:
- //printf("mmu_mrc read PID \n");
- data = state->mmu.process_id;
- case XSCALE_CP15_COPRO_ACCESS:
- //printf("xscale cp15 read coprocessor access\n");
- data = state->mmu.copro_access;
- break;
- default:
- data = 0;
- printf ("SKYEYE: xscale_cp15_mrc read UNKNOWN - reg %d, pc 0x%x\n", creg, state->Reg[15]);
- // skyeye_exit (-1);
- break;
- }
- *value = data;
- //printf("SKYEYE: xscale_cp15_mrc:end value 0x%x\n",data);
- return ARMul_DONE;
-}
-
-void xscale_cp15_cache_ops (ARMul_State * state, ARMword instr, ARMword value)
-{
-//chy: 2003-08-24 now, the BTB isn't simualted ....????
-
- unsigned CRm, OPC_2;
-
- CRm = BITS (0, 3);
- OPC_2 = BITS (5, 7);
- //err_msg("SKYEYE: xscale cp15_cache_ops:OPC_2 = 0x%x CRm = 0x%x, Reg15 0x%x\n", OPC_2, CRm,state->Reg[15]);
-
- if (OPC_2 == 0 && CRm == 7) {
- mmu_cache_invalidate_all (state, I_CACHE ());
- mmu_cache_invalidate_all (state, MAIN_D_CACHE ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 5) {
- mmu_cache_invalidate_all (state, I_CACHE ());
- return;
- }
- if (OPC_2 == 1 && CRm == 5) {
- mmu_cache_invalidate (state, I_CACHE (), value);
- return;
- }
-
- if (OPC_2 == 0 && CRm == 6) {
- mmu_cache_invalidate_all (state, MAIN_D_CACHE ());
- return;
- }
-
- if (OPC_2 == 1 && CRm == 6) {
- mmu_cache_invalidate (state, MAIN_D_CACHE (), value);
- return;
- }
-
- if (OPC_2 == 1 && CRm == 0xa) {
- mmu_cache_clean (state, MAIN_D_CACHE (), value);
- return;
- }
-
- if (OPC_2 == 4 && CRm == 0xa) {
- mmu_wb_drain_all (state, WB ());
- return;
- }
-
- if (OPC_2 == 6 && CRm == 5) {
- //chy 2004-07-19 shoud fix in the future????!!!!
- //printf("SKYEYE: xscale_cp15_cache_ops:invalidate BTB CANT!!!!!!!!!!\n");
- //exit(-1);
- return;
- }
-
- if (OPC_2 == 5 && CRm == 2) {
- //printf("SKYEYE: cp15_c_o: A L in D C, value %x, reg15 %x\n",value, state->Reg[15]);
- //exit(-1);
- //chy 2003-09-01 for test
- mmu_cache_invalidate_all (state, MAIN_D_CACHE ());
- return;
- }
-
- ERROR_LOG(ARM11, "SKYEYE: xscale cp15_cache_ops:Unknown OPC_2 = 0x%x CRm = 0x%x, Reg15 0x%x\n", OPC_2, CRm, state->Reg[15]);
- // skyeye_exit (-1);
-}
-
-static void
- xscale_cp15_tlb_ops (ARMul_State * state, ARMword instr,
- ARMword value)
-{
- int CRm, OPC_2;
-
- CRm = BITS (0, 3);
- OPC_2 = BITS (5, 7);
-
-
- //err_msg("SKYEYE:xscale_cp15_tlb_ops:OPC_2 = 0x%x CRm = 0x%x,Reg[15] 0x%x\n", OPC_2, CRm,state->Reg[15]);
- if (OPC_2 == 0 && CRm == 0x7) {
- mmu_tlb_invalidate_all (state, I_TLB ());
- mmu_tlb_invalidate_all (state, D_TLB ());
- return;
- }
-
- if (OPC_2 == 0 && CRm == 0x5) {
- mmu_tlb_invalidate_all (state, I_TLB ());
- return;
- }
-
- if (OPC_2 == 1 && CRm == 0x5) {
- mmu_tlb_invalidate_entry (state, I_TLB (), value);
- return;
- }
-
- if (OPC_2 == 0 && CRm == 0x6) {
- mmu_tlb_invalidate_all (state, D_TLB ());
- return;
- }
-
- if (OPC_2 == 1 && CRm == 0x6) {
- mmu_tlb_invalidate_entry (state, D_TLB (), value);
- return;
- }
-
- ERROR_LOG(ARM11, "SKYEYE:xscale_cp15_tlb_ops:Unknow OPC_2 = 0x%x CRm = 0x%x,Reg[15] 0x%x\n", OPC_2, CRm, state->Reg[15]);
- // skyeye_exit (-1);
-}
-
-
-ARMword xscale_cp15_mcr (ARMul_State * state,
- unsigned type, ARMword instr, ARMword value)
-{
- return xscale_mmu_mcr (state, instr, value);
-}
-
-ARMword xscale_mmu_mcr (ARMul_State * state, ARMword instr, ARMword value)
-{
- ARMword data;
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
- mmu_regnum_t creg = (mmu_regnum_t)reg;
-
- //printf("SKYEYE: xscale_cp15_mcr: opcode_2 0x%x, CRm 0x%x, reg ox%x, value 0x%x, reg[15] 0x%x, instr 0x%x\n",opcode_2,CRm,reg, value, state->Reg[15], instr);
-
- switch (creg) {
- case MMU_CONTROL:
- //printf("mmu_mcr wrote CONTROL val 0x%x \n",value);
- state->mmu.control =
- (opcode_2 ? (value & 0x33) : (value & 0x3FFF));
- break;
- case MMU_TRANSLATION_TABLE_BASE:
- //printf("mmu_mcr wrote TTB val 0x%x \n",value);
- state->mmu.translation_table_base = value & 0xFFFFC000;
- break;
- case MMU_DOMAIN_ACCESS_CONTROL:
- //printf("mmu_mcr wrote DACR val 0x%x \n",value);
- state->mmu.domain_access_control = value;
- break;
-
- case MMU_FAULT_STATUS:
- //printf("mmu_mcr wrote FS val 0x%x \n",value);
- state->mmu.fault_status = value & 0x6FF;
- break;
- case MMU_FAULT_ADDRESS:
- //printf("mmu_mcr wrote FA val 0x%x \n",value);
- state->mmu.fault_address = value;
- break;
-
- case MMU_CACHE_OPS:
-// printf("mmu_mcr wrote CO val 0x%x \n",value);
- xscale_cp15_cache_ops (state, instr, value);
- break;
- case MMU_TLB_OPS:
- //printf("mmu_mcr wrote TO val 0x%x \n",value);
- xscale_cp15_tlb_ops (state, instr, value);
- break;
- case MMU_PID:
- //printf("mmu_mcr wrote PID val 0x%x \n",value);
- state->mmu.process_id = value & 0xfe000000;
- break;
- case XSCALE_CP15_COPRO_ACCESS:
- //printf("xscale cp15 write coprocessor access val 0x %x\n",value);
- state->mmu.copro_access = value & 0x3ff;
- break;
-
- default:
- printf ("SKYEYE: xscale_cp15_mcr wrote UNKNOWN - reg %d, reg15 0x%x\n", creg, state->Reg[15]);
- break;
- }
- //printf("SKYEYE: xscale_cp15_mcr wrote val 0x%x\n", value);
- return 0;
-}
-
-//teawater add for arm2x86 2005.06.24-------------------------------------------
-static int xscale_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr,
- ARMword * phys_addr)
-{
- fault_t fault;
- tlb_entry_t *tlb;
-
- virt_addr = mmu_pid_va_map (virt_addr);
- if (MMU_Enabled) {
-
- /*align check */
- if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
- DEBUG_LOG(ARM11, "align\n");
- return ALIGNMENT_FAULT;
- }
- else
- virt_addr &= ~(WORD_SIZE - 1);
-
- /*translate tlb */
- fault = translate (state, virt_addr, I_TLB (), &tlb);
- if (fault) {
- DEBUG_LOG(ARM11, "translate\n");
- return fault;
- }
-
- /*check access */
- fault = check_access (state, virt_addr, tlb, 1);
- if (fault) {
- DEBUG_LOG(ARM11, "check_fault\n");
- return fault;
- }
- }
-
- if (MMU_Disabled) {
- *phys_addr = virt_addr;
- }
- else {
- *phys_addr = tlb_va_to_pa (tlb, virt_addr);
- }
-
- return (0);
-}
-
-//AJ2D--------------------------------------------------------------------------
-
-/*xscale mmu_ops_t*/
-//mmu_ops_t xscale_mmu_ops = {
-// xscale_cp15_init,
-// xscale_cp15_exit,
-// xscale_mmu_read_byte,
-// xscale_mmu_write_byte,
-// xscale_mmu_read_halfword,
-// xscale_mmu_write_halfword,
-// xscale_mmu_read_word,
-// xscale_mmu_write_word,
-// xscale_mmu_load_instr, xscale_mmu_mcr, xscale_mmu_mrc,
-////teawater add for arm2x86 2005.06.24-------------------------------------------
-// xscale_mmu_v2p_dbct,
-////AJ2D--------------------------------------------------------------------------
-//};
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index fd574a7a16..8e71948c6c 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -367,7 +367,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
int verbose; /* non-zero means print various messages like the banner */
- mmu_state_t mmu;
int mmu_inited;
//mem_state_t mem;
/*remove io_state to skyeye_mach_*.c files */
diff --git a/src/core/arm/skyeye_common/armmmu.h b/src/core/arm/skyeye_common/armmmu.h
index 818108c9cb..30858f9ba9 100644
--- a/src/core/arm/skyeye_common/armmmu.h
+++ b/src/core/arm/skyeye_common/armmmu.h
@@ -134,121 +134,4 @@ typedef enum fault_t
} fault_t;
-typedef struct mmu_ops_s
-{
- /*initilization */
- int (*init) (ARMul_State * state);
- /*free on exit */
- void (*exit) (ARMul_State * state);
- /*read byte data */
- fault_t (*read_byte) (ARMul_State * state, ARMword va,
- ARMword * data);
- /*write byte data */
- fault_t (*write_byte) (ARMul_State * state, ARMword va,
- ARMword data);
- /*read halfword data */
- fault_t (*read_halfword) (ARMul_State * state, ARMword va,
- ARMword * data);
- /*write halfword data */
- fault_t (*write_halfword) (ARMul_State * state, ARMword va,
- ARMword data);
- /*read word data */
- fault_t (*read_word) (ARMul_State * state, ARMword va,
- ARMword * data);
- /*write word data */
- fault_t (*write_word) (ARMul_State * state, ARMword va,
- ARMword data);
- /*load instr */
- fault_t (*load_instr) (ARMul_State * state, ARMword va,
- ARMword * instr);
- /*mcr */
- ARMword (*mcr) (ARMul_State * state, ARMword instr, ARMword val);
- /*mrc */
- ARMword (*mrc) (ARMul_State * state, ARMword instr, ARMword * val);
-
- /*ywc 2005-04-16 convert virtual address to physics address */
- int (*v2p_dbct) (ARMul_State * state, ARMword virt_addr,
- ARMword * phys_addr);
-} mmu_ops_t;
-
-
-#include "core/arm/interpreter/mmu/tlb.h"
-#include "core/arm/interpreter/mmu/rb.h"
-#include "core/arm/interpreter/mmu/wb.h"
-#include "core/arm/interpreter/mmu/cache.h"
-
-/*special process mmu.h*/
-#include "core/arm/interpreter/mmu/sa_mmu.h"
-//#include "core/arm/interpreter/mmu/arm7100_mmu.h"
-//#include "core/arm/interpreter/mmu/arm920t_mmu.h"
-//#include "core/arm/interpreter/mmu/arm926ejs_mmu.h"
-#include "core/arm/interpreter/mmu/arm1176jzf_s_mmu.h"
-//#include "core/arm/interpreter/mmu/cortex_a9_mmu.h"
-
-typedef struct mmu_state_t
-{
- ARMword control;
- ARMword translation_table_base;
-/* dyf 201-08-11 for arm1176 */
- ARMword auxiliary_control;
- ARMword coprocessor_access_control;
- ARMword translation_table_base0;
- ARMword translation_table_base1;
- ARMword translation_table_ctrl;
-/* arm1176 end */
-
- ARMword domain_access_control;
- ARMword fault_status;
- ARMword fault_statusi; /* prefetch fault status */
- ARMword fault_address;
- ARMword last_domain;
- ARMword process_id;
- ARMword context_id;
- ARMword thread_uro_id;
- ARMword cache_locked_down;
- ARMword tlb_locked_down;
-//chy 2003-08-24 for xscale
- ARMword cache_type; // 0
- ARMword aux_control; // 1
- ARMword copro_access; // 15
-
- mmu_ops_t ops;
- union
- {
- sa_mmu_t sa_mmu;
- //arm7100_mmu_t arm7100_mmu;
- //arm920t_mmu_t arm920t_mmu;
- //arm926ejs_mmu_t arm926ejs_mmu;
- } u;
-} mmu_state_t;
-
-int mmu_init (ARMul_State * state);
-int mmu_reset (ARMul_State * state);
-void mmu_exit (ARMul_State * state);
-
-fault_t mmu_read_word (ARMul_State * state, ARMword virt_addr,
- ARMword * data);
-fault_t mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data);
-fault_t mmu_load_instr (ARMul_State * state, ARMword virt_addr,
- ARMword * instr);
-
-ARMword mmu_mrc (ARMul_State * state, ARMword instr, ARMword * value);
-void mmu_mcr (ARMul_State * state, ARMword instr, ARMword value);
-
-/*ywc 20050416*/
-int mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr,
- ARMword * phys_addr);
-
-fault_t
-mmu_read_byte (ARMul_State * state, ARMword virt_addr, ARMword * data);
-fault_t
-mmu_read_halfword (ARMul_State * state, ARMword virt_addr, ARMword * data);
-fault_t
-mmu_read_word (ARMul_State * state, ARMword virt_addr, ARMword * data);
-fault_t
-mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data);
-fault_t
-mmu_write_halfword (ARMul_State * state, ARMword virt_addr, ARMword data);
-fault_t
-mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data);
#endif /* _ARMMMU_H_ */