mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-11-15 22:54:00 +00:00
video_core: Silent miscellaneous warnings (#2820)
* texture_cache/surface_params: Remove unused local variable * rasterizer_interface: Add missing documentation commentary * maxwell_dma: Remove unused rasterizer reference * video_core/gpu: Sort member declaration order to silent -Wreorder warning * fermi_2d: Remove unused MemoryManager reference * video_core: Silent unused variable warnings * buffer_cache: Silent -Wreorder warnings * kepler_memory: Remove unused MemoryManager reference * gl_texture_cache: Add missing override * buffer_cache: Add missing include * shader/decode: Remove unused variables
This commit is contained in:
parent
67cc2d5046
commit
4d4f9cc104
23 changed files with 22 additions and 48 deletions
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@ -69,7 +69,6 @@ protected:
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private:
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private:
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CacheAddr cache_addr{};
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CacheAddr cache_addr{};
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CacheAddr cache_addr_end{};
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CacheAddr cache_addr_end{};
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u64 pages{};
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std::size_t size{};
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std::size_t size{};
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u64 epoch{};
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u64 epoch{};
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};
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};
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@ -18,10 +18,7 @@
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#include "video_core/buffer_cache/buffer_block.h"
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#include "video_core/buffer_cache/buffer_block.h"
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#include "video_core/buffer_cache/map_interval.h"
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#include "video_core/buffer_cache/map_interval.h"
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#include "video_core/memory_manager.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace VideoCommon {
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namespace VideoCommon {
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@ -348,7 +345,6 @@ private:
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const CacheAddr cache_addr_end = cache_addr + size - 1;
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const CacheAddr cache_addr_end = cache_addr + size - 1;
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u64 page_start = cache_addr >> block_page_bits;
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u64 page_start = cache_addr >> block_page_bits;
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const u64 page_end = cache_addr_end >> block_page_bits;
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const u64 page_end = cache_addr_end >> block_page_bits;
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const u64 num_pages = page_end - page_start + 1;
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while (page_start <= page_end) {
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while (page_start <= page_end) {
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auto it = blocks.find(page_start);
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auto it = blocks.find(page_start);
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if (it == blocks.end()) {
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if (it == blocks.end()) {
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@ -417,7 +413,10 @@ private:
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return false;
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return false;
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}
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}
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VideoCore::RasterizerInterface& rasterizer;
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Core::System& system;
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std::unique_ptr<StreamBuffer> stream_buffer;
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std::unique_ptr<StreamBuffer> stream_buffer;
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TBufferType stream_buffer_handle{};
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TBufferType stream_buffer_handle{};
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bool invalidated = false;
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bool invalidated = false;
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@ -441,8 +440,7 @@ private:
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std::list<TBuffer> pending_destruction{};
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std::list<TBuffer> pending_destruction{};
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u64 epoch{};
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u64 epoch{};
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u64 modified_ticks{};
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u64 modified_ticks{};
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VideoCore::RasterizerInterface& rasterizer;
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Core::System& system;
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std::recursive_mutex mutex;
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std::recursive_mutex mutex;
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};
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};
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@ -10,8 +10,7 @@
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer) : rasterizer{rasterizer} {}
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: rasterizer{rasterizer}, memory_manager{memory_manager} {}
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void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
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void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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@ -33,7 +33,7 @@ namespace Tegra::Engines {
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class Fermi2D final {
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class Fermi2D final {
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public:
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public:
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explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager);
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explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer);
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~Fermi2D() = default;
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~Fermi2D() = default;
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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@ -145,7 +145,6 @@ public:
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private:
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private:
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VideoCore::RasterizerInterface& rasterizer;
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VideoCore::RasterizerInterface& rasterizer;
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MemoryManager& memory_manager;
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// registers.
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/// registers.
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@ -15,7 +15,7 @@
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
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KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager}, upload_state{memory_manager, regs.upload} {}
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: system{system}, upload_state{memory_manager, regs.upload} {}
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KeplerMemory::~KeplerMemory() = default;
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KeplerMemory::~KeplerMemory() = default;
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@ -65,7 +65,6 @@ public:
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private:
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private:
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Core::System& system;
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Core::System& system;
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MemoryManager& memory_manager;
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Upload::State upload_state;
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Upload::State upload_state;
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};
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};
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@ -524,7 +524,7 @@ void Maxwell3D::ProcessQueryCondition() {
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void Maxwell3D::ProcessSyncPoint() {
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void Maxwell3D::ProcessSyncPoint() {
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const u32 sync_point = regs.sync_info.sync_point.Value();
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const u32 sync_point = regs.sync_info.sync_point.Value();
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const u32 increment = regs.sync_info.increment.Value();
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const u32 increment = regs.sync_info.increment.Value();
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const u32 cache_flush = regs.sync_info.unknown.Value();
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[[maybe_unused]] const u32 cache_flush = regs.sync_info.unknown.Value();
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if (increment) {
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if (increment) {
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system.GPU().IncrementSyncPoint(sync_point);
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system.GPU().IncrementSyncPoint(sync_point);
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}
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}
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@ -626,10 +626,10 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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Texture::TICEntry tic_entry;
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Texture::TICEntry tic_entry;
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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const auto r_type{tic_entry.r_type.Value()};
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[[maybe_unused]] const auto r_type{tic_entry.r_type.Value()};
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const auto g_type{tic_entry.g_type.Value()};
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[[maybe_unused]] const auto g_type{tic_entry.g_type.Value()};
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const auto b_type{tic_entry.b_type.Value()};
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[[maybe_unused]] const auto b_type{tic_entry.b_type.Value()};
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const auto a_type{tic_entry.a_type.Value()};
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[[maybe_unused]] const auto a_type{tic_entry.a_type.Value()};
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// TODO(Subv): Different data types for separate components are not supported
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// TODO(Subv): Different data types for separate components are not supported
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DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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@ -8,15 +8,13 @@
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/memory_manager.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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MaxwellDMA::MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MaxwellDMA::MaxwellDMA(Core::System& system, MemoryManager& memory_manager)
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MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager} {}
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager} {}
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void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
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void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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@ -20,10 +20,6 @@ namespace Tegra {
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class MemoryManager;
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class MemoryManager;
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}
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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/**
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/**
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class MaxwellDMA final {
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class MaxwellDMA final {
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public:
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public:
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explicit MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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explicit MaxwellDMA(Core::System& system, MemoryManager& memory_manager);
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MemoryManager& memory_manager);
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~MaxwellDMA() = default;
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~MaxwellDMA() = default;
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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private:
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private:
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Core::System& system;
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Core::System& system;
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VideoCore::RasterizerInterface& rasterizer;
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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std::vector<u8> read_buffer;
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std::vector<u8> read_buffer;
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memory_manager = std::make_unique<Tegra::MemoryManager>(system, rasterizer);
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memory_manager = std::make_unique<Tegra::MemoryManager>(system, rasterizer);
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dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
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dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, rasterizer, *memory_manager);
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, rasterizer, *memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer);
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kepler_compute = std::make_unique<Engines::KeplerCompute>(system, rasterizer, *memory_manager);
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kepler_compute = std::make_unique<Engines::KeplerCompute>(system, rasterizer, *memory_manager);
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, rasterizer, *memory_manager);
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, *memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
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}
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}
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protected:
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protected:
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std::unique_ptr<Tegra::DmaPusher> dma_pusher;
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std::unique_ptr<Tegra::DmaPusher> dma_pusher;
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VideoCore::RendererBase& renderer;
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Core::System& system;
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Core::System& system;
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VideoCore::RendererBase& renderer;
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private:
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private:
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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/// and invalidated
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/// and invalidated
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virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
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virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
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// Notify the rasterizer to send all written commands to the host GPU.
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/// Notify the rasterizer to send all written commands to the host GPU.
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virtual void FlushCommands() = 0;
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virtual void FlushCommands() = 0;
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/// Notify rasterizer that a frame is about to finish
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/// Notify rasterizer that a frame is about to finish
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return;
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return;
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}
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}
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const auto& regs = gpu.regs;
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SyncColorMask();
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SyncColorMask();
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SyncFragmentColorClampState();
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SyncFragmentColorClampState();
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SyncMultiSampleState();
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SyncMultiSampleState();
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@ -295,7 +295,7 @@ std::set<GLenum> GetSupportedFormats() {
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CachedShader::CachedShader(const ShaderParameters& params, ProgramType program_type,
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CachedShader::CachedShader(const ShaderParameters& params, ProgramType program_type,
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GLShader::ProgramResult result)
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GLShader::ProgramResult result)
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: RasterizerCacheObject{params.host_ptr}, host_ptr{params.host_ptr}, cpu_addr{params.cpu_addr},
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: RasterizerCacheObject{params.host_ptr}, cpu_addr{params.cpu_addr},
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unique_identifier{params.unique_identifier}, program_type{program_type},
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unique_identifier{params.unique_identifier}, program_type{program_type},
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disk_cache{params.disk_cache}, precompiled_programs{params.precompiled_programs},
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disk_cache{params.disk_cache}, precompiled_programs{params.precompiled_programs},
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entries{result.second}, code{std::move(result.first)}, shader_length{entries.shader_length} {}
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entries{result.second}, code{std::move(result.first)}, shader_length{entries.shader_length} {}
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ShaderDiskCacheUsage GetUsage(const ProgramVariant& variant) const;
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ShaderDiskCacheUsage GetUsage(const ProgramVariant& variant) const;
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u8* host_ptr{};
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VAddr cpu_addr{};
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VAddr cpu_addr{};
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u64 unique_identifier{};
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u64 unique_identifier{};
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ProgramType program_type{};
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ProgramType program_type{};
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}
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}
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protected:
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protected:
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void DecorateSurfaceName();
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void DecorateSurfaceName() override;
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View CreateView(const ViewParams& view_key) override;
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View CreateView(const ViewParams& view_key) override;
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View CreateViewInner(const ViewParams& view_key, bool is_proxy);
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View CreateViewInner(const ViewParams& view_key, bool is_proxy);
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u32 ShaderIR::DecodeFloatSet(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeFloatSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fset.abs_a != 0,
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fset.abs_a != 0,
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instr.fset.neg_a != 0);
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instr.fset.neg_a != 0);
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u32 ShaderIR::DecodeFloatSetPredicate(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeFloatSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fsetp.abs_a != 0,
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fsetp.abs_a != 0,
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instr.fsetp.neg_a != 0);
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instr.fsetp.neg_a != 0);
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u32 ShaderIR::DecodeIntegerSet(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeIntegerSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = [&]() {
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const Node op_b = [&]() {
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@ -16,7 +16,6 @@ using Tegra::Shader::Pred;
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u32 ShaderIR::DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_a = GetRegister(instr.gpr8);
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@ -15,7 +15,6 @@ using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodePredicateSetRegister(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodePredicateSetRegister(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in PSET is not implemented");
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"Condition codes generation in PSET is not implemented");
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@ -58,7 +58,6 @@ public:
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||||||
std::size_t GetHostSizeInBytes() const {
|
std::size_t GetHostSizeInBytes() const {
|
||||||
std::size_t host_size_in_bytes;
|
std::size_t host_size_in_bytes;
|
||||||
if (GetCompressionType() == SurfaceCompression::Converted) {
|
if (GetCompressionType() == SurfaceCompression::Converted) {
|
||||||
constexpr std::size_t rgb8_bpp = 4ULL;
|
|
||||||
// ASTC is uncompressed in software, in emulated as RGBA8
|
// ASTC is uncompressed in software, in emulated as RGBA8
|
||||||
host_size_in_bytes = 0;
|
host_size_in_bytes = 0;
|
||||||
for (u32 level = 0; level < num_levels; ++level) {
|
for (u32 level = 0; level < num_levels; ++level) {
|
||||||
|
|
|
@ -308,8 +308,6 @@ protected:
|
||||||
if (!guard_render_targets && surface->IsRenderTarget()) {
|
if (!guard_render_targets && surface->IsRenderTarget()) {
|
||||||
ManageRenderTargetUnregister(surface);
|
ManageRenderTargetUnregister(surface);
|
||||||
}
|
}
|
||||||
const GPUVAddr gpu_addr = surface->GetGpuAddr();
|
|
||||||
const CacheAddr cache_ptr = surface->GetCacheAddr();
|
|
||||||
const std::size_t size = surface->GetSizeInBytes();
|
const std::size_t size = surface->GetSizeInBytes();
|
||||||
const VAddr cpu_addr = surface->GetCpuAddr();
|
const VAddr cpu_addr = surface->GetCpuAddr();
|
||||||
rasterizer.UpdatePagesCachedCount(cpu_addr, size, -1);
|
rasterizer.UpdatePagesCachedCount(cpu_addr, size, -1);
|
||||||
|
|
Loading…
Reference in a new issue