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gl_shader_decompiler: Refactor LOP32I instruction a bit in support of LOP.

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This commit is contained in:
bunnei 2018-06-17 12:49:34 -04:00
parent 3c43ea5c68
commit 5673ce39c7
2 changed files with 42 additions and 57 deletions
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5
src/video_core/engines/shader_bytecode.h
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@ -233,7 +233,7 @@ union Instruction {
BitField<53, 2, LogicOperation> operation; BitField<53, 2, LogicOperation> operation;
BitField<55, 1, u64> invert_a; BitField<55, 1, u64> invert_a;
BitField<56, 1, u64> invert_b; BitField<56, 1, u64> invert_b;
} lop; } lop32i;
float GetImm20_19() const { float GetImm20_19() const {
float result{}; float result{};
@ -518,7 +518,6 @@ public:
ArithmeticInteger, ArithmeticInteger,
ArithmeticIntegerImmediate, ArithmeticIntegerImmediate,
Bfe, Bfe,
Logic,
Shift, Shift,
Ffma, Ffma,
Flow, Flow,
@ -676,7 +675,7 @@ private:
INST("0100110000000---", Id::BFE_C, Type::Bfe, "BFE_C"), INST("0100110000000---", Id::BFE_C, Type::Bfe, "BFE_C"),
INST("0101110000000---", Id::BFE_R, Type::Bfe, "BFE_R"), INST("0101110000000---", Id::BFE_R, Type::Bfe, "BFE_R"),
INST("0011100-00000---", Id::BFE_IMM, Type::Bfe, "BFE_IMM"), INST("0011100-00000---", Id::BFE_IMM, Type::Bfe, "BFE_IMM"),
INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"), INST("000001----------", Id::LOP32I, Type::ArithmeticIntegerImmediate, "LOP32I"),
INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"), INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"), INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"), INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"),

94
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View file

@ -16,6 +16,7 @@ namespace Decompiler {
using Tegra::Shader::Attribute; using Tegra::Shader::Attribute;
using Tegra::Shader::Instruction; using Tegra::Shader::Instruction;
using Tegra::Shader::LogicOperation;
using Tegra::Shader::OpCode; using Tegra::Shader::OpCode;
using Tegra::Shader::Register; using Tegra::Shader::Register;
using Tegra::Shader::Sampler; using Tegra::Shader::Sampler;
@ -759,6 +760,31 @@ private:
return (absolute_offset % SchedPeriod) == 0; return (absolute_offset % SchedPeriod) == 0;
} }
void WriteLogicOperation(Register dest, LogicOperation logic_op, const std::string& op_a,
const std::string& op_b) {
switch (logic_op) {
case LogicOperation::And: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " & " + op_b + ')', 1, 1);
break;
}
case LogicOperation::Or: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " | " + op_b + ')', 1, 1);
break;
}
case LogicOperation::Xor: {
regs.SetRegisterToInteger(dest, true, 0, '(' + op_a + " ^ " + op_b + ')', 1, 1);
break;
}
case LogicOperation::PassB: {
regs.SetRegisterToInteger(dest, true, 0, op_b, 1, 1);
break;
}
default:
NGLOG_CRITICAL(HW_GPU, "Unimplemented logic operation: {}", static_cast<u32>(logic_op));
UNREACHABLE();
}
}
/** /**
* Compiles a single instruction from Tegra to GLSL. * Compiles a single instruction from Tegra to GLSL.
* @param offset the offset of the Tegra shader instruction. * @param offset the offset of the Tegra shader instruction.
@ -942,55 +968,6 @@ private:
break; break;
} }
case OpCode::Type::Logic: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
if (instr.alu.lop.invert_a)
op_a = "~(" + op_a + ')';
switch (opcode->GetId()) {
case OpCode::Id::LOP32I: {
u32 imm = static_cast<u32>(instr.alu.imm20_32.Value());
if (instr.alu.lop.invert_b)
imm = ~imm;
std::string op_b = std::to_string(imm);
switch (instr.alu.lop.operation) {
case Tegra::Shader::LogicOperation::And: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " & " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Or: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " | " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Xor: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " ^ " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::PassB: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_b, 1, 1);
break;
}
default:
NGLOG_CRITICAL(HW_GPU, "Unimplemented lop32i operation: {}",
static_cast<u32>(instr.alu.lop.operation.Value()));
UNREACHABLE();
}
break;
}
default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled logic instruction: {}", opcode->GetName());
UNREACHABLE();
}
}
break;
}
case OpCode::Type::Shift: { case OpCode::Type::Shift: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true); std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
@ -1036,17 +1013,26 @@ private:
case OpCode::Type::ArithmeticIntegerImmediate: { case OpCode::Type::ArithmeticIntegerImmediate: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
std::string op_b = std::to_string(instr.alu.imm20_32.Value());
if (instr.iadd32i.negate_a)
op_a = '-' + op_a;
std::string op_b = '(' + std::to_string(instr.alu.imm20_32.Value()) + ')';
switch (opcode->GetId()) { switch (opcode->GetId()) {
case OpCode::Id::IADD32I: case OpCode::Id::IADD32I:
if (instr.iadd32i.negate_a)
op_a = "-(" + op_a + ')';
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1, regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.iadd32i.saturate != 0); instr.iadd32i.saturate != 0);
break; break;
case OpCode::Id::LOP32I: {
if (instr.alu.lop32i.invert_a)
op_a = "~(" + op_a + ')';
if (instr.alu.lop32i.invert_b)
op_b = "~(" + op_b + ')';
WriteLogicOperation(instr.gpr0, instr.alu.lop32i.operation, op_a, op_b);
break;
}
default: { default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}", NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}",
opcode->GetName()); opcode->GetName());