From 3a9a0d9cb3e363854d8a59e982247b8fc673ea75 Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Sun, 27 Mar 2022 15:37:06 +0100
Subject: [PATCH 1/2] externals: Update dynarmic
IC instructions now check for a need to halt execution
---
externals/dynarmic | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/externals/dynarmic b/externals/dynarmic
index e1a266b929..af2d50288f 160000
--- a/externals/dynarmic
+++ b/externals/dynarmic
@@ -1 +1 @@
-Subproject commit e1a266b9299be81cc0318c7e25b00388c342704f
+Subproject commit af2d50288fc537201014c4230bb55ab9018a7438
From 1383441b1520f3fca5dc5868240ee21a5308d2cf Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Sun, 27 Mar 2022 15:37:19 +0100
Subject: [PATCH 2/2] arm_dynarmic_64: Invalidate on all cores
---
src/core/arm/dynarmic/arm_dynarmic_64.cpp | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index d96226c41f..24107f9f6f 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -93,17 +93,19 @@ public:
static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
- parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break;
}
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
- parent.ClearInstructionCache();
+ parent.system.InvalidateCpuInstructionCaches();
break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break;
}
+
+ parent.jit->HaltExecution();
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {