mirrors/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-15 22:54:00 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Added better asserts to IPA, Renamed IPA modes to match mesa

Browse source 
IpaMode is changed to IpaInterpMode
IpaMode is suppose to be 2 bits not 3
Added IpaSampleMode
Added Saturate

Renamed modes based on
d27c791891/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp (L2530)
This commit is contained in:
David Marcec 2018-09-01 16:34:27 +10:00
parent c69dc5acf9
commit ad3dca7e62
2 changed files with 13 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/video_core/engines/shader_bytecode.h
View file

@ -243,7 +243,8 @@ enum class TextureType : u64 {
TextureCube = 3, TextureCube = 3,
}; };
enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 }; enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, Flat = 2, Sc = 3 };
enum class IpaSampleMode : u64 { Default = 0, Centroid = 1, Offset = 2 };
union Instruction { union Instruction {
Instruction& operator=(const Instruction& instr) { Instruction& operator=(const Instruction& instr) {
@ -328,7 +329,9 @@ union Instruction {
} alu; } alu;
union { union {
BitField<54, 3, IpaMode> mode; BitField<51, 1, u64> saturate;
BitField<52, 2, IpaSampleMode> sample_mode;
BitField<54, 2, IpaInterpMode> interp_mode;
} ipa; } ipa;
union { union {

12
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View file

@ -2110,8 +2110,12 @@ private:
case OpCode::Id::IPA: { case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28; const auto& attribute = instr.attribute.fmt28;
const auto& reg = instr.gpr0; const auto& reg = instr.gpr0;
switch (instr.ipa.mode) { ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
case Tegra::Shader::IpaMode::Pass: "Unhandled IPA sample mode: {}",
static_cast<u32>(instr.ipa.sample_mode.Value()));
ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
switch (instr.ipa.interp_mode) {
case Tegra::Shader::IpaInterpMode::Linear:
if (stage == Maxwell3D::Regs::ShaderStage::Fragment && if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
attribute.index == Attribute::Index::Position) { attribute.index == Attribute::Index::Position) {
switch (attribute.element) { switch (attribute.element) {
@ -2132,12 +2136,12 @@ private:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
} }
break; break;
case Tegra::Shader::IpaMode::None: case Tegra::Shader::IpaInterpMode::Perspective:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
break; break;
default: default:
LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
static_cast<u32>(instr.ipa.mode.Value())); static_cast<u32>(instr.ipa.interp_mode.Value()));
UNREACHABLE(); UNREACHABLE();
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
} }