mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-11-15 22:54:00 +00:00
Dyncom: Tweak types and log formatting
This commit is contained in:
parent
cb4da3975e
commit
f0a582b218
3 changed files with 10 additions and 8 deletions
|
@ -415,7 +415,7 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
|
||||||
};
|
};
|
||||||
// clang-format on
|
// clang-format on
|
||||||
|
|
||||||
ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
|
ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx) {
|
||||||
int n = 0;
|
int n = 0;
|
||||||
int base = 0;
|
int base = 0;
|
||||||
int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
|
int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
|
||||||
|
|
|
@ -8,7 +8,7 @@
|
||||||
|
|
||||||
enum class ARMDecodeStatus { SUCCESS, FAILURE };
|
enum class ARMDecodeStatus { SUCCESS, FAILURE };
|
||||||
|
|
||||||
ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);
|
ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx);
|
||||||
|
|
||||||
struct InstructionSetEncodingItem {
|
struct InstructionSetEncodingItem {
|
||||||
const char* name;
|
const char* name;
|
||||||
|
|
|
@ -5,6 +5,7 @@
|
||||||
#define CITRA_IGNORE_EXIT(x)
|
#define CITRA_IGNORE_EXIT(x)
|
||||||
|
|
||||||
#include <algorithm>
|
#include <algorithm>
|
||||||
|
#include <cinttypes>
|
||||||
#include <cstdio>
|
#include <cstdio>
|
||||||
#include "common/common_types.h"
|
#include "common/common_types.h"
|
||||||
#include "common/logging/log.h"
|
#include "common/logging/log.h"
|
||||||
|
@ -808,8 +809,8 @@ MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
|
||||||
|
|
||||||
static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
|
static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
|
||||||
ARM_INST_PTR& inst_base) {
|
ARM_INST_PTR& inst_base) {
|
||||||
unsigned int inst_size = 4;
|
u32 inst_size = 4;
|
||||||
unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
|
u32 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
|
||||||
|
|
||||||
// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
|
// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
|
||||||
// instruction
|
// instruction
|
||||||
|
@ -828,10 +829,11 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
|
||||||
int idx;
|
int idx;
|
||||||
if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
|
if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
|
||||||
std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
|
std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
|
||||||
LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr,
|
LOG_ERROR(Core_ARM11,
|
||||||
disasm.c_str(), inst);
|
"Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %s [%08" PRIX32 "]",
|
||||||
LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag,
|
phys_addr, disasm.c_str(), inst);
|
||||||
cpu->Reg[15]);
|
LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
|
||||||
|
cpu->TFlag, cpu->Reg[15]);
|
||||||
CITRA_IGNORE_EXIT(-1);
|
CITRA_IGNORE_EXIT(-1);
|
||||||
}
|
}
|
||||||
inst_base = arm_instruction_trans[idx](inst, idx);
|
inst_base = arm_instruction_trans[idx](inst, idx);
|
||||||
|
|
Loading…
Reference in a new issue