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https://git.suyu.dev/suyu/suyu.git
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Refactor GetTextureCode and GetTexCode to use an optional instead of optional parameters
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parent
4841440382
commit
fd4e994de3
2 changed files with 33 additions and 34 deletions
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@ -54,7 +54,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const auto process_mode = instr.tex.GetTextureProcessMode();
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WriteTexInstructionFloat(
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bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi));
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi, {}));
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break;
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}
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case OpCode::Id::TEX_B: {
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@ -69,9 +69,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const bool is_array = instr.tex_b.array != 0;
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const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex_b.GetTextureProcessMode();
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WriteTexInstructionFloat(bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare,
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is_array, true, instr.gpr20));
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WriteTexInstructionFloat(
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bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, {instr.gpr20}));
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break;
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}
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case OpCode::Id::TEXS: {
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@ -162,10 +162,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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// Sadly, not all texture instructions specify the type of texture their sampler
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// uses. This must be fixed at a later instance.
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const auto& sampler =
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!is_bindless
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? GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false)
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: GetBindlessSampler(instr.gpr8, Tegra::Shader::TextureType::Texture2D, false,
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false);
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is_bindless
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? GetBindlessSampler(instr.gpr8, Tegra::Shader::TextureType::Texture2D, false,
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false)
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: GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false);
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u32 indexer = 0;
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switch (instr.txq.query_type) {
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@ -203,9 +203,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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auto texture_type = instr.tmml.texture_type.Value();
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const bool is_array = instr.tmml.array != 0;
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const auto& sampler = !is_bindless
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? GetSampler(instr.sampler, texture_type, is_array, false)
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: GetBindlessSampler(instr.gpr20, texture_type, is_array, false);
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const auto& sampler = is_bindless
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? GetBindlessSampler(instr.gpr20, texture_type, is_array, false)
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: GetSampler(instr.sampler, texture_type, is_array, false);
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std::vector<Node> coords;
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@ -381,25 +381,26 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
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Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, bool is_bindless,
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Register bindless_reg) {
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Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, std::optional<Tegra::Shader::Register> bindless_reg) {
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const bool is_array = array;
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const bool is_shadow = depth_compare;
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const bool is_bindless = bindless_reg.has_value();
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UNIMPLEMENTED_IF_MSG((texture_type == TextureType::Texture3D && (is_array || is_shadow)) ||
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(texture_type == TextureType::TextureCube && is_array && is_shadow),
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"This method is not supported.");
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const auto& sampler = !is_bindless
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? GetSampler(instr.sampler, texture_type, is_array, is_shadow)
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: GetBindlessSampler(bindless_reg, texture_type, is_array, is_shadow);
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const auto& sampler = is_bindless
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? GetBindlessSampler(*bindless_reg, texture_type, is_array, is_shadow)
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: GetSampler(instr.sampler, texture_type, is_array, is_shadow);
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const bool lod_needed = process_mode == TextureProcessMode::LZ ||
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process_mode == TextureProcessMode::LL ||
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process_mode == TextureProcessMode::LLA;
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// LOD selection (either via bias or explicit textureLod) not supported in GL for
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// sampler2DArrayShadow and samplerCubeArrayShadow.
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// LOD selection (either via bias or explicit textureLod) not
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// supported in GL for sampler2DArrayShadow and
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// samplerCubeArrayShadow.
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const bool gl_lod_supported =
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!((texture_type == Tegra::Shader::TextureType::Texture2D && is_array && is_shadow) ||
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(texture_type == Tegra::Shader::TextureType::TextureCube && is_array && is_shadow));
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@ -417,8 +418,9 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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lod = Immediate(0.0f);
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break;
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case TextureProcessMode::LB:
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// If present, lod or bias are always stored in the register indexed by the gpr20
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// field with an offset depending on the usage of the other registers
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// If present, lod or bias are always stored in the register
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// indexed by the gpr20 field with an offset depending on the
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// usage of the other registers
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bias = GetRegister(instr.gpr20.Value() + bias_offset);
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break;
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case TextureProcessMode::LL:
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@ -442,7 +444,7 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, bool depth_compare, bool is_array,
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bool is_aoffi, bool is_bindless, Register bindless_reg) {
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bool is_aoffi, std::optional<Tegra::Shader::Register> bindless_reg) {
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const bool lod_bias_enabled{
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(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)};
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@ -482,8 +484,7 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
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dc = GetRegister(parameter_register++);
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}
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi, is_bindless,
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bindless_reg);
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi, bindless_reg);
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}
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Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
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@ -769,11 +769,10 @@ private:
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void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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Node4 GetTexCode(
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Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, bool is_array,
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bool is_aoffi, bool is_bindless = false,
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Tegra::Shader::Register bindless_reg = static_cast<Tegra::Shader::Register>(0));
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Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array, bool is_aoffi,
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std::optional<Tegra::Shader::Register> bindless_reg);
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Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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@ -790,12 +789,11 @@ private:
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bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs);
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std::vector<Node> GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count, bool is_tld4);
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Node4 GetTextureCode(
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Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords, Node array,
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Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, bool is_bindless = false,
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Tegra::Shader::Register bindless_reg = static_cast<Tegra::Shader::Register>(0));
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Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi,
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std::optional<Tegra::Shader::Register> bindless_reg);
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Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type,
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u64 byte_height);
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