2017-09-13 00:05:47 +00:00
|
|
|
From 74c6836db73c9361c34dcc9dfd363f5b447d1b30 Mon Sep 17 00:00:00 2001
|
2017-07-05 02:14:49 +00:00
|
|
|
From: Marc Zyngier <Marc.Zyngier@arm.com>
|
|
|
|
|
Date: Sat, 1 Jul 2017 15:16:36 +0100
|
2017-09-13 00:05:47 +00:00
|
|
|
Subject: [PATCH 03/13] ARM64: dts: marvell: armada37xx: Wire PMUv3
|
2017-07-05 02:14:49 +00:00
|
|
|
|
|
|
|
|
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
|
|
|
|
|
a PMUv3, just like most ARMv8 cores.
|
|
|
|
|
|
|
|
|
|
Advertise the PMUv3 presence in the device tree, and wire its
|
|
|
|
|
interrupt. This allows the perf subsystem to work correctly.
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
|
|
|
|
---
|
|
|
|
|
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
|
|
|
|
|
1 file changed, 5 insertions(+)
|
|
|
|
|
|
|
|
|
|
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
2017-09-13 00:05:47 +00:00
|
|
|
index 2dfc09501f9f..d6a060d9f083 100644
|
2017-07-05 02:14:49 +00:00
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
|
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
|
|
|
@@ -81,6 +81,11 @@
|
|
|
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
+ pmu {
|
|
|
|
|
+ compatible = "arm,armv8-pmuv3";
|
|
|
|
|
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
soc {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
--
|
2017-09-13 00:05:47 +00:00
|
|
|
2.14.1
|
2017-07-05 02:14:49 +00:00
|
|
|
|
