2017-07-30 00:45:17 +00:00
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From 54e86a8e68e2ba130e1ed9cbd648901855041e86 Mon Sep 17 00:00:00 2001
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2017-07-13 00:21:51 +00:00
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 24 Mar 2017 20:41:55 +0800
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2017-07-30 00:45:17 +00:00
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Subject: [PATCH 11/12] fix: pcie: aardvark: correct the default MAX payload
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2017-07-13 00:21:51 +00:00
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size
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The previous PCIe MAX payload field is set to 7 which is undefined
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value according to functional specification.
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The default PICe host controller MAX payload size should be
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set to 512 bytes according to specification.
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Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/37926
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 0407c8cb89fb..cac1558b8d3b 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -30,6 +30,7 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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#define PCIE_CORE_MPS_UNIT_BYTE 128
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@@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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--
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2017-07-22 01:34:30 +00:00
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2.13.3
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2017-07-13 00:21:51 +00:00
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