2017-07-30 00:45:17 +00:00
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From 81e63953b87b41ae2aaddb97917ee0cd2e29656e Mon Sep 17 00:00:00 2001
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2017-07-13 00:21:51 +00:00
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From: Victor Gu <xigu@marvell.com>
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Date: Wed, 29 Mar 2017 15:17:03 +0800
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2017-07-30 00:45:17 +00:00
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Subject: [PATCH 08/12] fix: pci: aardvark: disable LOS state by default
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2017-07-13 00:21:51 +00:00
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Some PCIe devices do not support LOS, there will be time out issue
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if the RC forces the LOS state.
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This patch disables the LOS state by default.
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Change-Id: I88a6a5cf58ea5f2df234c99050ce041987cdabc6
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-on: http://vgitil04.il.marvell.com:8080/38119
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Tested-by: iSoC Platform CI <ykjenk@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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---
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drivers/pci/host/pci-aardvark.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 37d0bcd31f8a..072bc70e900c 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_pcie_wait_for_link(pcie);
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- reg = PCIE_CORE_LINK_L0S_ENTRY |
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- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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--
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2017-07-22 01:34:30 +00:00
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2.13.3
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2017-07-13 00:21:51 +00:00
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