2018-02-05 19:53:23 +00:00
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From 2c82a1ee1e896cd5e12f971e142282fc98694ca6 Mon Sep 17 00:00:00 2001
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2017-09-13 00:05:47 +00:00
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From: Evan Wang <xswang@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:47 +0200
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2017-11-13 02:53:28 +00:00
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Subject: [PATCH 7/7] PCI: aardvark: fix PCIe max read request size setting
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2017-09-13 00:05:47 +00:00
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There is an obvious typo issue in the definition of the PCIe maximum
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read request size: a bit shift is directly used as a value, while it
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should be used to shift the correct value.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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2017-11-13 02:53:28 +00:00
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index 5526d83a0c4d..249a088b463c 100644
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2017-09-13 00:05:47 +00:00
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -33,6 +33,7 @@
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
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#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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2017-11-13 02:53:28 +00:00
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@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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2017-09-13 00:05:47 +00:00
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(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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/* Program PCIe Control 2 to disable strict ordering */
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--
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2018-02-05 19:53:23 +00:00
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2.15.0
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2017-09-13 00:05:47 +00:00
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