mirror of
https://github.com/archlinuxarm/PKGBUILDs.git
synced 2025-02-16 23:57:11 +00:00
core/linux-espressobin to 4.17.0-1
This commit is contained in:
Kevin Mihelich
parent
3c45d51cc7
commit
bba7a66597
9 changed files with 137 additions and 503 deletions
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@ -1,7 +1,7 @@
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From b25b7ada12c54ea2670f9145c77d25564a4fb6e9 Mon Sep 17 00:00:00 2001
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From 6fa1b7f42dee531615600a3f0c98402683b19ffe Mon Sep 17 00:00:00 2001
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From: Kevin Mihelich <kevin@archlinuxarm.org>
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Date: Tue, 4 Jul 2017 19:25:28 -0600
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Subject: [PATCH 1/7] arm64: dts: marvell: armada37xx: Add eth0 alias
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Subject: [PATCH 1/3] arm64: dts: marvell: armada37xx: Add eth0 alias
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Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
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---
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@ -9,10 +9,10 @@ Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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index 90c26d616a54..bcf0ac91a14b 100644
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index 97207a61bc79..0d4dd9a4f976 100644
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@@ -54,6 +54,7 @@
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@@ -18,6 +18,7 @@
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#size-cells = <2>;
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aliases {
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@ -21,5 +21,5 @@ index 90c26d616a54..bcf0ac91a14b 100644
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serial1 = &uart1;
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};
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--
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2.15.0
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2.17.0
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@ -1,51 +0,0 @@
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From 97e8d3085e7ca8fa99c6089e459ca04c0425469e Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:42 +0200
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Subject: [PATCH 2/7] PCI: aardvark: fix logic in PCI configuration read/write
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functions
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The PCI configuration space read/write functions were special casing
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the situation where PCI_SLOT(devfn) != 0, and returned
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PCIBIOS_DEVICE_NOT_FOUND in this case.
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However, will this is what is intended for the root bus, it is not
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intended for the child busses, as it prevents discovering devices with
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PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only
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if we're on the root bus.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Wilson Ding <dingwei@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 26ed0c08f209..e591df338bcc 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -440,7 +440,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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u32 reg;
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int ret;
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- if (PCI_SLOT(devfn) != 0) {
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+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0)) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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@@ -494,7 +494,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int offset;
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int ret;
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- if (PCI_SLOT(devfn) != 0)
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+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (where % size)
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--
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2.15.0
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@ -1,7 +1,7 @@
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From 0904a091d796841d61172442258b5ad53b15c571 Mon Sep 17 00:00:00 2001
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From 9865599cadcbaca9e297cce5987f5baef9bb625d Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:44 +0200
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Subject: [PATCH 4/7] PCI: aardvark: set host and device to the same MAX
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Subject: [PATCH 2/3] PCI: aardvark: set host and device to the same MAX
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payload size
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Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
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@ -21,25 +21,26 @@ Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
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drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index 4f2bdb84b97f..ec0cd637fd37 100644
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index 9abf549631b4..a818390852be 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -30,8 +30,10 @@
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@@ -27,9 +27,11 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -297,7 +299,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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@@ -294,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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@ -47,9 +48,9 @@ index 4f2bdb84b97f..ec0cd637fd37 100644
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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@@ -879,6 +882,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
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@@ -883,6 +886,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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return err;
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}
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@ -108,7 +109,7 @@ index 4f2bdb84b97f..ec0cd637fd37 100644
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -952,6 +1007,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
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@@ -956,6 +1011,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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@ -119,5 +120,5 @@ index 4f2bdb84b97f..ec0cd637fd37 100644
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return 0;
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}
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--
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2.15.0
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2.17.0
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@ -1,7 +1,7 @@
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From f25a5f3109846ed3e8074c8119d2a5d91b15d7e8 Mon Sep 17 00:00:00 2001
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From 2bec069bf7b0e95bbde47b3f36b362b9c3429fc1 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:46 +0200
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Subject: [PATCH 6/7] PCI: aardvark: disable LOS state by default
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Subject: [PATCH 3/3] PCI: aardvark: disable LOS state by default
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Some PCIe devices do not support LOS, and will cause timeouts if the
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root complex forces the LOS state. This patch disables the LOS state
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@ -23,10 +23,10 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index c85ead4d5c15..5526d83a0c4d 100644
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index a818390852be..2632c3379349 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -368,8 +368,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_pcie_wait_for_link(pcie);
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@ -37,5 +37,5 @@ index c85ead4d5c15..5526d83a0c4d 100644
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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--
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2.15.0
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2.17.0
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@ -1,38 +0,0 @@
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From 218664e1f7fd4424e04fa937068103c6920a3407 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:43 +0200
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Subject: [PATCH 3/7] PCI: aardvark: set PIO_ADDR_LS correctly in
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advk_pcie_rd_conf()
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When setting the PIO_ADDR_LS register during a configuration read, we
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were properly passing the device number, function number and register
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number, but not the bus number, causing issues when reading the
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configuration of PCIe devices.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Wilson Ding <dingwei@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index e591df338bcc..4f2bdb84b97f 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -459,7 +459,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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advk_writel(pcie, reg, PIO_CTRL);
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/* Program the address registers */
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- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
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+ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
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advk_writel(pcie, reg, PIO_ADDR_LS);
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advk_writel(pcie, 0, PIO_ADDR_MS);
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--
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2.15.0
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@ -1,127 +0,0 @@
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From bd5723f9c5abfb77df49184daddc6c72fc4cc948 Mon Sep 17 00:00:00 2001
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From: Victor Gu <xigu@marvell.com>
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Date: Fri, 8 Sep 2017 11:53:45 +0200
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Subject: [PATCH 5/7] PCI: aardvark: use isr1 instead of isr0 interrupt in
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legacy irq mode
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The Aardvark has two interrupts sets:
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- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)
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- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)
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Only one set should be used, while another set should be masked.
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The second set, ISR1, is more advanced, the Legacy INT_X status bit is
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asserted once Assert_INTX message is received, and de-asserted after
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Deassert_INTX message is received. Therefore, it matches what the
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driver is currently doing in the ->irq_mask() and ->irq_unmask()
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functions. The ISR0 requires additional work to deassert the
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interrupt, which the driver doesn't do currently.
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This commit resolves a number of issues with legacy interrupts.
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This is part of fixing bug
|
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
|
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WiFi card working.
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|
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
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Signed-off-by: Victor Gu <xigu@marvell.com>
|
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Reviewed-by: Evan Wang <xswang@marvell.com>
|
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
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[Thomas: tweak commit log.]
|
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
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---
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drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
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1 file changed, 24 insertions(+), 17 deletions(-)
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diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
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index ec0cd637fd37..c85ead4d5c15 100644
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -105,7 +105,8 @@
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#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
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#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
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#define PCIE_ISR1_FLUSH BIT(5)
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-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
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+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
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+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
|
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#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
|
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
|
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@@ -615,9 +616,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
|
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
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u32 mask;
|
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|
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
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- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
|
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
|
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
|
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}
|
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static void advk_pcie_irq_unmask(struct irq_data *d)
|
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@@ -626,9 +627,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
|
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
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u32 mask;
|
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|
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
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- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
|
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
|
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
|
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+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
|
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
|
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}
|
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|
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static int advk_pcie_irq_map(struct irq_domain *h,
|
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@@ -771,29 +772,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
|
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|
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static void advk_pcie_handle_int(struct advk_pcie *pcie)
|
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{
|
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- u32 val, mask, status;
|
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+ u32 isr0_val, isr0_mask, isr0_status;
|
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+ u32 isr1_val, isr1_mask, isr1_status;
|
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int i, virq;
|
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|
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- val = advk_readl(pcie, PCIE_ISR0_REG);
|
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
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- status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
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+ isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
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+ isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
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+ isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
|
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|
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- if (!status) {
|
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- advk_writel(pcie, val, PCIE_ISR0_REG);
|
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+ isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
|
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+ isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
|
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+ isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
|
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+
|
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+ if (!isr0_status && !isr1_status) {
|
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+ advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
|
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+ advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
|
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return;
|
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}
|
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|
||||
/* Process MSI interrupts */
|
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- if (status & PCIE_ISR0_MSI_INT_PENDING)
|
||||
+ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
|
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advk_pcie_handle_msi(pcie);
|
||||
|
||||
/* Process legacy interrupts */
|
||||
for (i = 0; i < PCI_NUM_INTX; i++) {
|
||||
- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
|
||||
+ if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
|
||||
continue;
|
||||
|
||||
- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
|
||||
- PCIE_ISR0_REG);
|
||||
+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
|
||||
+ PCIE_ISR1_REG);
|
||||
|
||||
virq = irq_find_mapping(pcie->irq_domain, i);
|
||||
generic_handle_irq(virq);
|
||||
--
|
||||
2.15.0
|
||||
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
From 2c82a1ee1e896cd5e12f971e142282fc98694ca6 Mon Sep 17 00:00:00 2001
|
||||
From: Evan Wang <xswang@marvell.com>
|
||||
Date: Fri, 8 Sep 2017 11:53:47 +0200
|
||||
Subject: [PATCH 7/7] PCI: aardvark: fix PCIe max read request size setting
|
||||
|
||||
There is an obvious typo issue in the definition of the PCIe maximum
|
||||
read request size: a bit shift is directly used as a value, while it
|
||||
should be used to shift the correct value.
|
||||
|
||||
This is part of fixing bug
|
||||
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
||||
reported as the user to be important to get a Intel 7260 mini-PCIe
|
||||
WiFi card working.
|
||||
|
||||
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
||||
Signed-off-by: Evan Wang <xswang@marvell.com>
|
||||
Reviewed-by: Victor Gu <xigu@marvell.com>
|
||||
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
||||
[Thomas: tweak commit log.]
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
drivers/pci/host/pci-aardvark.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
|
||||
index 5526d83a0c4d..249a088b463c 100644
|
||||
--- a/drivers/pci/host/pci-aardvark.c
|
||||
+++ b/drivers/pci/host/pci-aardvark.c
|
||||
@@ -33,6 +33,7 @@
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
||||
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
|
||||
#define PCIE_CORE_MPS_UNIT_BYTE 128
|
||||
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
||||
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
||||
@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
||||
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
|
||||
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||||
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
||||
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
|
||||
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
||||
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
||||
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
||||
|
||||
/* Program PCIe Control 2 to disable strict ordering */
|
||||
--
|
||||
2.15.0
|
||||
|
||||
|
|
@ -4,10 +4,10 @@
|
|||
buildarch=8
|
||||
|
||||
pkgbase=linux-espressobin
|
||||
_srcname=linux-4.16
|
||||
_srcname=linux-4.17
|
||||
_kernelname=${pkgbase#linux}
|
||||
_desc="Globalscale ESPRESSOBin"
|
||||
pkgver=4.16.6
|
||||
pkgver=4.17.0
|
||||
pkgrel=1
|
||||
arch=('aarch64')
|
||||
url="http://www.kernel.org/"
|
||||
|
|
@ -15,42 +15,29 @@ license=('GPL2')
|
|||
makedepends=('xmlto' 'docbook-xsl' 'kmod' 'inetutils' 'bc' 'git')
|
||||
options=('!strip')
|
||||
source=("http://www.kernel.org/pub/linux/kernel/v4.x/${_srcname}.tar.xz"
|
||||
"http://www.kernel.org/pub/linux/kernel/v4.x/patch-${pkgver}.xz"
|
||||
#"http://www.kernel.org/pub/linux/kernel/v4.x/patch-${pkgver}.xz"
|
||||
'0001-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch'
|
||||
'0002-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch'
|
||||
'0003-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch'
|
||||
'0004-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch'
|
||||
'0005-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-l.patch'
|
||||
'0006-PCI-aardvark-disable-LOS-state-by-default.patch'
|
||||
'0007-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch'
|
||||
'0002-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch'
|
||||
'0003-PCI-aardvark-disable-LOS-state-by-default.patch'
|
||||
'config'
|
||||
'linux.preset')
|
||||
md5sums=('1357fb4ee7c288fdeac5d4e0048f5c18'
|
||||
'beb8a44d98138e4bfa78cb52097ec91e'
|
||||
'c5c8e2e253ad696a5d6b5d4d01d3325f'
|
||||
'e30c97ac1ee00200e7db2a56b6dd5aa6'
|
||||
'0ce27f3bb59fba94b1db3b4044d6ab2c'
|
||||
'623347a8838c8904a86d33b7ae694409'
|
||||
'5c81578bca3b0eb97115203093b6d480'
|
||||
'37e096efe4b2e8b17787e848a6f629db'
|
||||
'b7662cc111e08d0b518c7837d2bb586d'
|
||||
'6b411f8f55231a57efe38dfeaaa79186'
|
||||
md5sums=('5bb13a03274b66b56c85b26682e407d7'
|
||||
'087a1417d83fa72c2e1cb69ec68ed94d'
|
||||
'960e91f38b59e9d1ce47ec3b4cef3195'
|
||||
'810cc7029cca0741c170209eba2f9dad'
|
||||
'ab50135a41889a2b6e2665d81c75364d'
|
||||
'd8d30aa4a9d4c2b8d4ea53faf46ccf80')
|
||||
|
||||
prepare() {
|
||||
cd "${srcdir}/${_srcname}"
|
||||
|
||||
# add upstream patch
|
||||
git apply --whitespace=nowarn ../patch-${pkgver}
|
||||
#git apply --whitespace=nowarn ../patch-${pkgver}
|
||||
|
||||
# ALARM patches
|
||||
git apply ../0001-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
|
||||
git apply ../0002-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch
|
||||
git apply ../0003-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch
|
||||
git apply ../0004-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch
|
||||
git apply ../0005-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-l.patch
|
||||
git apply ../0006-PCI-aardvark-disable-LOS-state-by-default.patch
|
||||
git apply ../0007-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch
|
||||
git apply ../0002-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch
|
||||
git apply ../0003-PCI-aardvark-disable-LOS-state-by-default.patch
|
||||
|
||||
cat "${srcdir}/config" > ./.config
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Reference in a new issue