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core/linux-aarch64: remove upstreamed patch
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graysky
parent
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commit
eb5d24b5b6
2 changed files with 0 additions and 165 deletions
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@ -20,7 +20,6 @@ source=("http://www.kernel.org/pub/linux/kernel/v6.x/${_srcname}.tar.xz"
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'0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch'
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'0002-arm64-dts-rockchip-disable-pwm0-on-rk3399-firefly.patch'
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'0003-pps-Compatibility-hack-should-be-X86-specific.patch'
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'pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch'
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'config'
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'generate_chromebook_its.sh'
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'kernel.keyblock'
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@ -31,7 +30,6 @@ md5sums=('c0ce046a9a0d041e13cf222f81eae574'
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'7b08a199a97e3e2288e5c03d8e8ded2d'
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'c9d4e392555b77034e24e9f87c5ff0b3'
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'a6abfb191ecb3d7d5f6ccdaca335a11d'
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'd4add3377b26d8b6f0818f7dddfb8cda'
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'ebfcd5d79878361e9d06d45b829a3bd6'
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'7c97cf141750ad810235b1ad06eb9f75'
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'61c5ff73c136ed07a7aadbf58db3d96a'
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@ -53,9 +51,6 @@ prepare() {
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git apply ../0002-arm64-dts-rockchip-disable-pwm0-on-rk3399-firefly.patch
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git apply ../0003-pps-Compatibility-hack-should-be-X86-specific.patch
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# https://archlinuxarm.org/forum/viewtopic.php?f=65&t=16981
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patch -p1 -i ../pinctrl-rockchip-correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch
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cat "${srcdir}/config" > ./.config
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}
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@ -1,160 +0,0 @@
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From patchwork Tue Jul 9 10:54:28 2024
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To: Heiko Stuebner <heiko@sntech.de>,
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Linus Walleij <linus.walleij@linaro.org>
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Cc: Richard Kojedzinszky <richard@kojedz.in>,
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linux-gpio@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org,
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linux-rockchip@lists.infradead.org,
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linux-kernel@vger.kernel.org,
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Huang-Huang Bao <i@eh5.me>,
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stable@vger.kernel.org
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Subject: [PATCH] pinctrl: rockchip: correct RK3328 iomux width flag for
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GPIO2-B pins
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Date: Tue, 9 Jul 2024 18:54:28 +0800
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The base iomux offsets for each GPIO pin line are accumulatively
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calculated based off iomux width flag in rockchip_pinctrl_get_soc_data.
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If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or
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IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8
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bytes, otherwise it would increase by 4 bytes.
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Despite most of GPIO2-B iomux have 2-bit data width, which can be fit
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into 4 bytes space with write mask, it actually take 8 bytes width for
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whole GPIO2-B line.
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Commit e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328
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GPIO2-B pins") wrongly set iomux width flag to 0, causing all base
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iomux offset for line after GPIO2-B to be calculated wrong. Fix the
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iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is
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correctly increased by 8, matching the actual width of GPIO2-B iomux.
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Fixes: e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
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Cc: stable@vger.kernel.org
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Reported-by: Richard Kojedzinszky <richard@kojedz.in>
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Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@kojedz.in/
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Tested-by: Richard Kojedzinszky <richard@kojedz.in>
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Signed-off-by: Huang-Huang Bao <i@eh5.me>
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---
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I have double checked the iomux offsets in debug message match iomux
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register definitions in "GRF Register Description" section in RK3328
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TRM[1].
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[1]: https://opensource.rock-chips.com/images/9/97/Rockchip_RK3328TRM_V1.1-Part1-20170321.pdf
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Kernel pinctrl debug message with dyndbg="file pinctrl-rockchip.c +p":
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rockchip-pinctrl pinctrl: bank 0, iomux 0 has iom_offset 0x0 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 0, iomux 1 has iom_offset 0x4 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 0, iomux 2 has iom_offset 0x8 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 0, iomux 3 has iom_offset 0xc drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 1, iomux 0 has iom_offset 0x10 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 1, iomux 1 has iom_offset 0x14 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 1, iomux 2 has iom_offset 0x18 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 1, iomux 3 has iom_offset 0x1c drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 2, iomux 0 has iom_offset 0x20 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 2, iomux 1 has iom_offset 0x24 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 2, iomux 2 has iom_offset 0x2c drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 2, iomux 3 has iom_offset 0x34 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 3, iomux 0 has iom_offset 0x38 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 3, iomux 1 has iom_offset 0x40 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 3, iomux 2 has iom_offset 0x48 drv_offset 0x0
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rockchip-pinctrl pinctrl: bank 3, iomux 3 has iom_offset 0x4c drv_offset 0x0
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The "Closes" links to test report from original reporter with original
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issue contained, which was not delivered to any mailing list thus not
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available on the web.
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Added CC stable as the problematic e8448a6c817c fixed by this patch was
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recently merged to stable kernels.
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Sorry for the inconvenience caused,
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Huang-Huang
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drivers/pinctrl/pinctrl-rockchip.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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base-commit: 4376e966ecb78c520b0faf239d118ecfab42a119
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--
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2.45.2
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diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
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index 3f56991f5b89..f6da91941fbd 100644
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--- a/drivers/pinctrl/pinctrl-rockchip.c
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+++ b/drivers/pinctrl/pinctrl-rockchip.c
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@@ -3813,7 +3813,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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- 0,
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+ IOMUX_WIDTH_2BIT,
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IOMUX_WIDTH_3BIT,
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0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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