PKGBUILDs/core/linux-espressobin/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch

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2017-09-14 00:33:18 +00:00
From 291969f6c3444515961a1d3f6f99c9323f599b04 Mon Sep 17 00:00:00 2001
2017-07-05 02:14:49 +00:00
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:36 +0100
2017-09-14 00:33:18 +00:00
Subject: [PATCH 02/12] ARM64: dts: marvell: armada37xx: Wire PMUv3
2017-07-05 02:14:49 +00:00
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.
Advertise the PMUv3 presence in the device tree, and wire its
interrupt. This allows the perf subsystem to work correctly.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
2017-09-14 00:33:18 +00:00
index b6f1e7a5e5ec..35307cd93db5 100644
2017-07-05 02:14:49 +00:00
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -81,6 +81,11 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
--
2017-09-13 00:05:47 +00:00
2.14.1
2017-07-05 02:14:49 +00:00