2017-09-14 00:33:18 +00:00
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From 8cb51b7b1fce249f4a064e75f1fb8681906657fc Mon Sep 17 00:00:00 2001
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2017-07-05 02:14:49 +00:00
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From: Marc Zyngier <Marc.Zyngier@arm.com>
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Date: Sat, 1 Jul 2017 15:16:35 +0100
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2017-09-14 00:33:18 +00:00
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Subject: [PATCH 01/12] ARM64: dts: marvell: armada37xx: Enable memory-mapped
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2017-07-13 00:21:51 +00:00
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GIC CPU interface
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2017-07-05 02:14:49 +00:00
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The Cortex-A53s that power the Armada-37xx SoCs are equipped with
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a GIC CPU interface that gets enabled when coupled with a GICv3
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interrupt controller, such as the GIC-500 on the this SoC.
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Advertise the MMIO ranges provided by the CPUs, which enables
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(among other things) GICv2 guests to run under a hypervisor such
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as KVM.
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 ++++-
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1 file changed, 4 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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2017-09-14 00:33:18 +00:00
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index a92ac63addf0..b6f1e7a5e5ec 100644
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2017-07-05 02:14:49 +00:00
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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2017-09-13 00:05:47 +00:00
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@@ -322,7 +322,10 @@
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2017-07-05 02:14:49 +00:00
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1d00000 0x10000>, /* GICD */
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- <0x1d40000 0x40000>; /* GICR */
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+ <0x1d40000 0x40000>, /* GICR */
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+ <0x1d80000 0x2000>, /* GICC */
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+ <0x1d90000 0x2000>, /* GICH */
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+ <0x1da0000 0x20000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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--
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2017-09-13 00:05:47 +00:00
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2.14.1
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2017-07-05 02:14:49 +00:00
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